Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	708	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5434	1			T10	3		T12	3		T13	7
len_601_800	12179	1			T10	8		T12	4		T13	12
len_401_600	8259	1			T10	4		T13	5		T31	11
len_201_400	4630	1			T9	1		T10	1		T12	3
len_65_200	9456	1			T1	75		T13	2		T45	32
len_min_for_xof_require_squeeze	109	1			T50	1		T119	1		T160	9
len_keccak_block_sizes[72]	97	1			T45	1		T160	9		T161	5
len_keccak_block_sizes[104]	96	1			T1	2		T45	1		T160	9
len_keccak_block_sizes[136]	95	1			T1	1		T50	1		T160	9
len_keccak_block_sizes[144]	45	1			T161	5		T162	5		T70	1
len_keccak_block_sizes[168]	52	1			T161	5		T24	1		T162	5
len_datapath_width	1068	1			T1	4		T29	3		T30	3
len_2_63	15108	1			T1	78		T2	105		T3	137
len_1	44	1			T45	1		T50	1		T163	1