Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 284 1 T108 7 T110 4 T135 7
all_values[1] 284 1 T108 7 T110 4 T135 7
all_values[2] 284 1 T108 7 T110 4 T135 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 495 1 T108 13 T110 4 T135 15
auto[1] 357 1 T108 8 T110 8 T135 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 396 1 T108 10 T110 5 T135 6
auto[1] 456 1 T108 11 T110 7 T135 15


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 512 1 T108 12 T110 7 T135 13
auto[1] 340 1 T108 9 T110 5 T135 8


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 72 1 T108 2 T135 1 T136 2
all_values[0] auto[0] auto[0] auto[1] 28 1 T135 2 T137 1 T138 1
all_values[0] auto[0] auto[1] auto[0] 43 1 T108 1 T110 1 T139 1
all_values[0] auto[0] auto[1] auto[1] 31 1 T108 1 T110 1 T135 1
all_values[0] auto[1] auto[0] auto[1] 59 1 T108 1 T135 1 T139 1
all_values[0] auto[1] auto[1] auto[1] 51 1 T108 2 T110 2 T135 2
all_values[1] auto[0] auto[0] auto[0] 99 1 T108 2 T110 1 T135 4
all_values[1] auto[0] auto[1] auto[0] 71 1 T108 3 T110 1 T139 2
all_values[1] auto[1] auto[0] auto[1] 62 1 T108 1 T110 1 T135 1
all_values[1] auto[1] auto[1] auto[1] 52 1 T108 1 T110 1 T135 2
all_values[2] auto[0] auto[0] auto[0] 70 1 T108 2 T135 1 T136 3
all_values[2] auto[0] auto[0] auto[1] 29 1 T108 1 T110 1 T135 3
all_values[2] auto[0] auto[1] auto[0] 41 1 T110 2 T136 1 T139 1
all_values[2] auto[0] auto[1] auto[1] 28 1 T135 1 T140 1 T141 1
all_values[2] auto[1] auto[0] auto[1] 76 1 T108 4 T110 1 T135 2
all_values[2] auto[1] auto[1] auto[1] 40 1 T140 1 T138 1 T142 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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