| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.40 | 97.89 | 92.58 | 99.89 | 78.17 | 95.53 | 98.89 | 97.88 |
| T760 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1635097805 | Sep 09 11:28:19 AM UTC 24 | Sep 09 11:28:23 AM UTC 24 | 401668058 ps | ||
| T761 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.3321657283 | Sep 09 11:28:12 AM UTC 24 | Sep 09 11:28:23 AM UTC 24 | 655127651 ps | ||
| T762 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.418508485 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:23 AM UTC 24 | 154100190 ps | ||
| T763 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1917954445 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:23 AM UTC 24 | 81859383 ps | ||
| T764 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3297938570 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:23 AM UTC 24 | 167953107 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1799263194 | Sep 09 11:28:19 AM UTC 24 | Sep 09 11:28:24 AM UTC 24 | 424604629 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1942140281 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:34 AM UTC 24 | 237377239 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1109268728 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:24 AM UTC 24 | 41228144 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2746303118 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:24 AM UTC 24 | 85547619 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.2978792071 | Sep 09 11:28:29 AM UTC 24 | Sep 09 11:28:39 AM UTC 24 | 33789221 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.2426955142 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 22602494 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3411831124 | Sep 09 11:28:22 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 25373909 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.708354343 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 409075046 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3312627893 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 33911628 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2736255294 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 24727530 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1567887653 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 57410292 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.587125828 | Sep 09 11:28:22 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 27325402 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2800250558 | Sep 09 11:28:22 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 92474012 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1988117644 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 32796845 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.1861898526 | Sep 09 11:28:17 AM UTC 24 | Sep 09 11:28:25 AM UTC 24 | 308002939 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3088062628 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 343503376 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2711782788 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 408545421 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.552838318 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 289810494 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.705488311 | Sep 09 11:28:22 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 107159438 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1928932818 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:33 AM UTC 24 | 173108951 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.3454003777 | Sep 09 11:28:21 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 161117559 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2493626738 | Sep 09 11:28:22 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 147964752 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2941034800 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 124210207 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.877408916 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:26 AM UTC 24 | 13240941 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2310788856 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 1411557432 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2861439924 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 239633595 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2389031330 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 20274322 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2630134552 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 151395492 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1101197371 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 21289625 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1439164534 | Sep 09 11:28:25 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 44534560 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1814840396 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 44148196 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2622764323 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 111154994 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2790919156 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 61641189 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1799421197 | Sep 09 11:28:25 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 25340340 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3541934533 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 86001409 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1108395475 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 307336119 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.4042022889 | Sep 09 11:28:23 AM UTC 24 | Sep 09 11:28:27 AM UTC 24 | 412606663 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1920193102 | Sep 09 11:28:29 AM UTC 24 | Sep 09 11:28:39 AM UTC 24 | 46676809 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2234591615 | Sep 09 11:28:25 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 28909816 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2272930431 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 192523012 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1206777638 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 13191304 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3542966244 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 17724519 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.251638936 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 332565908 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3694939961 | Sep 09 11:28:24 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 302281727 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.266286307 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 25859322 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2263303105 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 58698635 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3821650616 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:28 AM UTC 24 | 311837576 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1325929142 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:29 AM UTC 24 | 27974216 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.1581135411 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:29 AM UTC 24 | 54011553 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1504588311 | Sep 09 11:28:25 AM UTC 24 | Sep 09 11:28:29 AM UTC 24 | 1943882503 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1018879836 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:29 AM UTC 24 | 85872231 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1547932877 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:29 AM UTC 24 | 53658280 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2224250555 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:29 AM UTC 24 | 138638666 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3990386177 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 36859354 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1896800273 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 17450317 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1718015962 | Sep 09 11:28:26 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 119541281 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.479142695 | Sep 09 11:28:29 AM UTC 24 | Sep 09 11:28:40 AM UTC 24 | 29549669 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1767025074 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 58999326 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.4010233814 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:28:34 AM UTC 24 | 41637663 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.70215282 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 16059971 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2096892734 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 54496394 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.47681380 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 19249958 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.406000837 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 258899116 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2344074241 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 53248862 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2497824643 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:30 AM UTC 24 | 69334764 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3305241486 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:31 AM UTC 24 | 56518728 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1928593357 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:31 AM UTC 24 | 26930703 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1296696740 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:31 AM UTC 24 | 76504235 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1917979426 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:31 AM UTC 24 | 251681273 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.940912462 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:31 AM UTC 24 | 214468988 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3687417033 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:31 AM UTC 24 | 100916577 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3285419153 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:31 AM UTC 24 | 132585086 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.4240544967 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:32 AM UTC 24 | 520664220 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2889798946 | Sep 09 11:28:14 AM UTC 24 | Sep 09 11:28:32 AM UTC 24 | 1008195371 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3182878216 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:32 AM UTC 24 | 504412495 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1621745523 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:32 AM UTC 24 | 458340459 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3339128072 | Sep 09 11:28:28 AM UTC 24 | Sep 09 11:28:32 AM UTC 24 | 1160618568 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2778308422 | Sep 09 11:28:15 AM UTC 24 | Sep 09 11:28:36 AM UTC 24 | 5226317570 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1891142754 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:28:35 AM UTC 24 | 95590892 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2838041854 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:28:38 AM UTC 24 | 963081368 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2279739028 | Sep 09 11:28:29 AM UTC 24 | Sep 09 11:28:39 AM UTC 24 | 70442927 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.856896949 | Sep 09 11:28:29 AM UTC 24 | Sep 09 11:28:40 AM UTC 24 | 59742379 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4021306430 | Sep 09 11:28:30 AM UTC 24 | Sep 09 11:28:40 AM UTC 24 | 36631352 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3034477253 | Sep 09 11:28:29 AM UTC 24 | Sep 09 11:28:41 AM UTC 24 | 2138978257 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.768648763 | Sep 09 11:28:29 AM UTC 24 | Sep 09 11:28:42 AM UTC 24 | 681571665 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1936672046 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 28724219 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3413495821 | Sep 09 11:28:35 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 15442364 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2972445121 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 13533551 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3126449846 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 16139278 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.4105037907 | Sep 09 11:28:35 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 30154039 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2306673849 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 24182888 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.260911869 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 37319779 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.197086334 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:44 AM UTC 24 | 54394728 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1697521995 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:28:45 AM UTC 24 | 77933597 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.198655182 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:28:45 AM UTC 24 | 106174345 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.577140102 | Sep 09 11:28:36 AM UTC 24 | Sep 09 11:28:49 AM UTC 24 | 46437930 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.4260809445 | Sep 09 11:28:41 AM UTC 24 | Sep 09 11:28:49 AM UTC 24 | 10969020 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2310448050 | Sep 09 11:28:41 AM UTC 24 | Sep 09 11:28:49 AM UTC 24 | 50860967 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2190072774 | Sep 09 11:28:37 AM UTC 24 | Sep 09 11:28:50 AM UTC 24 | 24368364 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.114901311 | Sep 09 11:28:41 AM UTC 24 | Sep 09 11:28:50 AM UTC 24 | 46701105 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1995562614 | Sep 09 11:28:38 AM UTC 24 | Sep 09 11:28:53 AM UTC 24 | 20470663 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2827963385 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:54 AM UTC 24 | 18310029 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2836275823 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:54 AM UTC 24 | 19967395 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3781405312 | Sep 09 11:28:35 AM UTC 24 | Sep 09 11:28:54 AM UTC 24 | 18502075 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.230009994 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:54 AM UTC 24 | 11332244 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1184275935 | Sep 09 11:28:32 AM UTC 24 | Sep 09 11:28:54 AM UTC 24 | 54772082 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.116826842 | Sep 09 11:28:35 AM UTC 24 | Sep 09 11:28:54 AM UTC 24 | 19554027 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2834029716 | Sep 09 11:28:39 AM UTC 24 | Sep 09 11:28:54 AM UTC 24 | 12676258 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3054001931 | Sep 09 11:28:39 AM UTC 24 | Sep 09 11:28:55 AM UTC 24 | 78226650 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3567214359 | Sep 09 11:28:39 AM UTC 24 | Sep 09 11:28:55 AM UTC 24 | 124625539 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1913141802 | Sep 09 11:28:42 AM UTC 24 | Sep 09 11:28:55 AM UTC 24 | 13048769 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.4085657756 | Sep 09 11:28:42 AM UTC 24 | Sep 09 11:28:55 AM UTC 24 | 202312190 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3375286926 | Sep 09 11:28:30 AM UTC 24 | Sep 09 11:28:55 AM UTC 24 | 90575895 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1769607597 | Sep 09 11:28:30 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 43026106 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2066935628 | Sep 09 11:28:34 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 12381111 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.4026050458 | Sep 09 11:28:34 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 15921098 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2532089675 | Sep 09 11:28:34 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 105349946 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2850505228 | Sep 09 11:28:34 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 59584371 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1712436223 | Sep 09 11:28:34 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 19683220 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.274949225 | Sep 09 11:28:34 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 11189744 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2861626871 | Sep 09 11:28:30 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 162376245 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.640993485 | Sep 09 11:28:30 AM UTC 24 | Sep 09 11:28:56 AM UTC 24 | 575814036 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3590028079 | Sep 09 11:28:30 AM UTC 24 | Sep 09 11:28:58 AM UTC 24 | 404253358 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.4206419801 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:29:10 AM UTC 24 | 15073427 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2149128485 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:29:11 AM UTC 24 | 26741969 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2679333906 | Sep 09 11:28:31 AM UTC 24 | Sep 09 11:29:21 AM UTC 24 | 238445976 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.2919457592 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3717963106 ps |
| CPU time | 78.47 seconds |
| Started | Sep 09 01:52:52 PM UTC 24 |
| Finished | Sep 09 01:54:13 PM UTC 24 |
| Peak memory | 264740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919457592 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2919457592 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.3950786206 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6544706326 ps |
| CPU time | 162.04 seconds |
| Started | Sep 09 01:53:33 PM UTC 24 |
| Finished | Sep 09 01:56:19 PM UTC 24 |
| Peak memory | 332656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950786206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3950786206 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.572861537 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 882306721 ps |
| CPU time | 4.78 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:15 AM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572861537 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.572861537 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.337409042 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2214827698 ps |
| CPU time | 59.6 seconds |
| Started | Sep 09 01:57:07 PM UTC 24 |
| Finished | Sep 09 01:58:09 PM UTC 24 |
| Peak memory | 278280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337409042 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.337409042 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.338210139 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4078062484 ps |
| CPU time | 228.31 seconds |
| Started | Sep 09 01:54:18 PM UTC 24 |
| Finished | Sep 09 01:58:10 PM UTC 24 |
| Peak memory | 295540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=338210139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_ra nd_reset.338210139 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.3488819688 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 77585387516 ps |
| CPU time | 343.95 seconds |
| Started | Sep 09 01:56:06 PM UTC 24 |
| Finished | Sep 09 02:01:54 PM UTC 24 |
| Peak memory | 510572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488819688 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.3488819688 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.1067591156 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 130025727 ps |
| CPU time | 2.06 seconds |
| Started | Sep 09 02:04:56 PM UTC 24 |
| Finished | Sep 09 02:04:59 PM UTC 24 |
| Peak memory | 234048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067591156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1067591156 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.880339766 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 393765134 ps |
| CPU time | 5.58 seconds |
| Started | Sep 09 01:53:58 PM UTC 24 |
| Finished | Sep 09 01:54:05 PM UTC 24 |
| Peak memory | 227880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880339766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.880339766 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_error.2610639573 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5091539976 ps |
| CPU time | 499.75 seconds |
| Started | Sep 09 02:09:57 PM UTC 24 |
| Finished | Sep 09 02:18:23 PM UTC 24 |
| Peak memory | 383556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610639573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2610639573 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4079730421 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 160466032 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:18 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079730421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.4079730421 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.3896761394 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 71495314 ps |
| CPU time | 1.86 seconds |
| Started | Sep 09 01:57:03 PM UTC 24 |
| Finished | Sep 09 01:57:07 PM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896761394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3896761394 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.2012771442 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 161000491 ps |
| CPU time | 3.04 seconds |
| Started | Sep 09 02:22:22 PM UTC 24 |
| Finished | Sep 09 02:22:26 PM UTC 24 |
| Peak memory | 234104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012771442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2012771442 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.1160631588 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 7569064923 ps |
| CPU time | 110.34 seconds |
| Started | Sep 09 02:10:37 PM UTC 24 |
| Finished | Sep 09 02:12:30 PM UTC 24 |
| Peak memory | 236140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160631588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1160631588 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.1494785893 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 152299714 ps |
| CPU time | 1.74 seconds |
| Started | Sep 09 02:04:45 PM UTC 24 |
| Finished | Sep 09 02:04:47 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494785893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1494785893 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1169843952 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 19486412 ps |
| CPU time | 0.83 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:12 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169843952 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1169843952 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.1870310287 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1841242077 ps |
| CPU time | 32.69 seconds |
| Started | Sep 09 02:20:00 PM UTC 24 |
| Finished | Sep 09 02:20:34 PM UTC 24 |
| Peak memory | 250408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870310287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1870310287 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.25806957 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 164176315 ps |
| CPU time | 1.72 seconds |
| Started | Sep 09 01:54:08 PM UTC 24 |
| Finished | Sep 09 01:54:11 PM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25806957 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.25806957 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1911873543 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 405578800 ps |
| CPU time | 2.52 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911873543 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.1911 873543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.254970524 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 32527643 ps |
| CPU time | 2.04 seconds |
| Started | Sep 09 01:54:13 PM UTC 24 |
| Finished | Sep 09 01:54:16 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254970524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.254970524 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.617683783 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 22291470433 ps |
| CPU time | 466.13 seconds |
| Started | Sep 09 01:57:04 PM UTC 24 |
| Finished | Sep 09 02:04:56 PM UTC 24 |
| Peak memory | 367556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617683783 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.617683783 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.3879899666 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 287350802 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 11:28:09 AM UTC 24 |
| Finished | Sep 09 11:28:12 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879899666 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.3879899666 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.2139200985 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 143934519 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 02:24:35 PM UTC 24 |
| Finished | Sep 09 02:24:39 PM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139200985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2139200985 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.1247467514 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 150867011 ps |
| CPU time | 2.15 seconds |
| Started | Sep 09 02:33:58 PM UTC 24 |
| Finished | Sep 09 02:34:02 PM UTC 24 |
| Peak memory | 234044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247467514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1247467514 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.2544070961 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 16707618 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 01:54:47 PM UTC 24 |
| Finished | Sep 09 01:54:49 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544070961 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2544070961 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.1854962435 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 17612244911 ps |
| CPU time | 218.15 seconds |
| Started | Sep 09 01:59:47 PM UTC 24 |
| Finished | Sep 09 02:03:28 PM UTC 24 |
| Peak memory | 367132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854962435 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1854962435 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.3552423972 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 87186881414 ps |
| CPU time | 970.52 seconds |
| Started | Sep 09 01:54:15 PM UTC 24 |
| Finished | Sep 09 02:10:38 PM UTC 24 |
| Peak memory | 394164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552423972 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3552423972 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.2395829330 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 436966298 ps |
| CPU time | 4.05 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:17 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395829330 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.2395829330 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2736255294 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 24727530 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 224908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736255294 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2736255294 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2948363727 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 75798832 ps |
| CPU time | 4.11 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:15 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948363727 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2948363727 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_error.2016120529 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 7160429880 ps |
| CPU time | 315.24 seconds |
| Started | Sep 09 02:24:00 PM UTC 24 |
| Finished | Sep 09 02:29:20 PM UTC 24 |
| Peak memory | 436780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016120529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2016120529 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.877408916 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 13240941 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877408916 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.877408916 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3694939961 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 302281727 ps |
| CPU time | 2.87 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694939961 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3694939961 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3590028079 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 404253358 ps |
| CPU time | 4.08 seconds |
| Started | Sep 09 11:28:30 AM UTC 24 |
| Finished | Sep 09 11:28:58 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590028079 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3590028079 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.125746555 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 102265158 ps |
| CPU time | 4.31 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:18 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125746555 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.125746555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.2887722865 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 16700533752 ps |
| CPU time | 317.05 seconds |
| Started | Sep 09 01:55:01 PM UTC 24 |
| Finished | Sep 09 02:00:23 PM UTC 24 |
| Peak memory | 447068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887722865 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2887722865 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.2485277196 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4829601097 ps |
| CPU time | 204.21 seconds |
| Started | Sep 09 02:30:47 PM UTC 24 |
| Finished | Sep 09 02:34:14 PM UTC 24 |
| Peak memory | 279144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485277196 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2485277196 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.2244286825 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8231442441 ps |
| CPU time | 37.54 seconds |
| Started | Sep 09 01:57:05 PM UTC 24 |
| Finished | Sep 09 01:57:44 PM UTC 24 |
| Peak memory | 261372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2244286825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_r and_reset.2244286825 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.208401341 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1479123706 ps |
| CPU time | 9.98 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208401341 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.208401341 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2635811256 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 191621079 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:12 AM UTC 24 |
| Peak memory | 224276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635811256 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2635811256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4065888703 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 254723008 ps |
| CPU time | 2.29 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:13 AM UTC 24 |
| Peak memory | 229736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4065888703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_ rw_with_rand_reset.4065888703 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2820664823 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 31961473 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:12 AM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820664823 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2820664823 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2002636724 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 30067686 ps |
| CPU time | 0.82 seconds |
| Started | Sep 09 11:28:09 AM UTC 24 |
| Finished | Sep 09 11:28:11 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002636724 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2002636724 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2679767216 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 111051879 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:13 AM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679767216 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.2679767216 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1604320230 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 221178234 ps |
| CPU time | 1.76 seconds |
| Started | Sep 09 11:28:08 AM UTC 24 |
| Finished | Sep 09 11:28:10 AM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604320230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1604320230 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1715849917 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 55581260 ps |
| CPU time | 1.88 seconds |
| Started | Sep 09 11:28:09 AM UTC 24 |
| Finished | Sep 09 11:28:12 AM UTC 24 |
| Peak memory | 224436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715849917 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.1715 849917 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.3211918780 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 255982745 ps |
| CPU time | 3.65 seconds |
| Started | Sep 09 11:28:09 AM UTC 24 |
| Finished | Sep 09 11:28:14 AM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211918780 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3211918780 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2062025705 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 942871068 ps |
| CPU time | 8.85 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062025705 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2062025705 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.3321657283 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 655127651 ps |
| CPU time | 9.6 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321657283 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3321657283 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.163618932 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 44235383 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:14 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163618932 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.163618932 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1841371409 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 66720274 ps |
| CPU time | 2.31 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:15 AM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1841371409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_ rw_with_rand_reset.1841371409 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.3702308118 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 15126257 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:14 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702308118 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3702308118 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.658412365 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 21470537 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:14 AM UTC 24 |
| Peak memory | 224608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658412365 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.658412365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.3604466811 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 16930569 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:14 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604466811 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.3604466811 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2196824491 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 36827577 ps |
| CPU time | 0.9 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:12 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196824491 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2196824491 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2209615246 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 126228466 ps |
| CPU time | 1.51 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:15 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209615246 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.2209615246 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.183106699 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 64891811 ps |
| CPU time | 1.74 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:13 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183106699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.183106699 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3641499933 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 166860058 ps |
| CPU time | 2.71 seconds |
| Started | Sep 09 11:28:10 AM UTC 24 |
| Finished | Sep 09 11:28:14 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641499933 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.3641 499933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.414293776 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 160966137 ps |
| CPU time | 3.75 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414293776 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.414293776 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2861439924 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 239633595 ps |
| CPU time | 2.56 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 231260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2861439924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem _rw_with_rand_reset.2861439924 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1988117644 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 32796845 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988117644 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1988117644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2310788856 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1411557432 ps |
| CPU time | 2.46 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 225052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310788856 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.2310788856 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1567887653 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 57410292 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567887653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.1567887653 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.552838318 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 289810494 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552838318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.5528 38318 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2790919156 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 61641189 ps |
| CPU time | 3.29 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790919156 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2790919156 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2630134552 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 151395492 ps |
| CPU time | 2.67 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630134552 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2630134552 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1108395475 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 307336119 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1108395475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem _rw_with_rand_reset.1108395475 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1101197371 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 21289625 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101197371 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1101197371 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2622764323 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 111154994 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622764323 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.2622764323 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1814840396 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 44148196 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 224212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814840396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1814840396 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2272930431 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 192523012 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272930431 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.227 2930431 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3541934533 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 86001409 ps |
| CPU time | 1.7 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541934533 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3541934533 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1018879836 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 85872231 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:29 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1018879836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem _rw_with_rand_reset.1018879836 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1206777638 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 13191304 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 223912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206777638 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1206777638 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1439164534 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 44534560 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 11:28:25 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439164534 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1439164534 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.266286307 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 25859322 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266286307 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.266286307 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2389031330 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 20274322 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 11:28:24 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 224432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389031330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2389031330 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1799421197 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 25340340 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 11:28:25 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799421197 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.179 9421197 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2234591615 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 28909816 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 11:28:25 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234591615 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2234591615 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1504588311 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1943882503 ps |
| CPU time | 3.25 seconds |
| Started | Sep 09 11:28:25 AM UTC 24 |
| Finished | Sep 09 11:28:29 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504588311 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1504588311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3990386177 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 36859354 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3990386177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem _rw_with_rand_reset.3990386177 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2263303105 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 58698635 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 224548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263303105 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2263303105 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3542966244 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 17724519 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542966244 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3542966244 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1325929142 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 27974216 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:29 AM UTC 24 |
| Peak memory | 224276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325929142 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.1325929142 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.251638936 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 332565908 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251638936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.251638936 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2224250555 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 138638666 ps |
| CPU time | 2.32 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:29 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224250555 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.222 4250555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.1581135411 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 54011553 ps |
| CPU time | 1.84 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:29 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581135411 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1581135411 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1718015962 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 119541281 ps |
| CPU time | 2.47 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718015962 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1718015962 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1917979426 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 251681273 ps |
| CPU time | 2.13 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:31 AM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1917979426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem _rw_with_rand_reset.1917979426 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.70215282 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 16059971 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 223932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70215282 -assert nopostproc +UVM_TESTNAME=km ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.70215282 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1896800273 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 17450317 ps |
| CPU time | 0.78 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896800273 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1896800273 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.406000837 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 258899116 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406000837 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.406000837 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3821650616 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 311837576 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:28 AM UTC 24 |
| Peak memory | 224432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821650616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3821650616 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1547932877 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 53658280 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 11:28:26 AM UTC 24 |
| Finished | Sep 09 11:28:29 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547932877 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.154 7932877 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3687417033 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 100916577 ps |
| CPU time | 2.48 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:31 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687417033 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3687417033 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.4240544967 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 520664220 ps |
| CPU time | 2.75 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:32 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240544967 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.4240544967 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3285419153 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 132585086 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:31 AM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3285419153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem _rw_with_rand_reset.3285419153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2096892734 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 54496394 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096892734 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2096892734 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1767025074 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 58999326 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767025074 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1767025074 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1928593357 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 26930703 ps |
| CPU time | 1.51 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:31 AM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928593357 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1928593357 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2344074241 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 53248862 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344074241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2344074241 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1296696740 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 76504235 ps |
| CPU time | 1.94 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:31 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296696740 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.129 6696740 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1928932818 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 173108951 ps |
| CPU time | 3.94 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:33 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928932818 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1928932818 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.940912462 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 214468988 ps |
| CPU time | 2.17 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:31 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940912462 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.940912462 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.856896949 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 59742379 ps |
| CPU time | 2.04 seconds |
| Started | Sep 09 11:28:29 AM UTC 24 |
| Finished | Sep 09 11:28:40 AM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=856896949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_ rw_with_rand_reset.856896949 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2497824643 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 69334764 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497824643 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2497824643 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.47681380 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 19249958 ps |
| CPU time | 0.71 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:30 AM UTC 24 |
| Peak memory | 224384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47681380 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.47681380 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3339128072 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1160618568 ps |
| CPU time | 2.45 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:32 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339128072 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.3339128072 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3305241486 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 56518728 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:31 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305241486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.3305241486 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1621745523 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 458340459 ps |
| CPU time | 2.83 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:32 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621745523 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.162 1745523 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3182878216 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 504412495 ps |
| CPU time | 2.65 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:32 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182878216 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3182878216 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1942140281 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 237377239 ps |
| CPU time | 4.28 seconds |
| Started | Sep 09 11:28:28 AM UTC 24 |
| Finished | Sep 09 11:28:34 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942140281 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1942140281 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1769607597 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 43026106 ps |
| CPU time | 1.58 seconds |
| Started | Sep 09 11:28:30 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 228600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1769607597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem _rw_with_rand_reset.1769607597 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.2978792071 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 33789221 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 11:28:29 AM UTC 24 |
| Finished | Sep 09 11:28:39 AM UTC 24 |
| Peak memory | 224476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978792071 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2978792071 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1920193102 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 46676809 ps |
| CPU time | 0.81 seconds |
| Started | Sep 09 11:28:29 AM UTC 24 |
| Finished | Sep 09 11:28:39 AM UTC 24 |
| Peak memory | 224848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920193102 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1920193102 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4021306430 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 36631352 ps |
| CPU time | 1.89 seconds |
| Started | Sep 09 11:28:30 AM UTC 24 |
| Finished | Sep 09 11:28:40 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021306430 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.4021306430 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2279739028 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 70442927 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 11:28:29 AM UTC 24 |
| Finished | Sep 09 11:28:39 AM UTC 24 |
| Peak memory | 226480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279739028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2279739028 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3034477253 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2138978257 ps |
| CPU time | 3.23 seconds |
| Started | Sep 09 11:28:29 AM UTC 24 |
| Finished | Sep 09 11:28:41 AM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034477253 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.303 4477253 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.479142695 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 29549669 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 11:28:29 AM UTC 24 |
| Finished | Sep 09 11:28:40 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479142695 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.479142695 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.768648763 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 681571665 ps |
| CPU time | 4.32 seconds |
| Started | Sep 09 11:28:29 AM UTC 24 |
| Finished | Sep 09 11:28:42 AM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768648763 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.768648763 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.4206419801 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 15073427 ps |
| CPU time | 0.82 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:29:10 AM UTC 24 |
| Peak memory | 224904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206419801 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.4206419801 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2149128485 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 26741969 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:29:11 AM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149128485 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.2149128485 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3375286926 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 90575895 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 11:28:30 AM UTC 24 |
| Finished | Sep 09 11:28:55 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375286926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.3375286926 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.640993485 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 575814036 ps |
| CPU time | 2.43 seconds |
| Started | Sep 09 11:28:30 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640993485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.6409 93485 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2861626871 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 162376245 ps |
| CPU time | 2.2 seconds |
| Started | Sep 09 11:28:30 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861626871 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2861626871 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.198655182 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 106174345 ps |
| CPU time | 2.13 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:28:45 AM UTC 24 |
| Peak memory | 231820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=198655182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_ rw_with_rand_reset.198655182 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2306673849 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 24182888 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306673849 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2306673849 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.4010233814 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 41637663 ps |
| CPU time | 0.71 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:28:34 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010233814 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.4010233814 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1891142754 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 95590892 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:28:35 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891142754 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1891142754 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2679333906 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 238445976 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:29:21 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679333906 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.267 9333906 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1697521995 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 77933597 ps |
| CPU time | 2 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:28:45 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697521995 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1697521995 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2838041854 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 963081368 ps |
| CPU time | 4.42 seconds |
| Started | Sep 09 11:28:31 AM UTC 24 |
| Finished | Sep 09 11:28:38 AM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838041854 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2838041854 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.230322609 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 78363823 ps |
| CPU time | 4.21 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230322609 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.230322609 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2889798946 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1008195371 ps |
| CPU time | 16.96 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:32 AM UTC 24 |
| Peak memory | 225744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889798946 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2889798946 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.2540750241 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 28186570 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540750241 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2540750241 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.666225298 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 162974612 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:17 AM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=666225298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_r w_with_rand_reset.666225298 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1122617226 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 170878297 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122617226 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1122617226 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3803357378 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 30085441 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803357378 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3803357378 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.4033923570 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 41756522 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:15 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033923570 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.4033923570 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2164065621 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 22713686 ps |
| CPU time | 0.9 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:14 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164065621 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2164065621 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3993986547 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 91157859 ps |
| CPU time | 1.58 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:17 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993986547 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3993986547 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4000147520 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 45067598 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:15 AM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000147520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.4000147520 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.445644200 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 28554789 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:15 AM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445644200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.44564 4200 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.425514672 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 46625693 ps |
| CPU time | 2.3 seconds |
| Started | Sep 09 11:28:12 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425514672 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.425514672 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1936672046 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 28724219 ps |
| CPU time | 0.75 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936672046 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1936672046 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3126449846 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 16139278 ps |
| CPU time | 0.74 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126449846 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3126449846 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.197086334 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 54394728 ps |
| CPU time | 0.71 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197086334 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.197086334 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.260911869 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 37319779 ps |
| CPU time | 0.69 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 224964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260911869 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.260911869 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.1184275935 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 54772082 ps |
| CPU time | 0.77 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:54 AM UTC 24 |
| Peak memory | 224184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184275935 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1184275935 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.230009994 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 11332244 ps |
| CPU time | 0.75 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:54 AM UTC 24 |
| Peak memory | 224412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230009994 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.230009994 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2836275823 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 19967395 ps |
| CPU time | 0.7 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:54 AM UTC 24 |
| Peak memory | 224216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836275823 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2836275823 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2972445121 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 13533551 ps |
| CPU time | 0.7 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972445121 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2972445121 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2827963385 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 18310029 ps |
| CPU time | 0.71 seconds |
| Started | Sep 09 11:28:32 AM UTC 24 |
| Finished | Sep 09 11:28:54 AM UTC 24 |
| Peak memory | 224384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827963385 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2827963385 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1712436223 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 19683220 ps |
| CPU time | 0.78 seconds |
| Started | Sep 09 11:28:34 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712436223 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1712436223 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1442754593 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 287857332 ps |
| CPU time | 4.25 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442754593 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1442754593 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2778308422 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5226317570 ps |
| CPU time | 19.2 seconds |
| Started | Sep 09 11:28:15 AM UTC 24 |
| Finished | Sep 09 11:28:36 AM UTC 24 |
| Peak memory | 225744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778308422 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2778308422 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.1162092462 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 56854126 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 11:28:15 AM UTC 24 |
| Finished | Sep 09 11:28:17 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162092462 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1162092462 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.445367994 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 144957351 ps |
| CPU time | 2.41 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=445367994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_r w_with_rand_reset.445367994 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.4128907571 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 39725894 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 11:28:15 AM UTC 24 |
| Finished | Sep 09 11:28:17 AM UTC 24 |
| Peak memory | 224384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128907571 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4128907571 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3717042198 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 29539230 ps |
| CPU time | 0.79 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 224388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717042198 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3717042198 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.1747143106 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 33457470 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747143106 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.1747143106 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.384462022 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 20039801 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384462022 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.384462022 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2990053879 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 67596416 ps |
| CPU time | 2.23 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990053879 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2990053879 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.879548549 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 17812068 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:16 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879548549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.879548549 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1214601894 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 234056193 ps |
| CPU time | 1.83 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:17 AM UTC 24 |
| Peak memory | 224276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214601894 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.1214 601894 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1182339047 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 50104890 ps |
| CPU time | 2.79 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:18 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182339047 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1182339047 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.2365682751 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 234621135 ps |
| CPU time | 2.35 seconds |
| Started | Sep 09 11:28:14 AM UTC 24 |
| Finished | Sep 09 11:28:18 AM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365682751 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.2365682751 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2066935628 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 12381111 ps |
| CPU time | 0.7 seconds |
| Started | Sep 09 11:28:34 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066935628 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2066935628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.4026050458 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 15921098 ps |
| CPU time | 0.75 seconds |
| Started | Sep 09 11:28:34 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026050458 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.4026050458 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2850505228 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 59584371 ps |
| CPU time | 0.73 seconds |
| Started | Sep 09 11:28:34 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850505228 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2850505228 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2532089675 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 105349946 ps |
| CPU time | 0.73 seconds |
| Started | Sep 09 11:28:34 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532089675 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2532089675 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.274949225 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 11189744 ps |
| CPU time | 0.75 seconds |
| Started | Sep 09 11:28:34 AM UTC 24 |
| Finished | Sep 09 11:28:56 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274949225 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.274949225 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.4105037907 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 30154039 ps |
| CPU time | 0.66 seconds |
| Started | Sep 09 11:28:35 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105037907 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.4105037907 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3413495821 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 15442364 ps |
| CPU time | 0.69 seconds |
| Started | Sep 09 11:28:35 AM UTC 24 |
| Finished | Sep 09 11:28:44 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413495821 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3413495821 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3781405312 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 18502075 ps |
| CPU time | 0.68 seconds |
| Started | Sep 09 11:28:35 AM UTC 24 |
| Finished | Sep 09 11:28:54 AM UTC 24 |
| Peak memory | 224548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781405312 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3781405312 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.116826842 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 19554027 ps |
| CPU time | 0.74 seconds |
| Started | Sep 09 11:28:35 AM UTC 24 |
| Finished | Sep 09 11:28:54 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116826842 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.116826842 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.577140102 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 46437930 ps |
| CPU time | 0.71 seconds |
| Started | Sep 09 11:28:36 AM UTC 24 |
| Finished | Sep 09 11:28:49 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577140102 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.577140102 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.42784453 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1934843515 ps |
| CPU time | 4.67 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42784453 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.42784453 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.1861898526 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 308002939 ps |
| CPU time | 7.28 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861898526 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1861898526 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.4084093277 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 28946853 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084093277 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.4084093277 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1718102445 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 283700349 ps |
| CPU time | 3.22 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1718102445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_ rw_with_rand_reset.1718102445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.3913285496 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 94045928 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913285496 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3913285496 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2115096241 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 14663256 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:18 AM UTC 24 |
| Peak memory | 224388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115096241 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2115096241 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.958281372 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 134510614 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:18 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958281372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.958281372 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3433851838 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 14228611 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:18 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433851838 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3433851838 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.254207613 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 197029561 ps |
| CPU time | 3.04 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254207613 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.254207613 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.709990219 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 170057348 ps |
| CPU time | 2.73 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709990219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.70999 0219 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3953585341 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 59582640 ps |
| CPU time | 2.23 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953585341 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3953585341 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.4245019566 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 304988032 ps |
| CPU time | 4.8 seconds |
| Started | Sep 09 11:28:16 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245019566 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.4245019566 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2190072774 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 24368364 ps |
| CPU time | 0.69 seconds |
| Started | Sep 09 11:28:37 AM UTC 24 |
| Finished | Sep 09 11:28:50 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190072774 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2190072774 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1995562614 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 20470663 ps |
| CPU time | 0.73 seconds |
| Started | Sep 09 11:28:38 AM UTC 24 |
| Finished | Sep 09 11:28:53 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995562614 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1995562614 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2834029716 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 12676258 ps |
| CPU time | 0.71 seconds |
| Started | Sep 09 11:28:39 AM UTC 24 |
| Finished | Sep 09 11:28:54 AM UTC 24 |
| Peak memory | 224480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834029716 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2834029716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3567214359 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 124625539 ps |
| CPU time | 0.74 seconds |
| Started | Sep 09 11:28:39 AM UTC 24 |
| Finished | Sep 09 11:28:55 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567214359 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3567214359 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3054001931 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 78226650 ps |
| CPU time | 0.75 seconds |
| Started | Sep 09 11:28:39 AM UTC 24 |
| Finished | Sep 09 11:28:55 AM UTC 24 |
| Peak memory | 224892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054001931 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3054001931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.4260809445 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 10969020 ps |
| CPU time | 0.67 seconds |
| Started | Sep 09 11:28:41 AM UTC 24 |
| Finished | Sep 09 11:28:49 AM UTC 24 |
| Peak memory | 223900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260809445 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.4260809445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2310448050 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 50860967 ps |
| CPU time | 0.73 seconds |
| Started | Sep 09 11:28:41 AM UTC 24 |
| Finished | Sep 09 11:28:49 AM UTC 24 |
| Peak memory | 224848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310448050 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2310448050 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.114901311 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 46701105 ps |
| CPU time | 0.67 seconds |
| Started | Sep 09 11:28:41 AM UTC 24 |
| Finished | Sep 09 11:28:50 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114901311 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.114901311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1913141802 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 13048769 ps |
| CPU time | 0.71 seconds |
| Started | Sep 09 11:28:42 AM UTC 24 |
| Finished | Sep 09 11:28:55 AM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913141802 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1913141802 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.4085657756 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 202312190 ps |
| CPU time | 0.72 seconds |
| Started | Sep 09 11:28:42 AM UTC 24 |
| Finished | Sep 09 11:28:55 AM UTC 24 |
| Peak memory | 224536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085657756 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.4085657756 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.373054808 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 110610735 ps |
| CPU time | 2.45 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=373054808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_r w_with_rand_reset.373054808 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.964838018 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 23161275 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:20 AM UTC 24 |
| Peak memory | 224388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964838018 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.964838018 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1867753306 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 38406211 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:19 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867753306 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1867753306 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.657171524 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 40986575 ps |
| CPU time | 2.3 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657171524 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.657171524 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1845741198 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 84081171 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:20 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845741198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.1845741198 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.385176862 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 222726130 ps |
| CPU time | 2.97 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385176862 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.385176862 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3165563204 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 208947701 ps |
| CPU time | 2.31 seconds |
| Started | Sep 09 11:28:17 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165563204 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.3165563204 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3944110360 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 163416661 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3944110360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_ rw_with_rand_reset.3944110360 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.1746739059 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 126417360 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746739059 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1746739059 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.1198359405 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 12022496 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 224276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198359405 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1198359405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1635097805 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 401668058 ps |
| CPU time | 2.5 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635097805 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1635097805 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.4154025719 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 88130198 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:21 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154025719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.4154025719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.40961886 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 168695272 ps |
| CPU time | 2.15 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40961886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.409618 86 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.3028701683 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 98670039 ps |
| CPU time | 3.29 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028701683 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3028701683 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1799263194 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 424604629 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:24 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799263194 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.1799263194 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2746303118 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 85547619 ps |
| CPU time | 2.55 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:24 AM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2746303118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_ rw_with_rand_reset.2746303118 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.4081032194 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 81421373 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081032194 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.4081032194 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3183471902 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 31519993 ps |
| CPU time | 0.84 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 224844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183471902 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3183471902 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3297938570 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 167953107 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297938570 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3297938570 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2758742606 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 300962707 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758742606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2758742606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2113186791 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 32227872 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113186791 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.2113 186791 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1623540843 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 105503646 ps |
| CPU time | 1.86 seconds |
| Started | Sep 09 11:28:19 AM UTC 24 |
| Finished | Sep 09 11:28:22 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623540843 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1623540843 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3088062628 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 343503376 ps |
| CPU time | 3.82 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088062628 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.3088062628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2800250558 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 92474012 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 11:28:22 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 226164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2800250558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_ rw_with_rand_reset.2800250558 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.418508485 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 154100190 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418508485 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.418508485 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1418825101 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 59365905 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 224852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418825101 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1418825101 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.587125828 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 27325402 ps |
| CPU time | 1.57 seconds |
| Started | Sep 09 11:28:22 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587125828 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.587125828 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1917954445 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 81859383 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:23 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917954445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1917954445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1109268728 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 41228144 ps |
| CPU time | 2.21 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:24 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109268728 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.1109 268728 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.3454003777 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 161117559 ps |
| CPU time | 3.99 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454003777 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3454003777 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.708354343 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 409075046 ps |
| CPU time | 2.75 seconds |
| Started | Sep 09 11:28:21 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708354343 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.708354343 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2711782788 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 408545421 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 228596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2711782788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_ rw_with_rand_reset.2711782788 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3312627893 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 33911628 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 223840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312627893 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3312627893 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.2426955142 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 22602494 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426955142 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2426955142 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2941034800 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 124210207 ps |
| CPU time | 2.59 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941034800 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.2941034800 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3411831124 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 25373909 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 11:28:22 AM UTC 24 |
| Finished | Sep 09 11:28:25 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411831124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.3411831124 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2493626738 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 147964752 ps |
| CPU time | 2.51 seconds |
| Started | Sep 09 11:28:22 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493626738 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.2493 626738 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.705488311 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 107159438 ps |
| CPU time | 2.23 seconds |
| Started | Sep 09 11:28:22 AM UTC 24 |
| Finished | Sep 09 11:28:26 AM UTC 24 |
| Peak memory | 224960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705488311 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.705488311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.4042022889 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 412606663 ps |
| CPU time | 3.85 seconds |
| Started | Sep 09 11:28:23 AM UTC 24 |
| Finished | Sep 09 11:28:27 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042022889 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.4042022889 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_app.800495870 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 43451216826 ps |
| CPU time | 125.07 seconds |
| Started | Sep 09 01:52:50 PM UTC 24 |
| Finished | Sep 09 01:54:58 PM UTC 24 |
| Peak memory | 295524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800495870 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.800495870 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.1857956026 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 43832918570 ps |
| CPU time | 580.76 seconds |
| Started | Sep 09 01:49:24 PM UTC 24 |
| Finished | Sep 09 01:59:13 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857956026 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1857956026 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3432391437 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 493500422 ps |
| CPU time | 39.46 seconds |
| Started | Sep 09 01:54:05 PM UTC 24 |
| Finished | Sep 09 01:54:46 PM UTC 24 |
| Peak memory | 235956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432391437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3432391437 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.2208543542 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 34936642 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 01:54:11 PM UTC 24 |
| Finished | Sep 09 01:54:14 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208543542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2208543542 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3720626195 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 959103663 ps |
| CPU time | 6.97 seconds |
| Started | Sep 09 01:53:24 PM UTC 24 |
| Finished | Sep 09 01:53:33 PM UTC 24 |
| Peak memory | 232092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720626195 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3720626195 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_error.3751100363 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1221371869 ps |
| CPU time | 57.35 seconds |
| Started | Sep 09 01:53:42 PM UTC 24 |
| Finished | Sep 09 01:54:41 PM UTC 24 |
| Peak memory | 268772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751100363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3751100363 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.31511800 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 69876757512 ps |
| CPU time | 1561.76 seconds |
| Started | Sep 09 01:49:06 PM UTC 24 |
| Finished | Sep 09 02:15:27 PM UTC 24 |
| Peak memory | 1835560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31511800 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.31511800 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.2559725553 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3634044780 ps |
| CPU time | 46.14 seconds |
| Started | Sep 09 01:54:43 PM UTC 24 |
| Finished | Sep 09 01:55:30 PM UTC 24 |
| Peak memory | 278260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559725553 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2559725553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.3838570839 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 70034253125 ps |
| CPU time | 768.88 seconds |
| Started | Sep 09 01:49:09 PM UTC 24 |
| Finished | Sep 09 02:02:08 PM UTC 24 |
| Peak memory | 637512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838570839 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.3838570839 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.2210850499 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1645248562 ps |
| CPU time | 94.8 seconds |
| Started | Sep 09 01:48:54 PM UTC 24 |
| Finished | Sep 09 01:50:31 PM UTC 24 |
| Peak memory | 235992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210850499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2210850499 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.2455903349 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 739755789 ps |
| CPU time | 4.22 seconds |
| Started | Sep 09 01:52:38 PM UTC 24 |
| Finished | Sep 09 01:52:43 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455903349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.2455903349 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3164949614 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 116104657 ps |
| CPU time | 4.47 seconds |
| Started | Sep 09 01:52:44 PM UTC 24 |
| Finished | Sep 09 01:52:50 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164949614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3164949614 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.1296135907 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 64169724444 ps |
| CPU time | 1938.42 seconds |
| Started | Sep 09 01:49:39 PM UTC 24 |
| Finished | Sep 09 02:22:20 PM UTC 24 |
| Peak memory | 1143332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296135907 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1296135907 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2922807463 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4225253680 ps |
| CPU time | 51.87 seconds |
| Started | Sep 09 01:50:01 PM UTC 24 |
| Finished | Sep 09 01:50:55 PM UTC 24 |
| Peak memory | 234216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922807463 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2922807463 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.683193686 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 863332980 ps |
| CPU time | 39.48 seconds |
| Started | Sep 09 01:50:08 PM UTC 24 |
| Finished | Sep 09 01:50:49 PM UTC 24 |
| Peak memory | 230000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683193686 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.683193686 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.1011948482 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 9569176651 ps |
| CPU time | 1290.17 seconds |
| Started | Sep 09 01:50:32 PM UTC 24 |
| Finished | Sep 09 02:12:19 PM UTC 24 |
| Peak memory | 709052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011948482 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1011948482 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.4201142941 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 21390058084 ps |
| CPU time | 2363.51 seconds |
| Started | Sep 09 01:50:51 PM UTC 24 |
| Finished | Sep 09 02:30:40 PM UTC 24 |
| Peak memory | 1317420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201142941 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.4201142941 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.1104707634 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 244180186887 ps |
| CPU time | 2663.94 seconds |
| Started | Sep 09 01:50:56 PM UTC 24 |
| Finished | Sep 09 02:35:50 PM UTC 24 |
| Peak memory | 3039792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104707634 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1104707634 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.3260631867 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 37346740 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 01:57:10 PM UTC 24 |
| Finished | Sep 09 01:57:12 PM UTC 24 |
| Peak memory | 225164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260631867 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3260631867 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_app.313383058 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6030495251 ps |
| CPU time | 41.04 seconds |
| Started | Sep 09 01:56:01 PM UTC 24 |
| Finished | Sep 09 01:56:44 PM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313383058 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.313383058 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.340001760 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4923981525 ps |
| CPU time | 181.03 seconds |
| Started | Sep 09 01:56:04 PM UTC 24 |
| Finished | Sep 09 01:59:08 PM UTC 24 |
| Peak memory | 320032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340001760 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.340001760 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.169460966 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4504252781 ps |
| CPU time | 280.1 seconds |
| Started | Sep 09 01:55:01 PM UTC 24 |
| Finished | Sep 09 01:59:46 PM UTC 24 |
| Peak memory | 248464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169460966 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.169460966 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.3626546729 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 502048521 ps |
| CPU time | 15.08 seconds |
| Started | Sep 09 01:56:45 PM UTC 24 |
| Finished | Sep 09 01:57:01 PM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626546729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3626546729 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.98097516 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 62983866 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 01:57:01 PM UTC 24 |
| Finished | Sep 09 01:57:03 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98097516 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.98097516 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.2854819371 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 133674822 ps |
| CPU time | 3.43 seconds |
| Started | Sep 09 01:57:03 PM UTC 24 |
| Finished | Sep 09 01:57:08 PM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854819371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2854819371 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_error.3652818575 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 11285631736 ps |
| CPU time | 141.68 seconds |
| Started | Sep 09 01:56:19 PM UTC 24 |
| Finished | Sep 09 01:58:44 PM UTC 24 |
| Peak memory | 295464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652818575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3652818575 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.1061029051 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1558720598 ps |
| CPU time | 19.4 seconds |
| Started | Sep 09 01:56:44 PM UTC 24 |
| Finished | Sep 09 01:57:04 PM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061029051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1061029051 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.310496670 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 50165586342 ps |
| CPU time | 820.5 seconds |
| Started | Sep 09 01:54:53 PM UTC 24 |
| Finished | Sep 09 02:08:43 PM UTC 24 |
| Peak memory | 1168100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310496670 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.310496670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.298097261 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 39344181198 ps |
| CPU time | 349.3 seconds |
| Started | Sep 09 01:56:15 PM UTC 24 |
| Finished | Sep 09 02:02:09 PM UTC 24 |
| Peak memory | 498592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298097261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.298097261 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.3141238733 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 817778575 ps |
| CPU time | 33.22 seconds |
| Started | Sep 09 01:54:50 PM UTC 24 |
| Finished | Sep 09 01:55:25 PM UTC 24 |
| Peak memory | 234164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141238733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3141238733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2022637980 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 152912104 ps |
| CPU time | 3.4 seconds |
| Started | Sep 09 01:55:54 PM UTC 24 |
| Finished | Sep 09 01:55:59 PM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022637980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.2022637980 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.137668131 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 237061010 ps |
| CPU time | 2.84 seconds |
| Started | Sep 09 01:56:01 PM UTC 24 |
| Finished | Sep 09 01:56:05 PM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137668131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.137668131 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.179526282 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 163367010985 ps |
| CPU time | 2477.06 seconds |
| Started | Sep 09 01:55:05 PM UTC 24 |
| Finished | Sep 09 02:36:48 PM UTC 24 |
| Peak memory | 3179048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179526282 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.179526282 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.3874597481 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 242875218017 ps |
| CPU time | 2448.2 seconds |
| Started | Sep 09 01:55:08 PM UTC 24 |
| Finished | Sep 09 02:36:24 PM UTC 24 |
| Peak memory | 3015100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874597481 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3874597481 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.1151338170 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3634819569 ps |
| CPU time | 36.65 seconds |
| Started | Sep 09 01:55:15 PM UTC 24 |
| Finished | Sep 09 01:55:53 PM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151338170 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1151338170 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.36776153 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 49497305905 ps |
| CPU time | 2141.38 seconds |
| Started | Sep 09 01:55:20 PM UTC 24 |
| Finished | Sep 09 02:31:27 PM UTC 24 |
| Peak memory | 1737156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36776153 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.36776153 +enable_m asking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.3205087422 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 59188174767 ps |
| CPU time | 321.97 seconds |
| Started | Sep 09 01:55:25 PM UTC 24 |
| Finished | Sep 09 02:00:52 PM UTC 24 |
| Peak memory | 444960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205087422 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3205087422 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.3651513059 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 44661450793 ps |
| CPU time | 539.95 seconds |
| Started | Sep 09 01:55:31 PM UTC 24 |
| Finished | Sep 09 02:04:39 PM UTC 24 |
| Peak memory | 270848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651513059 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3651513059 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.754300390 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 15877963 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 02:22:25 PM UTC 24 |
| Finished | Sep 09 02:22:28 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754300390 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.754300390 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_app.894131141 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 31507479842 ps |
| CPU time | 531.26 seconds |
| Started | Sep 09 02:21:48 PM UTC 24 |
| Finished | Sep 09 02:30:46 PM UTC 24 |
| Peak memory | 555620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894131141 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.894131141 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.3042317802 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 126301142197 ps |
| CPU time | 1680.03 seconds |
| Started | Sep 09 02:21:38 PM UTC 24 |
| Finished | Sep 09 02:49:58 PM UTC 24 |
| Peak memory | 272932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042317802 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3042317802 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1697883719 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 73994609 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 02:22:19 PM UTC 24 |
| Finished | Sep 09 02:22:21 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697883719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1697883719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.3913499214 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 270108062 ps |
| CPU time | 1.97 seconds |
| Started | Sep 09 02:22:21 PM UTC 24 |
| Finished | Sep 09 02:22:24 PM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913499214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3913499214 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.4032619976 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 6268174910 ps |
| CPU time | 128.69 seconds |
| Started | Sep 09 02:21:48 PM UTC 24 |
| Finished | Sep 09 02:23:59 PM UTC 24 |
| Peak memory | 311912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032619976 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.4032619976 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_error.1024659255 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4525854973 ps |
| CPU time | 202.55 seconds |
| Started | Sep 09 02:22:05 PM UTC 24 |
| Finished | Sep 09 02:25:31 PM UTC 24 |
| Peak memory | 301676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024659255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1024659255 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.943649990 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 704942634 ps |
| CPU time | 6.54 seconds |
| Started | Sep 09 02:22:15 PM UTC 24 |
| Finished | Sep 09 02:22:23 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943649990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.943649990 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2307465893 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 50850337934 ps |
| CPU time | 2068.46 seconds |
| Started | Sep 09 02:21:33 PM UTC 24 |
| Finished | Sep 09 02:56:26 PM UTC 24 |
| Peak memory | 1210984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307465893 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2307465893 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.1732957902 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 78067520433 ps |
| CPU time | 486.53 seconds |
| Started | Sep 09 02:21:36 PM UTC 24 |
| Finished | Sep 09 02:29:49 PM UTC 24 |
| Peak memory | 653928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732957902 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1732957902 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.2131446351 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6253617965 ps |
| CPU time | 79.64 seconds |
| Started | Sep 09 02:21:32 PM UTC 24 |
| Finished | Sep 09 02:22:53 PM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131446351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2131446351 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.1685716638 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 32232220185 ps |
| CPU time | 296.87 seconds |
| Started | Sep 09 02:22:24 PM UTC 24 |
| Finished | Sep 09 02:27:26 PM UTC 24 |
| Peak memory | 320100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685716638 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1685716638 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.1693731493 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 57042927 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 02:24:49 PM UTC 24 |
| Finished | Sep 09 02:24:51 PM UTC 24 |
| Peak memory | 225100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693731493 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1693731493 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_app.3851107547 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 98720530990 ps |
| CPU time | 314.06 seconds |
| Started | Sep 09 02:22:51 PM UTC 24 |
| Finished | Sep 09 02:28:09 PM UTC 24 |
| Peak memory | 332360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851107547 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3851107547 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.3776522072 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4021296003 ps |
| CPU time | 188.67 seconds |
| Started | Sep 09 02:22:38 PM UTC 24 |
| Finished | Sep 09 02:25:49 PM UTC 24 |
| Peak memory | 240356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776522072 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3776522072 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.3863032045 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 30436729 ps |
| CPU time | 3.65 seconds |
| Started | Sep 09 02:24:26 PM UTC 24 |
| Finished | Sep 09 02:24:31 PM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863032045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3863032045 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.965925726 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 33345267 ps |
| CPU time | 1.72 seconds |
| Started | Sep 09 02:24:32 PM UTC 24 |
| Finished | Sep 09 02:24:35 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965925726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.965925726 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.3600331733 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 19724916798 ps |
| CPU time | 324.73 seconds |
| Started | Sep 09 02:22:54 PM UTC 24 |
| Finished | Sep 09 02:28:23 PM UTC 24 |
| Peak memory | 350860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600331733 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3600331733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.3485079789 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 13754839022 ps |
| CPU time | 30.3 seconds |
| Started | Sep 09 02:24:18 PM UTC 24 |
| Finished | Sep 09 02:24:50 PM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485079789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3485079789 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.260761364 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 51687351226 ps |
| CPU time | 2054.77 seconds |
| Started | Sep 09 02:22:28 PM UTC 24 |
| Finished | Sep 09 02:57:06 PM UTC 24 |
| Peak memory | 2589400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260761364 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.260761364 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.2355145952 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 26939978753 ps |
| CPU time | 506.7 seconds |
| Started | Sep 09 02:22:36 PM UTC 24 |
| Finished | Sep 09 02:31:10 PM UTC 24 |
| Peak memory | 559712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355145952 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2355145952 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.112914029 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 31584320953 ps |
| CPU time | 115.66 seconds |
| Started | Sep 09 02:22:27 PM UTC 24 |
| Finished | Sep 09 02:24:26 PM UTC 24 |
| Peak memory | 236052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112914029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.112914029 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.1230645677 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1624079307 ps |
| CPU time | 122.79 seconds |
| Started | Sep 09 02:24:40 PM UTC 24 |
| Finished | Sep 09 02:26:45 PM UTC 24 |
| Peak memory | 252332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230645677 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1230645677 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.3265701423 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 32869878 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 02:26:54 PM UTC 24 |
| Finished | Sep 09 02:26:57 PM UTC 24 |
| Peak memory | 225220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265701423 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3265701423 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_app.2531853363 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6007437758 ps |
| CPU time | 70.59 seconds |
| Started | Sep 09 02:25:32 PM UTC 24 |
| Finished | Sep 09 02:26:44 PM UTC 24 |
| Peak memory | 254556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531853363 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2531853363 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.3172854705 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 31382997630 ps |
| CPU time | 1018.05 seconds |
| Started | Sep 09 02:25:12 PM UTC 24 |
| Finished | Sep 09 02:42:22 PM UTC 24 |
| Peak memory | 264796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172854705 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3172854705 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2835875998 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 142725600 ps |
| CPU time | 1.96 seconds |
| Started | Sep 09 02:26:46 PM UTC 24 |
| Finished | Sep 09 02:26:49 PM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835875998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2835875998 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1715089961 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 45916363 ps |
| CPU time | 1.77 seconds |
| Started | Sep 09 02:26:46 PM UTC 24 |
| Finished | Sep 09 02:26:49 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715089961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1715089961 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.156442042 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1797597254 ps |
| CPU time | 48.55 seconds |
| Started | Sep 09 02:25:50 PM UTC 24 |
| Finished | Sep 09 02:26:40 PM UTC 24 |
| Peak memory | 240036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156442042 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.156442042 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_error.3401103926 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 8957788328 ps |
| CPU time | 209.65 seconds |
| Started | Sep 09 02:26:00 PM UTC 24 |
| Finished | Sep 09 02:29:33 PM UTC 24 |
| Peak memory | 371220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401103926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3401103926 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.3483497492 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 750082488 ps |
| CPU time | 10.69 seconds |
| Started | Sep 09 02:26:42 PM UTC 24 |
| Finished | Sep 09 02:26:53 PM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483497492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3483497492 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.2878286782 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 38444351 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 02:26:50 PM UTC 24 |
| Finished | Sep 09 02:26:53 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878286782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2878286782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.560279686 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 54497286563 ps |
| CPU time | 1188.86 seconds |
| Started | Sep 09 02:24:52 PM UTC 24 |
| Finished | Sep 09 02:44:54 PM UTC 24 |
| Peak memory | 1544812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560279686 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.560279686 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.3060781456 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 6095541904 ps |
| CPU time | 252.1 seconds |
| Started | Sep 09 02:25:04 PM UTC 24 |
| Finished | Sep 09 02:29:20 PM UTC 24 |
| Peak memory | 316000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060781456 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3060781456 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.2693963496 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3064453575 ps |
| CPU time | 67.32 seconds |
| Started | Sep 09 02:24:51 PM UTC 24 |
| Finished | Sep 09 02:26:00 PM UTC 24 |
| Peak memory | 236072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693963496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2693963496 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.101989353 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 23493728380 ps |
| CPU time | 1770.88 seconds |
| Started | Sep 09 02:26:50 PM UTC 24 |
| Finished | Sep 09 02:56:41 PM UTC 24 |
| Peak memory | 646040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101989353 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.101989353 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.1465373555 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 19805733 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 02:29:00 PM UTC 24 |
| Finished | Sep 09 02:29:03 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465373555 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1465373555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_app.679254971 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 19641693058 ps |
| CPU time | 597.44 seconds |
| Started | Sep 09 02:27:51 PM UTC 24 |
| Finished | Sep 09 02:37:57 PM UTC 24 |
| Peak memory | 565872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679254971 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.679254971 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.2939985439 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 10602924696 ps |
| CPU time | 1014.93 seconds |
| Started | Sep 09 02:27:26 PM UTC 24 |
| Finished | Sep 09 02:44:33 PM UTC 24 |
| Peak memory | 250476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939985439 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2939985439 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.884514725 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 809180157 ps |
| CPU time | 28.18 seconds |
| Started | Sep 09 02:28:36 PM UTC 24 |
| Finished | Sep 09 02:29:05 PM UTC 24 |
| Peak memory | 231984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884514725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.884514725 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.2125859077 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 5665677564 ps |
| CPU time | 14.52 seconds |
| Started | Sep 09 02:28:44 PM UTC 24 |
| Finished | Sep 09 02:29:00 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125859077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2125859077 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.468918780 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2048003730 ps |
| CPU time | 49.18 seconds |
| Started | Sep 09 02:27:53 PM UTC 24 |
| Finished | Sep 09 02:28:43 PM UTC 24 |
| Peak memory | 240020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468918780 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.468918780 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_error.1277045009 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 67338264802 ps |
| CPU time | 513.82 seconds |
| Started | Sep 09 02:28:11 PM UTC 24 |
| Finished | Sep 09 02:36:51 PM UTC 24 |
| Peak memory | 602744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277045009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1277045009 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.1323402796 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 876825247 ps |
| CPU time | 10.16 seconds |
| Started | Sep 09 02:28:24 PM UTC 24 |
| Finished | Sep 09 02:28:35 PM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323402796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1323402796 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.1935250075 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 56304162 ps |
| CPU time | 2.92 seconds |
| Started | Sep 09 02:28:56 PM UTC 24 |
| Finished | Sep 09 02:29:00 PM UTC 24 |
| Peak memory | 234112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935250075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1935250075 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1207063810 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 23462646575 ps |
| CPU time | 2341.92 seconds |
| Started | Sep 09 02:26:57 PM UTC 24 |
| Finished | Sep 09 03:06:25 PM UTC 24 |
| Peak memory | 1602168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207063810 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.1207063810 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.3239181927 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 89596599340 ps |
| CPU time | 720.92 seconds |
| Started | Sep 09 02:26:57 PM UTC 24 |
| Finished | Sep 09 02:39:07 PM UTC 24 |
| Peak memory | 670292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239181927 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3239181927 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.2747322648 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 7498138598 ps |
| CPU time | 56.52 seconds |
| Started | Sep 09 02:26:54 PM UTC 24 |
| Finished | Sep 09 02:27:52 PM UTC 24 |
| Peak memory | 236132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747322648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2747322648 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.2587198915 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 18341905573 ps |
| CPU time | 652.63 seconds |
| Started | Sep 09 02:28:56 PM UTC 24 |
| Finished | Sep 09 02:39:57 PM UTC 24 |
| Peak memory | 371624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587198915 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2587198915 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.239760266 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 18567682 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 02:29:57 PM UTC 24 |
| Finished | Sep 09 02:30:00 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239760266 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.239760266 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_app.322243889 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 676743981 ps |
| CPU time | 25.23 seconds |
| Started | Sep 09 02:29:21 PM UTC 24 |
| Finished | Sep 09 02:29:47 PM UTC 24 |
| Peak memory | 250352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322243889 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.322243889 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.270991908 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 22248827781 ps |
| CPU time | 1280.91 seconds |
| Started | Sep 09 02:29:07 PM UTC 24 |
| Finished | Sep 09 02:50:43 PM UTC 24 |
| Peak memory | 268972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270991908 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.270991908 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.493569282 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1770261517 ps |
| CPU time | 38.03 seconds |
| Started | Sep 09 02:29:49 PM UTC 24 |
| Finished | Sep 09 02:30:28 PM UTC 24 |
| Peak memory | 235812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493569282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.493569282 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.2375246899 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 22309813 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 02:29:50 PM UTC 24 |
| Finished | Sep 09 02:29:52 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375246899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2375246899 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.3008276612 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 58219620948 ps |
| CPU time | 388.74 seconds |
| Started | Sep 09 02:29:22 PM UTC 24 |
| Finished | Sep 09 02:35:56 PM UTC 24 |
| Peak memory | 477804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008276612 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3008276612 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_error.4146590147 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 38180475384 ps |
| CPU time | 433.76 seconds |
| Started | Sep 09 02:29:34 PM UTC 24 |
| Finished | Sep 09 02:36:54 PM UTC 24 |
| Peak memory | 488036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146590147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.4146590147 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.2746109891 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 952504985 ps |
| CPU time | 7.47 seconds |
| Started | Sep 09 02:29:48 PM UTC 24 |
| Finished | Sep 09 02:29:56 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746109891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2746109891 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.1227136219 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 55337957 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 02:29:53 PM UTC 24 |
| Finished | Sep 09 02:29:56 PM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227136219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1227136219 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.1929608947 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 53964505814 ps |
| CPU time | 2726.41 seconds |
| Started | Sep 09 02:29:03 PM UTC 24 |
| Finished | Sep 09 03:15:01 PM UTC 24 |
| Peak memory | 2753360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929608947 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.1929608947 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.2666215523 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3716949551 ps |
| CPU time | 127.14 seconds |
| Started | Sep 09 02:29:05 PM UTC 24 |
| Finished | Sep 09 02:31:15 PM UTC 24 |
| Peak memory | 330332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666215523 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2666215523 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.3252700767 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 94033165 ps |
| CPU time | 2.81 seconds |
| Started | Sep 09 02:29:01 PM UTC 24 |
| Finished | Sep 09 02:29:05 PM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252700767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3252700767 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.1010100466 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 35165828862 ps |
| CPU time | 856.09 seconds |
| Started | Sep 09 02:29:57 PM UTC 24 |
| Finished | Sep 09 02:44:24 PM UTC 24 |
| Peak memory | 381876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010100466 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1010100466 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.128847706 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 20700838 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 02:31:32 PM UTC 24 |
| Finished | Sep 09 02:31:34 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128847706 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.128847706 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_app.1707721759 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 20859058852 ps |
| CPU time | 112.61 seconds |
| Started | Sep 09 02:30:41 PM UTC 24 |
| Finished | Sep 09 02:32:35 PM UTC 24 |
| Peak memory | 322084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707721759 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1707721759 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.3335403112 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 7565435364 ps |
| CPU time | 247.7 seconds |
| Started | Sep 09 02:30:30 PM UTC 24 |
| Finished | Sep 09 02:34:41 PM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335403112 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.3335403112 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.3487981018 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 297761681 ps |
| CPU time | 17.85 seconds |
| Started | Sep 09 02:31:16 PM UTC 24 |
| Finished | Sep 09 02:31:36 PM UTC 24 |
| Peak memory | 235980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487981018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3487981018 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.710828983 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 74781646 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 02:31:24 PM UTC 24 |
| Finished | Sep 09 02:31:27 PM UTC 24 |
| Peak memory | 227880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710828983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.710828983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_error.1001224444 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 87824165705 ps |
| CPU time | 480.35 seconds |
| Started | Sep 09 02:31:11 PM UTC 24 |
| Finished | Sep 09 02:39:18 PM UTC 24 |
| Peak memory | 520876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001224444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1001224444 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.1941577552 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 677849382 ps |
| CPU time | 8.9 seconds |
| Started | Sep 09 02:31:13 PM UTC 24 |
| Finished | Sep 09 02:31:24 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941577552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1941577552 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.3783069257 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 97947479 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 02:31:27 PM UTC 24 |
| Finished | Sep 09 02:31:31 PM UTC 24 |
| Peak memory | 234132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783069257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3783069257 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.4021037887 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 785586217804 ps |
| CPU time | 2802.78 seconds |
| Started | Sep 09 02:30:00 PM UTC 24 |
| Finished | Sep 09 03:17:16 PM UTC 24 |
| Peak memory | 3127988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021037887 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.4021037887 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.2922943471 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 43733313445 ps |
| CPU time | 204.33 seconds |
| Started | Sep 09 02:30:02 PM UTC 24 |
| Finished | Sep 09 02:33:30 PM UTC 24 |
| Peak memory | 295548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922943471 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2922943471 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.4225599236 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 8908803115 ps |
| CPU time | 69.76 seconds |
| Started | Sep 09 02:30:00 PM UTC 24 |
| Finished | Sep 09 02:31:12 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225599236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.4225599236 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.403889182 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 57440141487 ps |
| CPU time | 1175.15 seconds |
| Started | Sep 09 02:31:28 PM UTC 24 |
| Finished | Sep 09 02:51:17 PM UTC 24 |
| Peak memory | 1215412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403889182 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.403889182 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.2536012204 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 28798960 ps |
| CPU time | 1.37 seconds |
| Started | Sep 09 02:34:02 PM UTC 24 |
| Finished | Sep 09 02:34:05 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536012204 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2536012204 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_app.1535177464 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 14375224108 ps |
| CPU time | 388 seconds |
| Started | Sep 09 02:32:36 PM UTC 24 |
| Finished | Sep 09 02:39:10 PM UTC 24 |
| Peak memory | 498280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535177464 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1535177464 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.843350644 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 5547863099 ps |
| CPU time | 470.55 seconds |
| Started | Sep 09 02:31:59 PM UTC 24 |
| Finished | Sep 09 02:39:55 PM UTC 24 |
| Peak memory | 244260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843350644 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.843350644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2525390901 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 581886391 ps |
| CPU time | 13.25 seconds |
| Started | Sep 09 02:33:44 PM UTC 24 |
| Finished | Sep 09 02:33:59 PM UTC 24 |
| Peak memory | 235808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525390901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2525390901 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.2501688931 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 33810595 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 02:33:54 PM UTC 24 |
| Finished | Sep 09 02:33:57 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501688931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2501688931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.607079184 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 10332778131 ps |
| CPU time | 373.77 seconds |
| Started | Sep 09 02:32:42 PM UTC 24 |
| Finished | Sep 09 02:39:02 PM UTC 24 |
| Peak memory | 320040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607079184 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.607079184 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_error.2626411581 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2794829446 ps |
| CPU time | 255.07 seconds |
| Started | Sep 09 02:32:46 PM UTC 24 |
| Finished | Sep 09 02:37:05 PM UTC 24 |
| Peak memory | 328216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626411581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2626411581 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.347481728 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 819534218 ps |
| CPU time | 11.06 seconds |
| Started | Sep 09 02:33:31 PM UTC 24 |
| Finished | Sep 09 02:33:43 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347481728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.347481728 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.1995911131 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 439326009168 ps |
| CPU time | 1650.55 seconds |
| Started | Sep 09 02:31:37 PM UTC 24 |
| Finished | Sep 09 02:59:26 PM UTC 24 |
| Peak memory | 2087596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995911131 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.1995911131 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.1606114062 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5573889241 ps |
| CPU time | 192.44 seconds |
| Started | Sep 09 02:31:52 PM UTC 24 |
| Finished | Sep 09 02:35:07 PM UTC 24 |
| Peak memory | 381524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606114062 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1606114062 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.200356504 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 643843217 ps |
| CPU time | 21.77 seconds |
| Started | Sep 09 02:31:35 PM UTC 24 |
| Finished | Sep 09 02:31:58 PM UTC 24 |
| Peak memory | 235948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200356504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.200356504 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.251750745 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 23141673734 ps |
| CPU time | 857.65 seconds |
| Started | Sep 09 02:33:59 PM UTC 24 |
| Finished | Sep 09 02:48:27 PM UTC 24 |
| Peak memory | 1258220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251750745 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.251750745 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.3156440732 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 12379557 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 02:35:58 PM UTC 24 |
| Finished | Sep 09 02:36:01 PM UTC 24 |
| Peak memory | 224680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156440732 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3156440732 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_app.3299154082 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 9772812384 ps |
| CPU time | 384.84 seconds |
| Started | Sep 09 02:35:08 PM UTC 24 |
| Finished | Sep 09 02:41:38 PM UTC 24 |
| Peak memory | 465504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299154082 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3299154082 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.3160341544 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 25167248036 ps |
| CPU time | 1256.32 seconds |
| Started | Sep 09 02:34:43 PM UTC 24 |
| Finished | Sep 09 02:55:54 PM UTC 24 |
| Peak memory | 266852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160341544 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3160341544 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3834137785 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2186684310 ps |
| CPU time | 38.66 seconds |
| Started | Sep 09 02:35:38 PM UTC 24 |
| Finished | Sep 09 02:36:18 PM UTC 24 |
| Peak memory | 235620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834137785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3834137785 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.1051485686 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 130876139 ps |
| CPU time | 1.84 seconds |
| Started | Sep 09 02:35:51 PM UTC 24 |
| Finished | Sep 09 02:35:54 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051485686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1051485686 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.3632885242 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6786104188 ps |
| CPU time | 387.9 seconds |
| Started | Sep 09 02:35:20 PM UTC 24 |
| Finished | Sep 09 02:41:53 PM UTC 24 |
| Peak memory | 332396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632885242 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3632885242 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_error.2871772513 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 30006101984 ps |
| CPU time | 563.89 seconds |
| Started | Sep 09 02:35:30 PM UTC 24 |
| Finished | Sep 09 02:45:01 PM UTC 24 |
| Peak memory | 651876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871772513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2871772513 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.2419979698 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1360176611 ps |
| CPU time | 5.73 seconds |
| Started | Sep 09 02:35:30 PM UTC 24 |
| Finished | Sep 09 02:35:37 PM UTC 24 |
| Peak memory | 227900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419979698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2419979698 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.976090475 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 65370194 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 02:35:55 PM UTC 24 |
| Finished | Sep 09 02:35:58 PM UTC 24 |
| Peak memory | 233636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976090475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.976090475 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.3377772809 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 156513169577 ps |
| CPU time | 4385.65 seconds |
| Started | Sep 09 02:34:16 PM UTC 24 |
| Finished | Sep 09 03:48:09 PM UTC 24 |
| Peak memory | 4518324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377772809 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.3377772809 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.676386835 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3703524212 ps |
| CPU time | 112.96 seconds |
| Started | Sep 09 02:34:25 PM UTC 24 |
| Finished | Sep 09 02:36:20 PM UTC 24 |
| Peak memory | 309844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676386835 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.676386835 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.3890945568 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2880739664 ps |
| CPU time | 71.49 seconds |
| Started | Sep 09 02:34:05 PM UTC 24 |
| Finished | Sep 09 02:35:19 PM UTC 24 |
| Peak memory | 234240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890945568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3890945568 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.1132515808 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 611912718 ps |
| CPU time | 52.26 seconds |
| Started | Sep 09 02:35:57 PM UTC 24 |
| Finished | Sep 09 02:36:51 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132515808 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1132515808 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.2514075884 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 54102813 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 02:37:12 PM UTC 24 |
| Finished | Sep 09 02:37:14 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514075884 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2514075884 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_app.953580299 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1772737070 ps |
| CPU time | 40.96 seconds |
| Started | Sep 09 02:36:49 PM UTC 24 |
| Finished | Sep 09 02:37:31 PM UTC 24 |
| Peak memory | 262628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953580299 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.953580299 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.2074236930 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 47124874231 ps |
| CPU time | 1272.19 seconds |
| Started | Sep 09 02:36:25 PM UTC 24 |
| Finished | Sep 09 02:57:52 PM UTC 24 |
| Peak memory | 266852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074236930 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2074236930 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.3425274801 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2804823807 ps |
| CPU time | 43.63 seconds |
| Started | Sep 09 02:36:59 PM UTC 24 |
| Finished | Sep 09 02:37:44 PM UTC 24 |
| Peak memory | 244340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425274801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3425274801 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1966768820 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 29883574 ps |
| CPU time | 1.37 seconds |
| Started | Sep 09 02:37:06 PM UTC 24 |
| Finished | Sep 09 02:37:09 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966768820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1966768820 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1992742895 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 102706780947 ps |
| CPU time | 210.44 seconds |
| Started | Sep 09 02:36:52 PM UTC 24 |
| Finished | Sep 09 02:40:26 PM UTC 24 |
| Peak memory | 334412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992742895 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1992742895 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_error.3703660315 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 40480117941 ps |
| CPU time | 145.08 seconds |
| Started | Sep 09 02:36:52 PM UTC 24 |
| Finished | Sep 09 02:39:20 PM UTC 24 |
| Peak memory | 361088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703660315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3703660315 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.1344092430 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1530684043 ps |
| CPU time | 17.17 seconds |
| Started | Sep 09 02:36:55 PM UTC 24 |
| Finished | Sep 09 02:37:14 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344092430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1344092430 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.3069700698 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 33224419 ps |
| CPU time | 2.35 seconds |
| Started | Sep 09 02:37:07 PM UTC 24 |
| Finished | Sep 09 02:37:11 PM UTC 24 |
| Peak memory | 234044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069700698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3069700698 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1179100106 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 139561222159 ps |
| CPU time | 2548.46 seconds |
| Started | Sep 09 02:36:19 PM UTC 24 |
| Finished | Sep 09 03:19:17 PM UTC 24 |
| Peak memory | 1511976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179100106 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1179100106 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.1891947148 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 41381212274 ps |
| CPU time | 425.16 seconds |
| Started | Sep 09 02:36:21 PM UTC 24 |
| Finished | Sep 09 02:43:32 PM UTC 24 |
| Peak memory | 504424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891947148 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1891947148 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.378988295 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 8599680674 ps |
| CPU time | 83.99 seconds |
| Started | Sep 09 02:36:01 PM UTC 24 |
| Finished | Sep 09 02:37:27 PM UTC 24 |
| Peak memory | 232256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378988295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.378988295 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.628822614 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 10833127771 ps |
| CPU time | 720.86 seconds |
| Started | Sep 09 02:37:09 PM UTC 24 |
| Finished | Sep 09 02:49:19 PM UTC 24 |
| Peak memory | 529316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628822614 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.628822614 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.3654257483 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 56631962 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 02:38:17 PM UTC 24 |
| Finished | Sep 09 02:38:19 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654257483 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3654257483 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_app.1152546799 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 11054638511 ps |
| CPU time | 343.4 seconds |
| Started | Sep 09 02:37:29 PM UTC 24 |
| Finished | Sep 09 02:43:17 PM UTC 24 |
| Peak memory | 461412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152546799 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1152546799 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.2685610521 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 58926582177 ps |
| CPU time | 1579.1 seconds |
| Started | Sep 09 02:37:28 PM UTC 24 |
| Finished | Sep 09 03:04:07 PM UTC 24 |
| Peak memory | 256560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685610521 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2685610521 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.1011484484 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5823122872 ps |
| CPU time | 59.18 seconds |
| Started | Sep 09 02:37:59 PM UTC 24 |
| Finished | Sep 09 02:38:59 PM UTC 24 |
| Peak memory | 250492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011484484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1011484484 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2958515137 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 74703427 ps |
| CPU time | 1.78 seconds |
| Started | Sep 09 02:38:09 PM UTC 24 |
| Finished | Sep 09 02:38:11 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958515137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2958515137 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1394765161 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 15621424191 ps |
| CPU time | 392.48 seconds |
| Started | Sep 09 02:37:32 PM UTC 24 |
| Finished | Sep 09 02:44:10 PM UTC 24 |
| Peak memory | 418404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394765161 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1394765161 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_error.2844037734 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 33101754040 ps |
| CPU time | 249.88 seconds |
| Started | Sep 09 02:37:40 PM UTC 24 |
| Finished | Sep 09 02:41:54 PM UTC 24 |
| Peak memory | 449072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844037734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2844037734 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.4136144232 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3489886771 ps |
| CPU time | 21.08 seconds |
| Started | Sep 09 02:37:45 PM UTC 24 |
| Finished | Sep 09 02:38:08 PM UTC 24 |
| Peak memory | 228012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136144232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.4136144232 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.605381180 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 49675284 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 02:38:13 PM UTC 24 |
| Finished | Sep 09 02:38:16 PM UTC 24 |
| Peak memory | 232056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605381180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.605381180 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1486854470 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 61792135523 ps |
| CPU time | 3054.97 seconds |
| Started | Sep 09 02:37:15 PM UTC 24 |
| Finished | Sep 09 03:28:45 PM UTC 24 |
| Peak memory | 3119664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486854470 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1486854470 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.119789558 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 117424991 ps |
| CPU time | 11.9 seconds |
| Started | Sep 09 02:37:15 PM UTC 24 |
| Finished | Sep 09 02:37:28 PM UTC 24 |
| Peak memory | 234512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119789558 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.119789558 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.562953058 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2116828104 ps |
| CPU time | 23.77 seconds |
| Started | Sep 09 02:37:15 PM UTC 24 |
| Finished | Sep 09 02:37:40 PM UTC 24 |
| Peak memory | 236000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562953058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.562953058 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.4266206592 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 6248994531 ps |
| CPU time | 89.32 seconds |
| Started | Sep 09 02:38:17 PM UTC 24 |
| Finished | Sep 09 02:39:48 PM UTC 24 |
| Peak memory | 269168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266206592 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.4266206592 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.54416410 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 37479386 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 02:02:52 PM UTC 24 |
| Finished | Sep 09 02:02:55 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54416410 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.54416410 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_app.1772198692 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 7655326129 ps |
| CPU time | 249.88 seconds |
| Started | Sep 09 02:00:23 PM UTC 24 |
| Finished | Sep 09 02:04:37 PM UTC 24 |
| Peak memory | 371248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772198692 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1772198692 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.4021679716 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13185265757 ps |
| CPU time | 165.27 seconds |
| Started | Sep 09 02:00:23 PM UTC 24 |
| Finished | Sep 09 02:03:11 PM UTC 24 |
| Peak memory | 285280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021679716 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.4021679716 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.1913542115 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 31903225207 ps |
| CPU time | 838.72 seconds |
| Started | Sep 09 01:58:11 PM UTC 24 |
| Finished | Sep 09 02:12:19 PM UTC 24 |
| Peak memory | 248364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913542115 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.1913542115 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1612262405 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 75761423 ps |
| CPU time | 1.63 seconds |
| Started | Sep 09 02:02:09 PM UTC 24 |
| Finished | Sep 09 02:02:12 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612262405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1612262405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.4292039740 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 31398207 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 02:02:13 PM UTC 24 |
| Finished | Sep 09 02:02:16 PM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292039740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.4292039740 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.1460932077 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 26961769605 ps |
| CPU time | 98.89 seconds |
| Started | Sep 09 02:02:15 PM UTC 24 |
| Finished | Sep 09 02:03:56 PM UTC 24 |
| Peak memory | 236200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460932077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1460932077 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1695968888 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 18143615227 ps |
| CPU time | 104.9 seconds |
| Started | Sep 09 02:00:54 PM UTC 24 |
| Finished | Sep 09 02:02:41 PM UTC 24 |
| Peak memory | 312036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695968888 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1695968888 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_error.3038497069 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 16215808092 ps |
| CPU time | 499.18 seconds |
| Started | Sep 09 02:02:06 PM UTC 24 |
| Finished | Sep 09 02:10:32 PM UTC 24 |
| Peak memory | 563804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038497069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3038497069 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.139489634 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 825331233 ps |
| CPU time | 4.25 seconds |
| Started | Sep 09 02:02:09 PM UTC 24 |
| Finished | Sep 09 02:02:15 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139489634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.139489634 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.3476964769 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 51698466 ps |
| CPU time | 2.44 seconds |
| Started | Sep 09 02:02:16 PM UTC 24 |
| Finished | Sep 09 02:02:20 PM UTC 24 |
| Peak memory | 232032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476964769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3476964769 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.3046963810 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 73950707929 ps |
| CPU time | 2072.52 seconds |
| Started | Sep 09 01:57:45 PM UTC 24 |
| Finished | Sep 09 02:32:41 PM UTC 24 |
| Peak memory | 1335832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046963810 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.3046963810 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.1137208929 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13880597546 ps |
| CPU time | 116.49 seconds |
| Started | Sep 09 02:01:55 PM UTC 24 |
| Finished | Sep 09 02:03:54 PM UTC 24 |
| Peak memory | 267116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137208929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1137208929 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.1020910671 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15154203803 ps |
| CPU time | 91.95 seconds |
| Started | Sep 09 02:02:42 PM UTC 24 |
| Finished | Sep 09 02:04:16 PM UTC 24 |
| Peak memory | 290600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020910671 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1020910671 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.3456037142 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 148077040 ps |
| CPU time | 6.62 seconds |
| Started | Sep 09 01:58:10 PM UTC 24 |
| Finished | Sep 09 01:58:18 PM UTC 24 |
| Peak memory | 235984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456037142 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3456037142 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.1044286606 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2853760814 ps |
| CPU time | 70.6 seconds |
| Started | Sep 09 01:57:13 PM UTC 24 |
| Finished | Sep 09 01:58:25 PM UTC 24 |
| Peak memory | 236140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044286606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1044286606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.4251033493 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3106974421 ps |
| CPU time | 204.99 seconds |
| Started | Sep 09 02:02:21 PM UTC 24 |
| Finished | Sep 09 02:05:49 PM UTC 24 |
| Peak memory | 297812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251033493 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.4251033493 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.2028234279 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13288677508 ps |
| CPU time | 115.74 seconds |
| Started | Sep 09 02:02:23 PM UTC 24 |
| Finished | Sep 09 02:04:22 PM UTC 24 |
| Peak memory | 283660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2028234279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_r and_reset.2028234279 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.29275758 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 53426255 ps |
| CPU time | 3.16 seconds |
| Started | Sep 09 02:00:13 PM UTC 24 |
| Finished | Sep 09 02:00:17 PM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29275758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors _kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.29275758 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.1651741379 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 253789815 ps |
| CPU time | 3.31 seconds |
| Started | Sep 09 02:00:18 PM UTC 24 |
| Finished | Sep 09 02:00:23 PM UTC 24 |
| Peak memory | 228096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651741379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1651741379 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.3905678607 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 19084746006 ps |
| CPU time | 2140.67 seconds |
| Started | Sep 09 01:58:18 PM UTC 24 |
| Finished | Sep 09 02:34:24 PM UTC 24 |
| Peak memory | 1173944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905678607 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3905678607 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3348737104 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 245615582917 ps |
| CPU time | 2779.71 seconds |
| Started | Sep 09 01:58:26 PM UTC 24 |
| Finished | Sep 09 02:45:20 PM UTC 24 |
| Peak memory | 3045928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348737104 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3348737104 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.729193759 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 28913569358 ps |
| CPU time | 1671.66 seconds |
| Started | Sep 09 01:58:44 PM UTC 24 |
| Finished | Sep 09 02:26:56 PM UTC 24 |
| Peak memory | 907712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729193759 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.729193759 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.3510955079 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 34048043726 ps |
| CPU time | 1301.35 seconds |
| Started | Sep 09 01:59:08 PM UTC 24 |
| Finished | Sep 09 02:21:04 PM UTC 24 |
| Peak memory | 1708480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510955079 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3510955079 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.4203725819 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 8465805374 ps |
| CPU time | 237.82 seconds |
| Started | Sep 09 01:59:14 PM UTC 24 |
| Finished | Sep 09 02:03:15 PM UTC 24 |
| Peak memory | 244372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203725819 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.4203725819 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.3199516251 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 41452976 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 02:39:49 PM UTC 24 |
| Finished | Sep 09 02:39:53 PM UTC 24 |
| Peak memory | 226360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199516251 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3199516251 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_app.413794227 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 20994508001 ps |
| CPU time | 267.27 seconds |
| Started | Sep 09 02:39:11 PM UTC 24 |
| Finished | Sep 09 02:43:42 PM UTC 24 |
| Peak memory | 438900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413794227 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.413794227 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.1165521995 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 29042222532 ps |
| CPU time | 373.63 seconds |
| Started | Sep 09 02:39:09 PM UTC 24 |
| Finished | Sep 09 02:45:27 PM UTC 24 |
| Peak memory | 244256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165521995 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1165521995 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2477430152 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 18679154194 ps |
| CPU time | 382.2 seconds |
| Started | Sep 09 02:39:15 PM UTC 24 |
| Finished | Sep 09 02:45:43 PM UTC 24 |
| Peak memory | 332392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477430152 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2477430152 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_error.1420038339 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 33726708456 ps |
| CPU time | 390.34 seconds |
| Started | Sep 09 02:39:19 PM UTC 24 |
| Finished | Sep 09 02:45:55 PM UTC 24 |
| Peak memory | 465444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420038339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1420038339 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.598495396 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 17228373670 ps |
| CPU time | 19.41 seconds |
| Started | Sep 09 02:39:21 PM UTC 24 |
| Finished | Sep 09 02:39:42 PM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598495396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.598495396 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.1165770190 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 147497825 ps |
| CPU time | 2.05 seconds |
| Started | Sep 09 02:39:42 PM UTC 24 |
| Finished | Sep 09 02:39:46 PM UTC 24 |
| Peak memory | 232000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165770190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1165770190 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.550488599 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 36641425106 ps |
| CPU time | 1441.31 seconds |
| Started | Sep 09 02:39:00 PM UTC 24 |
| Finished | Sep 09 03:03:18 PM UTC 24 |
| Peak memory | 1964580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550488599 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.550488599 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.4176900950 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 30094635881 ps |
| CPU time | 239.11 seconds |
| Started | Sep 09 02:39:03 PM UTC 24 |
| Finished | Sep 09 02:43:05 PM UTC 24 |
| Peak memory | 326184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176900950 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.4176900950 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.3766187365 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 20169773033 ps |
| CPU time | 52.6 seconds |
| Started | Sep 09 02:38:20 PM UTC 24 |
| Finished | Sep 09 02:39:14 PM UTC 24 |
| Peak memory | 234304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766187365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3766187365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.2338307479 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 17842471935 ps |
| CPU time | 1321.71 seconds |
| Started | Sep 09 02:39:46 PM UTC 24 |
| Finished | Sep 09 03:02:03 PM UTC 24 |
| Peak memory | 777140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338307479 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2338307479 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.94286298 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 52771017 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 02:41:34 PM UTC 24 |
| Finished | Sep 09 02:41:37 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94286298 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.94286298 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_app.1742931899 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 13130635138 ps |
| CPU time | 165.52 seconds |
| Started | Sep 09 02:41:02 PM UTC 24 |
| Finished | Sep 09 02:43:51 PM UTC 24 |
| Peak memory | 295436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742931899 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1742931899 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.420708706 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 50174774741 ps |
| CPU time | 1430.98 seconds |
| Started | Sep 09 02:40:27 PM UTC 24 |
| Finished | Sep 09 03:04:35 PM UTC 24 |
| Peak memory | 270956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420708706 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.420708706 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.1412511382 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 6674031364 ps |
| CPU time | 111.78 seconds |
| Started | Sep 09 02:41:14 PM UTC 24 |
| Finished | Sep 09 02:43:07 PM UTC 24 |
| Peak memory | 326180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412511382 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1412511382 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.3784338803 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 14198293865 ps |
| CPU time | 18.55 seconds |
| Started | Sep 09 02:41:19 PM UTC 24 |
| Finished | Sep 09 02:41:39 PM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784338803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3784338803 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.2156642778 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 181627536 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 02:41:30 PM UTC 24 |
| Finished | Sep 09 02:41:33 PM UTC 24 |
| Peak memory | 234044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156642778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2156642778 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.2960380168 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 120207338652 ps |
| CPU time | 4310.72 seconds |
| Started | Sep 09 02:39:56 PM UTC 24 |
| Finished | Sep 09 03:52:32 PM UTC 24 |
| Peak memory | 4424400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960380168 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.2960380168 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.1057938906 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 14774453721 ps |
| CPU time | 207.26 seconds |
| Started | Sep 09 02:39:58 PM UTC 24 |
| Finished | Sep 09 02:43:28 PM UTC 24 |
| Peak memory | 377376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057938906 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1057938906 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.3718073931 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 7642096661 ps |
| CPU time | 82.52 seconds |
| Started | Sep 09 02:39:53 PM UTC 24 |
| Finished | Sep 09 02:41:18 PM UTC 24 |
| Peak memory | 236144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718073931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3718073931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.2412758591 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 149715703991 ps |
| CPU time | 983.37 seconds |
| Started | Sep 09 02:41:34 PM UTC 24 |
| Finished | Sep 09 02:58:09 PM UTC 24 |
| Peak memory | 416696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412758591 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2412758591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.1505493017 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 30766384 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 02:42:00 PM UTC 24 |
| Finished | Sep 09 02:42:02 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505493017 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1505493017 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_app.3762601746 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 16947526161 ps |
| CPU time | 539.39 seconds |
| Started | Sep 09 02:41:44 PM UTC 24 |
| Finished | Sep 09 02:50:51 PM UTC 24 |
| Peak memory | 565820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762601746 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3762601746 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.1795645528 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 20030568229 ps |
| CPU time | 525.75 seconds |
| Started | Sep 09 02:41:41 PM UTC 24 |
| Finished | Sep 09 02:50:34 PM UTC 24 |
| Peak memory | 246376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795645528 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1795645528 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.2644001553 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 5575991429 ps |
| CPU time | 260.99 seconds |
| Started | Sep 09 02:41:45 PM UTC 24 |
| Finished | Sep 09 02:46:10 PM UTC 24 |
| Peak memory | 305788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644001553 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2644001553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_error.2123730578 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 11385464733 ps |
| CPU time | 415.36 seconds |
| Started | Sep 09 02:41:54 PM UTC 24 |
| Finished | Sep 09 02:48:55 PM UTC 24 |
| Peak memory | 541284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123730578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2123730578 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.4265203988 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 7841388431 ps |
| CPU time | 12.59 seconds |
| Started | Sep 09 02:41:56 PM UTC 24 |
| Finished | Sep 09 02:42:09 PM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265203988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.4265203988 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.3731987937 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 36701517 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 02:41:56 PM UTC 24 |
| Finished | Sep 09 02:41:59 PM UTC 24 |
| Peak memory | 234188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731987937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3731987937 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.1489712237 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 136426515296 ps |
| CPU time | 5732.09 seconds |
| Started | Sep 09 02:41:39 PM UTC 24 |
| Finished | Sep 09 04:18:16 PM UTC 24 |
| Peak memory | 4786940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489712237 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.1489712237 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.3068855411 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 45499194554 ps |
| CPU time | 399.87 seconds |
| Started | Sep 09 02:41:40 PM UTC 24 |
| Finished | Sep 09 02:48:25 PM UTC 24 |
| Peak memory | 487972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068855411 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3068855411 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.3773380851 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 104085462 ps |
| CPU time | 4.44 seconds |
| Started | Sep 09 02:41:37 PM UTC 24 |
| Finished | Sep 09 02:41:43 PM UTC 24 |
| Peak memory | 234108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773380851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3773380851 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.2046751626 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 38930902787 ps |
| CPU time | 313.33 seconds |
| Started | Sep 09 02:41:59 PM UTC 24 |
| Finished | Sep 09 02:47:16 PM UTC 24 |
| Peak memory | 479784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046751626 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2046751626 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.1289057311 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 17051415 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 02:43:06 PM UTC 24 |
| Finished | Sep 09 02:43:08 PM UTC 24 |
| Peak memory | 225940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289057311 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1289057311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_app.4038574072 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 122489784315 ps |
| CPU time | 396.33 seconds |
| Started | Sep 09 02:42:11 PM UTC 24 |
| Finished | Sep 09 02:48:52 PM UTC 24 |
| Peak memory | 545376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038574072 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.4038574072 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.1346380896 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2451086119 ps |
| CPU time | 148.75 seconds |
| Started | Sep 09 02:42:07 PM UTC 24 |
| Finished | Sep 09 02:44:39 PM UTC 24 |
| Peak memory | 236044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346380896 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.1346380896 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.1438729087 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2201490707 ps |
| CPU time | 44.19 seconds |
| Started | Sep 09 02:42:23 PM UTC 24 |
| Finished | Sep 09 02:43:08 PM UTC 24 |
| Peak memory | 244264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438729087 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1438729087 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_error.2520779507 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 26212005008 ps |
| CPU time | 497.19 seconds |
| Started | Sep 09 02:42:24 PM UTC 24 |
| Finished | Sep 09 02:50:48 PM UTC 24 |
| Peak memory | 389732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520779507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2520779507 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.4034474921 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 424325079 ps |
| CPU time | 6.38 seconds |
| Started | Sep 09 02:42:56 PM UTC 24 |
| Finished | Sep 09 02:43:04 PM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034474921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.4034474921 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.1747624076 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1762664255 ps |
| CPU time | 16.77 seconds |
| Started | Sep 09 02:42:56 PM UTC 24 |
| Finished | Sep 09 02:43:14 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747624076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1747624076 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2298995484 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 760650140010 ps |
| CPU time | 4504.98 seconds |
| Started | Sep 09 02:42:03 PM UTC 24 |
| Finished | Sep 09 03:58:01 PM UTC 24 |
| Peak memory | 4143724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298995484 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2298995484 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.4197686076 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 14691626683 ps |
| CPU time | 384.81 seconds |
| Started | Sep 09 02:42:05 PM UTC 24 |
| Finished | Sep 09 02:48:35 PM UTC 24 |
| Peak memory | 541288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197686076 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.4197686076 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.3190875544 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 79662442 ps |
| CPU time | 2.67 seconds |
| Started | Sep 09 02:42:03 PM UTC 24 |
| Finished | Sep 09 02:42:07 PM UTC 24 |
| Peak memory | 234172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190875544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3190875544 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.1217044000 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 111218802208 ps |
| CPU time | 1076.17 seconds |
| Started | Sep 09 02:43:04 PM UTC 24 |
| Finished | Sep 09 03:01:14 PM UTC 24 |
| Peak memory | 760688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217044000 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1217044000 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.779659884 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 15434651 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 02:43:26 PM UTC 24 |
| Finished | Sep 09 02:43:29 PM UTC 24 |
| Peak memory | 225220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779659884 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.779659884 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_app.230814330 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 22660628399 ps |
| CPU time | 430.34 seconds |
| Started | Sep 09 02:43:13 PM UTC 24 |
| Finished | Sep 09 02:50:30 PM UTC 24 |
| Peak memory | 350828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230814330 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.230814330 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.2799782696 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 53814443070 ps |
| CPU time | 994.03 seconds |
| Started | Sep 09 02:43:09 PM UTC 24 |
| Finished | Sep 09 02:59:54 PM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799782696 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.2799782696 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1030147012 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 73640419828 ps |
| CPU time | 320.04 seconds |
| Started | Sep 09 02:43:15 PM UTC 24 |
| Finished | Sep 09 02:48:40 PM UTC 24 |
| Peak memory | 446996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030147012 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1030147012 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_error.253624712 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 724289128 ps |
| CPU time | 27.92 seconds |
| Started | Sep 09 02:43:18 PM UTC 24 |
| Finished | Sep 09 02:43:47 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253624712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.253624712 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.1389101048 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 340475353 ps |
| CPU time | 2.71 seconds |
| Started | Sep 09 02:43:18 PM UTC 24 |
| Finished | Sep 09 02:43:22 PM UTC 24 |
| Peak memory | 227732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389101048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1389101048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.882328771 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 52973321 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 02:43:22 PM UTC 24 |
| Finished | Sep 09 02:43:25 PM UTC 24 |
| Peak memory | 232000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882328771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.882328771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3675073473 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 23929329896 ps |
| CPU time | 1300.29 seconds |
| Started | Sep 09 02:43:08 PM UTC 24 |
| Finished | Sep 09 03:05:04 PM UTC 24 |
| Peak memory | 944740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675073473 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3675073473 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.6433794 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 11914790324 ps |
| CPU time | 445.51 seconds |
| Started | Sep 09 02:43:09 PM UTC 24 |
| Finished | Sep 09 02:50:41 PM UTC 24 |
| Peak memory | 539160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6433794 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.6433794 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.1728003436 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3968274751 ps |
| CPU time | 35.03 seconds |
| Started | Sep 09 02:43:07 PM UTC 24 |
| Finished | Sep 09 02:43:44 PM UTC 24 |
| Peak memory | 236152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728003436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1728003436 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.3553473602 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 31850985994 ps |
| CPU time | 1002.67 seconds |
| Started | Sep 09 02:43:24 PM UTC 24 |
| Finished | Sep 09 03:00:19 PM UTC 24 |
| Peak memory | 396152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553473602 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3553473602 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.750964537 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 25531327 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 02:43:56 PM UTC 24 |
| Finished | Sep 09 02:43:58 PM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750964537 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.750964537 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_app.3394987804 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 14946007933 ps |
| CPU time | 245.21 seconds |
| Started | Sep 09 02:43:43 PM UTC 24 |
| Finished | Sep 09 02:47:52 PM UTC 24 |
| Peak memory | 326364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394987804 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3394987804 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.1246012123 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 34355653818 ps |
| CPU time | 1029.06 seconds |
| Started | Sep 09 02:43:34 PM UTC 24 |
| Finished | Sep 09 03:00:56 PM UTC 24 |
| Peak memory | 248484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246012123 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1246012123 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.4125771804 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6408129383 ps |
| CPU time | 244.4 seconds |
| Started | Sep 09 02:43:45 PM UTC 24 |
| Finished | Sep 09 02:47:53 PM UTC 24 |
| Peak memory | 328380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125771804 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4125771804 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_error.1983797832 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 13287432548 ps |
| CPU time | 317.84 seconds |
| Started | Sep 09 02:43:45 PM UTC 24 |
| Finished | Sep 09 02:49:07 PM UTC 24 |
| Peak memory | 539172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983797832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1983797832 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.667129681 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1771426241 ps |
| CPU time | 14.45 seconds |
| Started | Sep 09 02:43:45 PM UTC 24 |
| Finished | Sep 09 02:44:01 PM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667129681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.667129681 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.1321138249 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 339209813 ps |
| CPU time | 17.51 seconds |
| Started | Sep 09 02:43:47 PM UTC 24 |
| Finished | Sep 09 02:44:06 PM UTC 24 |
| Peak memory | 244424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321138249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1321138249 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.1773272944 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 19219046369 ps |
| CPU time | 1960.05 seconds |
| Started | Sep 09 02:43:30 PM UTC 24 |
| Finished | Sep 09 03:16:32 PM UTC 24 |
| Peak memory | 1274544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773272944 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.1773272944 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.2734701142 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 912914305 ps |
| CPU time | 13.71 seconds |
| Started | Sep 09 02:43:30 PM UTC 24 |
| Finished | Sep 09 02:43:44 PM UTC 24 |
| Peak memory | 250036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734701142 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2734701142 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.3956162671 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2474938643 ps |
| CPU time | 26.18 seconds |
| Started | Sep 09 02:43:26 PM UTC 24 |
| Finished | Sep 09 02:43:54 PM UTC 24 |
| Peak memory | 236104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956162671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3956162671 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.3651011293 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 53342765925 ps |
| CPU time | 1018.86 seconds |
| Started | Sep 09 02:43:52 PM UTC 24 |
| Finished | Sep 09 03:01:03 PM UTC 24 |
| Peak memory | 594812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651011293 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3651011293 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.2619708531 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 28381027 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 02:44:48 PM UTC 24 |
| Finished | Sep 09 02:44:50 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619708531 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2619708531 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_app.3110543933 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 15372974249 ps |
| CPU time | 479.73 seconds |
| Started | Sep 09 02:44:11 PM UTC 24 |
| Finished | Sep 09 02:52:18 PM UTC 24 |
| Peak memory | 537100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110543933 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3110543933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.110607190 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 42697576877 ps |
| CPU time | 763.26 seconds |
| Started | Sep 09 02:44:07 PM UTC 24 |
| Finished | Sep 09 02:57:01 PM UTC 24 |
| Peak memory | 258604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110607190 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.110607190 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.4166048145 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 87148311602 ps |
| CPU time | 224.67 seconds |
| Started | Sep 09 02:44:25 PM UTC 24 |
| Finished | Sep 09 02:48:14 PM UTC 24 |
| Peak memory | 326252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166048145 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.4166048145 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_error.1492141587 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 23300247261 ps |
| CPU time | 131.6 seconds |
| Started | Sep 09 02:44:31 PM UTC 24 |
| Finished | Sep 09 02:46:46 PM UTC 24 |
| Peak memory | 317988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492141587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1492141587 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.567617087 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1622644609 ps |
| CPU time | 12.6 seconds |
| Started | Sep 09 02:44:34 PM UTC 24 |
| Finished | Sep 09 02:44:47 PM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567617087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.567617087 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.1690729950 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 29458976 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 02:44:40 PM UTC 24 |
| Finished | Sep 09 02:44:42 PM UTC 24 |
| Peak memory | 233660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690729950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1690729950 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.2826893018 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 85204089489 ps |
| CPU time | 2042.71 seconds |
| Started | Sep 09 02:44:02 PM UTC 24 |
| Finished | Sep 09 03:18:28 PM UTC 24 |
| Peak memory | 1317520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826893018 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.2826893018 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.1023131502 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 11249544888 ps |
| CPU time | 103.82 seconds |
| Started | Sep 09 02:44:02 PM UTC 24 |
| Finished | Sep 09 02:45:48 PM UTC 24 |
| Peak memory | 305768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023131502 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1023131502 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.3070942732 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2744984809 ps |
| CPU time | 29.46 seconds |
| Started | Sep 09 02:43:59 PM UTC 24 |
| Finished | Sep 09 02:44:30 PM UTC 24 |
| Peak memory | 236116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070942732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3070942732 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.1311724065 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 42419386937 ps |
| CPU time | 1032.03 seconds |
| Started | Sep 09 02:44:44 PM UTC 24 |
| Finished | Sep 09 03:02:08 PM UTC 24 |
| Peak memory | 936956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311724065 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1311724065 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.1247871348 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 53129729 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 02:46:11 PM UTC 24 |
| Finished | Sep 09 02:46:14 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247871348 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1247871348 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_app.2128142014 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 65606573955 ps |
| CPU time | 510.53 seconds |
| Started | Sep 09 02:45:28 PM UTC 24 |
| Finished | Sep 09 02:54:06 PM UTC 24 |
| Peak memory | 514644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128142014 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2128142014 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.1543030365 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 68245526973 ps |
| CPU time | 423.07 seconds |
| Started | Sep 09 02:45:20 PM UTC 24 |
| Finished | Sep 09 02:52:29 PM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543030365 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1543030365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.1490778166 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 52442714167 ps |
| CPU time | 379.39 seconds |
| Started | Sep 09 02:45:44 PM UTC 24 |
| Finished | Sep 09 02:52:08 PM UTC 24 |
| Peak memory | 520748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490778166 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1490778166 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_error.1192910171 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 13037095082 ps |
| CPU time | 217.7 seconds |
| Started | Sep 09 02:45:49 PM UTC 24 |
| Finished | Sep 09 02:49:30 PM UTC 24 |
| Peak memory | 334372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192910171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1192910171 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.1671172529 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 359674606 ps |
| CPU time | 5.7 seconds |
| Started | Sep 09 02:45:56 PM UTC 24 |
| Finished | Sep 09 02:46:03 PM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671172529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1671172529 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.2347246654 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 39463424 ps |
| CPU time | 2.21 seconds |
| Started | Sep 09 02:46:04 PM UTC 24 |
| Finished | Sep 09 02:46:07 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347246654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2347246654 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.2972700877 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 73844804447 ps |
| CPU time | 1791.41 seconds |
| Started | Sep 09 02:44:55 PM UTC 24 |
| Finished | Sep 09 03:15:06 PM UTC 24 |
| Peak memory | 1225388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972700877 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.2972700877 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.2313786334 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 9671875728 ps |
| CPU time | 226.73 seconds |
| Started | Sep 09 02:45:02 PM UTC 24 |
| Finished | Sep 09 02:48:52 PM UTC 24 |
| Peak memory | 307900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313786334 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2313786334 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.4219131246 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 14667712927 ps |
| CPU time | 84.62 seconds |
| Started | Sep 09 02:44:51 PM UTC 24 |
| Finished | Sep 09 02:46:18 PM UTC 24 |
| Peak memory | 236116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219131246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.4219131246 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.3447388241 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 34587372918 ps |
| CPU time | 508.55 seconds |
| Started | Sep 09 02:46:08 PM UTC 24 |
| Finished | Sep 09 02:54:44 PM UTC 24 |
| Peak memory | 484276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447388241 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3447388241 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2457727951 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 39337485 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 02:48:28 PM UTC 24 |
| Finished | Sep 09 02:48:30 PM UTC 24 |
| Peak memory | 224740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457727951 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2457727951 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_app.1802558616 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 16603531913 ps |
| CPU time | 360.65 seconds |
| Started | Sep 09 02:47:28 PM UTC 24 |
| Finished | Sep 09 02:53:34 PM UTC 24 |
| Peak memory | 572000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802558616 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1802558616 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.3697937852 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 8571658039 ps |
| CPU time | 362.05 seconds |
| Started | Sep 09 02:47:18 PM UTC 24 |
| Finished | Sep 09 02:53:25 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697937852 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3697937852 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.3520923698 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 19267214086 ps |
| CPU time | 97.67 seconds |
| Started | Sep 09 02:47:53 PM UTC 24 |
| Finished | Sep 09 02:49:33 PM UTC 24 |
| Peak memory | 291444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520923698 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3520923698 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_error.781519798 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 25575936519 ps |
| CPU time | 214.12 seconds |
| Started | Sep 09 02:47:54 PM UTC 24 |
| Finished | Sep 09 02:51:32 PM UTC 24 |
| Peak memory | 375464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781519798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.781519798 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.1946211586 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1133985640 ps |
| CPU time | 13.39 seconds |
| Started | Sep 09 02:48:16 PM UTC 24 |
| Finished | Sep 09 02:48:30 PM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946211586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1946211586 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.436851116 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 143641254 ps |
| CPU time | 1.78 seconds |
| Started | Sep 09 02:48:26 PM UTC 24 |
| Finished | Sep 09 02:48:29 PM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436851116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.436851116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.1889401569 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 287831460636 ps |
| CPU time | 3376.89 seconds |
| Started | Sep 09 02:46:19 PM UTC 24 |
| Finished | Sep 09 03:43:12 PM UTC 24 |
| Peak memory | 3437096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889401569 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.1889401569 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.2082049056 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 14644295430 ps |
| CPU time | 309.38 seconds |
| Started | Sep 09 02:46:47 PM UTC 24 |
| Finished | Sep 09 02:52:00 PM UTC 24 |
| Peak memory | 334428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082049056 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2082049056 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.1684086335 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3159119173 ps |
| CPU time | 70.75 seconds |
| Started | Sep 09 02:46:14 PM UTC 24 |
| Finished | Sep 09 02:47:27 PM UTC 24 |
| Peak memory | 236072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684086335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1684086335 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.2009379324 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 20482182370 ps |
| CPU time | 366.56 seconds |
| Started | Sep 09 02:48:27 PM UTC 24 |
| Finished | Sep 09 02:54:39 PM UTC 24 |
| Peak memory | 396204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009379324 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2009379324 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.3256127035 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 17647706 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 02:49:08 PM UTC 24 |
| Finished | Sep 09 02:49:11 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256127035 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3256127035 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_app.4235864522 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 5878799582 ps |
| CPU time | 452.95 seconds |
| Started | Sep 09 02:48:41 PM UTC 24 |
| Finished | Sep 09 02:56:20 PM UTC 24 |
| Peak memory | 365096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235864522 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.4235864522 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.2422730046 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 21456347649 ps |
| CPU time | 1147.41 seconds |
| Started | Sep 09 02:48:36 PM UTC 24 |
| Finished | Sep 09 03:07:58 PM UTC 24 |
| Peak memory | 266784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422730046 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2422730046 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.451366889 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 342626066 ps |
| CPU time | 14 seconds |
| Started | Sep 09 02:48:53 PM UTC 24 |
| Finished | Sep 09 02:49:08 PM UTC 24 |
| Peak memory | 236048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451366889 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.451366889 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_error.2158156569 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 14457236133 ps |
| CPU time | 616.23 seconds |
| Started | Sep 09 02:48:53 PM UTC 24 |
| Finished | Sep 09 02:59:17 PM UTC 24 |
| Peak memory | 608872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158156569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2158156569 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.970178765 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4751803436 ps |
| CPU time | 16.94 seconds |
| Started | Sep 09 02:48:54 PM UTC 24 |
| Finished | Sep 09 02:49:12 PM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970178765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.970178765 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.1947847100 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 51566839 ps |
| CPU time | 1.74 seconds |
| Started | Sep 09 02:48:56 PM UTC 24 |
| Finished | Sep 09 02:48:59 PM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947847100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1947847100 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.1901215738 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 221946359128 ps |
| CPU time | 4261.39 seconds |
| Started | Sep 09 02:48:31 PM UTC 24 |
| Finished | Sep 09 04:00:23 PM UTC 24 |
| Peak memory | 3945064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901215738 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.1901215738 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.2414478539 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 25375297688 ps |
| CPU time | 387.14 seconds |
| Started | Sep 09 02:48:31 PM UTC 24 |
| Finished | Sep 09 02:55:04 PM UTC 24 |
| Peak memory | 555684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414478539 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2414478539 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.3624020877 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 869625480 ps |
| CPU time | 20.48 seconds |
| Started | Sep 09 02:48:30 PM UTC 24 |
| Finished | Sep 09 02:48:52 PM UTC 24 |
| Peak memory | 232060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624020877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3624020877 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.2357590515 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 19843490187 ps |
| CPU time | 248.97 seconds |
| Started | Sep 09 02:48:59 PM UTC 24 |
| Finished | Sep 09 02:53:12 PM UTC 24 |
| Peak memory | 310140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357590515 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2357590515 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.3223632314 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 18528341 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 02:05:12 PM UTC 24 |
| Finished | Sep 09 02:05:15 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223632314 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3223632314 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_app.3247285499 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4373322426 ps |
| CPU time | 349.69 seconds |
| Started | Sep 09 02:04:37 PM UTC 24 |
| Finished | Sep 09 02:10:32 PM UTC 24 |
| Peak memory | 322152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247285499 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3247285499 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1179146350 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3088784400 ps |
| CPU time | 99.36 seconds |
| Started | Sep 09 02:04:37 PM UTC 24 |
| Finished | Sep 09 02:06:19 PM UTC 24 |
| Peak memory | 281132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179146350 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1179146350 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.2054369580 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 17015517281 ps |
| CPU time | 829.06 seconds |
| Started | Sep 09 02:03:21 PM UTC 24 |
| Finished | Sep 09 02:17:20 PM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054369580 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2054369580 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.512546601 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 17830053 ps |
| CPU time | 1.45 seconds |
| Started | Sep 09 02:04:48 PM UTC 24 |
| Finished | Sep 09 02:04:50 PM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512546601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.512546601 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3987096970 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2170043222 ps |
| CPU time | 18.52 seconds |
| Started | Sep 09 02:04:51 PM UTC 24 |
| Finished | Sep 09 02:05:11 PM UTC 24 |
| Peak memory | 232116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987096970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3987096970 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.2097764137 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 21197911391 ps |
| CPU time | 445.52 seconds |
| Started | Sep 09 02:04:38 PM UTC 24 |
| Finished | Sep 09 02:12:10 PM UTC 24 |
| Peak memory | 510572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097764137 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2097764137 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_error.239720300 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 246659036 ps |
| CPU time | 2.93 seconds |
| Started | Sep 09 02:04:39 PM UTC 24 |
| Finished | Sep 09 02:04:43 PM UTC 24 |
| Peak memory | 234104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239720300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.239720300 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.94341756 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1166688445 ps |
| CPU time | 13.85 seconds |
| Started | Sep 09 02:04:41 PM UTC 24 |
| Finished | Sep 09 02:04:56 PM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94341756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.94341756 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.3258770279 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2238293016 ps |
| CPU time | 102.7 seconds |
| Started | Sep 09 02:03:13 PM UTC 24 |
| Finished | Sep 09 02:04:57 PM UTC 24 |
| Peak memory | 326200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258770279 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3258770279 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.3785536048 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 7734552673 ps |
| CPU time | 429.7 seconds |
| Started | Sep 09 02:04:39 PM UTC 24 |
| Finished | Sep 09 02:11:55 PM UTC 24 |
| Peak memory | 351100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785536048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3785536048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.1782857657 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 8649704777 ps |
| CPU time | 157.87 seconds |
| Started | Sep 09 02:05:00 PM UTC 24 |
| Finished | Sep 09 02:07:41 PM UTC 24 |
| Peak memory | 327468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782857657 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1782857657 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.2372753940 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5939574928 ps |
| CPU time | 555.1 seconds |
| Started | Sep 09 02:03:16 PM UTC 24 |
| Finished | Sep 09 02:12:38 PM UTC 24 |
| Peak memory | 399888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372753940 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2372753940 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.3454148847 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2386660953 ps |
| CPU time | 66.83 seconds |
| Started | Sep 09 02:02:55 PM UTC 24 |
| Finished | Sep 09 02:04:04 PM UTC 24 |
| Peak memory | 234232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454148847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3454148847 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.1221964950 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 51949706392 ps |
| CPU time | 366.9 seconds |
| Started | Sep 09 02:04:57 PM UTC 24 |
| Finished | Sep 09 02:11:09 PM UTC 24 |
| Peak memory | 351272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221964950 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1221964950 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.2371820256 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 65278242 ps |
| CPU time | 4.04 seconds |
| Started | Sep 09 02:04:31 PM UTC 24 |
| Finished | Sep 09 02:04:36 PM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371820256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.2371820256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.408987771 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 83477748 ps |
| CPU time | 3.92 seconds |
| Started | Sep 09 02:04:31 PM UTC 24 |
| Finished | Sep 09 02:04:36 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408987771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.408987771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.947540053 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 10098099808 ps |
| CPU time | 67.14 seconds |
| Started | Sep 09 02:03:29 PM UTC 24 |
| Finished | Sep 09 02:04:39 PM UTC 24 |
| Peak memory | 260604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947540053 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.947540053 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3599901729 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2042812781 ps |
| CPU time | 41.28 seconds |
| Started | Sep 09 02:03:56 PM UTC 24 |
| Finished | Sep 09 02:04:38 PM UTC 24 |
| Peak memory | 256344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599901729 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3599901729 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2837547809 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 122782987428 ps |
| CPU time | 2226.79 seconds |
| Started | Sep 09 02:03:58 PM UTC 24 |
| Finished | Sep 09 02:41:29 PM UTC 24 |
| Peak memory | 2392516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837547809 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2837547809 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3970049663 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2324513558 ps |
| CPU time | 24.08 seconds |
| Started | Sep 09 02:04:05 PM UTC 24 |
| Finished | Sep 09 02:04:30 PM UTC 24 |
| Peak memory | 228140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970049663 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3970049663 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1937326806 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 8835141337 ps |
| CPU time | 240.15 seconds |
| Started | Sep 09 02:04:17 PM UTC 24 |
| Finished | Sep 09 02:08:21 PM UTC 24 |
| Peak memory | 244264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937326806 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1937326806 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.734781863 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 117766441125 ps |
| CPU time | 396.18 seconds |
| Started | Sep 09 02:04:23 PM UTC 24 |
| Finished | Sep 09 02:11:04 PM UTC 24 |
| Peak memory | 369096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734781863 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.734781863 +ena ble_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.2838033762 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 38935768 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 02:50:35 PM UTC 24 |
| Finished | Sep 09 02:50:37 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838033762 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2838033762 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_app.3967974014 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2870247422 ps |
| CPU time | 156.15 seconds |
| Started | Sep 09 02:49:31 PM UTC 24 |
| Finished | Sep 09 02:52:10 PM UTC 24 |
| Peak memory | 291368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967974014 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3967974014 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.560069032 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 17596392520 ps |
| CPU time | 213.6 seconds |
| Started | Sep 09 02:49:20 PM UTC 24 |
| Finished | Sep 09 02:52:57 PM UTC 24 |
| Peak memory | 238124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560069032 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.560069032 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.3605523855 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 29558838418 ps |
| CPU time | 135.68 seconds |
| Started | Sep 09 02:49:34 PM UTC 24 |
| Finished | Sep 09 02:51:52 PM UTC 24 |
| Peak memory | 334380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605523855 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3605523855 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_error.2329467304 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4611252680 ps |
| CPU time | 115.4 seconds |
| Started | Sep 09 02:49:55 PM UTC 24 |
| Finished | Sep 09 02:51:53 PM UTC 24 |
| Peak memory | 279156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329467304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2329467304 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.1815226874 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 8058180135 ps |
| CPU time | 7.37 seconds |
| Started | Sep 09 02:49:58 PM UTC 24 |
| Finished | Sep 09 02:50:07 PM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815226874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1815226874 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.184706868 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 443264342 ps |
| CPU time | 36.54 seconds |
| Started | Sep 09 02:50:08 PM UTC 24 |
| Finished | Sep 09 02:50:46 PM UTC 24 |
| Peak memory | 252472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184706868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.184706868 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.2803546380 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 172732918234 ps |
| CPU time | 2931.09 seconds |
| Started | Sep 09 02:49:12 PM UTC 24 |
| Finished | Sep 09 03:38:35 PM UTC 24 |
| Peak memory | 3213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803546380 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.2803546380 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.3652375917 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 15422654557 ps |
| CPU time | 307.67 seconds |
| Started | Sep 09 02:49:13 PM UTC 24 |
| Finished | Sep 09 02:54:25 PM UTC 24 |
| Peak memory | 330404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652375917 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3652375917 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.545323429 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 5663836317 ps |
| CPU time | 44.27 seconds |
| Started | Sep 09 02:49:08 PM UTC 24 |
| Finished | Sep 09 02:49:54 PM UTC 24 |
| Peak memory | 236156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545323429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.545323429 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.3641390723 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 150365669945 ps |
| CPU time | 444.51 seconds |
| Started | Sep 09 02:50:31 PM UTC 24 |
| Finished | Sep 09 02:58:02 PM UTC 24 |
| Peak memory | 377780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641390723 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3641390723 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.1901378077 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 52471335 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 02:51:38 PM UTC 24 |
| Finished | Sep 09 02:51:40 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901378077 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1901378077 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_app.3215337389 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 15971714404 ps |
| CPU time | 209.94 seconds |
| Started | Sep 09 02:50:49 PM UTC 24 |
| Finished | Sep 09 02:54:22 PM UTC 24 |
| Peak memory | 373284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215337389 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3215337389 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.1588060268 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 66770823259 ps |
| CPU time | 871.96 seconds |
| Started | Sep 09 02:50:46 PM UTC 24 |
| Finished | Sep 09 03:05:29 PM UTC 24 |
| Peak memory | 258600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588060268 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1588060268 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.4256802177 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 9706779512 ps |
| CPU time | 114.78 seconds |
| Started | Sep 09 02:50:52 PM UTC 24 |
| Finished | Sep 09 02:52:49 PM UTC 24 |
| Peak memory | 297488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256802177 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.4256802177 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_error.3098108846 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2318131281 ps |
| CPU time | 74.8 seconds |
| Started | Sep 09 02:51:17 PM UTC 24 |
| Finished | Sep 09 02:52:34 PM UTC 24 |
| Peak memory | 283180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098108846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3098108846 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.3465890666 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 5028036521 ps |
| CPU time | 16.07 seconds |
| Started | Sep 09 02:51:18 PM UTC 24 |
| Finished | Sep 09 02:51:35 PM UTC 24 |
| Peak memory | 228016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465890666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3465890666 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.2278817311 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 84826502 ps |
| CPU time | 2.29 seconds |
| Started | Sep 09 02:51:33 PM UTC 24 |
| Finished | Sep 09 02:51:37 PM UTC 24 |
| Peak memory | 234052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278817311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2278817311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.4127843107 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 10614793562 ps |
| CPU time | 682.72 seconds |
| Started | Sep 09 02:50:42 PM UTC 24 |
| Finished | Sep 09 03:02:14 PM UTC 24 |
| Peak memory | 545376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127843107 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.4127843107 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.1020678009 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 9518964411 ps |
| CPU time | 295.8 seconds |
| Started | Sep 09 02:50:43 PM UTC 24 |
| Finished | Sep 09 02:55:44 PM UTC 24 |
| Peak memory | 436840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020678009 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1020678009 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.4130058737 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 9502034502 ps |
| CPU time | 36.32 seconds |
| Started | Sep 09 02:50:38 PM UTC 24 |
| Finished | Sep 09 02:51:16 PM UTC 24 |
| Peak memory | 236132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130058737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.4130058737 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.3164433520 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 128855306645 ps |
| CPU time | 2678.38 seconds |
| Started | Sep 09 02:51:36 PM UTC 24 |
| Finished | Sep 09 03:36:49 PM UTC 24 |
| Peak memory | 1319824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164433520 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3164433520 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.719472332 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 30393384 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 02:52:42 PM UTC 24 |
| Finished | Sep 09 02:52:44 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719472332 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.719472332 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_app.1977816199 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 13381909879 ps |
| CPU time | 298.08 seconds |
| Started | Sep 09 02:52:09 PM UTC 24 |
| Finished | Sep 09 02:57:12 PM UTC 24 |
| Peak memory | 479836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977816199 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1977816199 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.1027453086 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 613557177 ps |
| CPU time | 40.36 seconds |
| Started | Sep 09 02:52:01 PM UTC 24 |
| Finished | Sep 09 02:52:43 PM UTC 24 |
| Peak memory | 246240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027453086 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1027453086 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.4011591153 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3223240498 ps |
| CPU time | 97.53 seconds |
| Started | Sep 09 02:52:10 PM UTC 24 |
| Finished | Sep 09 02:53:50 PM UTC 24 |
| Peak memory | 264852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011591153 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.4011591153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_error.131716315 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 9145530965 ps |
| CPU time | 413.84 seconds |
| Started | Sep 09 02:52:18 PM UTC 24 |
| Finished | Sep 09 02:59:17 PM UTC 24 |
| Peak memory | 371284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131716315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.131716315 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.2519911862 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 9550559190 ps |
| CPU time | 21.46 seconds |
| Started | Sep 09 02:52:19 PM UTC 24 |
| Finished | Sep 09 02:52:41 PM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519911862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2519911862 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.357380874 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13826413014 ps |
| CPU time | 26.79 seconds |
| Started | Sep 09 02:52:30 PM UTC 24 |
| Finished | Sep 09 02:52:58 PM UTC 24 |
| Peak memory | 268976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357380874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.357380874 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.1761402559 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 28534824391 ps |
| CPU time | 948.23 seconds |
| Started | Sep 09 02:51:53 PM UTC 24 |
| Finished | Sep 09 03:07:53 PM UTC 24 |
| Peak memory | 1223276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761402559 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.1761402559 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.1127309501 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 42601199109 ps |
| CPU time | 394.2 seconds |
| Started | Sep 09 02:51:54 PM UTC 24 |
| Finished | Sep 09 02:58:34 PM UTC 24 |
| Peak memory | 365164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127309501 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1127309501 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.2059732218 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 13295797704 ps |
| CPU time | 78.26 seconds |
| Started | Sep 09 02:51:41 PM UTC 24 |
| Finished | Sep 09 02:53:01 PM UTC 24 |
| Peak memory | 236072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059732218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2059732218 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.3898472399 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 96882871937 ps |
| CPU time | 3401.84 seconds |
| Started | Sep 09 02:52:35 PM UTC 24 |
| Finished | Sep 09 03:49:56 PM UTC 24 |
| Peak memory | 1366960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898472399 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3898472399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.3355238966 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 47732559 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 02:53:32 PM UTC 24 |
| Finished | Sep 09 02:53:34 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355238966 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3355238966 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_app.1655715145 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 12113712429 ps |
| CPU time | 373.72 seconds |
| Started | Sep 09 02:52:59 PM UTC 24 |
| Finished | Sep 09 02:59:18 PM UTC 24 |
| Peak memory | 453156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655715145 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1655715145 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.2289708782 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 58430394298 ps |
| CPU time | 1569.94 seconds |
| Started | Sep 09 02:52:58 PM UTC 24 |
| Finished | Sep 09 03:19:26 PM UTC 24 |
| Peak memory | 256612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289708782 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2289708782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.1807474833 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 27918450016 ps |
| CPU time | 62.27 seconds |
| Started | Sep 09 02:53:02 PM UTC 24 |
| Finished | Sep 09 02:54:06 PM UTC 24 |
| Peak memory | 260708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807474833 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1807474833 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_error.2127512344 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 10274060669 ps |
| CPU time | 251.61 seconds |
| Started | Sep 09 02:53:02 PM UTC 24 |
| Finished | Sep 09 02:57:18 PM UTC 24 |
| Peak memory | 318004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127512344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2127512344 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.3244774872 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1354078818 ps |
| CPU time | 16.4 seconds |
| Started | Sep 09 02:53:13 PM UTC 24 |
| Finished | Sep 09 02:53:31 PM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244774872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3244774872 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.3560171966 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 60095316 ps |
| CPU time | 3.16 seconds |
| Started | Sep 09 02:53:26 PM UTC 24 |
| Finished | Sep 09 02:53:31 PM UTC 24 |
| Peak memory | 234088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560171966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3560171966 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.2451602815 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 130130675462 ps |
| CPU time | 5500.05 seconds |
| Started | Sep 09 02:52:45 PM UTC 24 |
| Finished | Sep 09 04:25:26 PM UTC 24 |
| Peak memory | 5020432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451602815 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.2451602815 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.36914918 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 21494816649 ps |
| CPU time | 534.12 seconds |
| Started | Sep 09 02:52:49 PM UTC 24 |
| Finished | Sep 09 03:01:52 PM UTC 24 |
| Peak memory | 381544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36914918 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.36914918 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.626087752 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1262497529 ps |
| CPU time | 15.31 seconds |
| Started | Sep 09 02:52:44 PM UTC 24 |
| Finished | Sep 09 02:53:01 PM UTC 24 |
| Peak memory | 232040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626087752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.626087752 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.1396071258 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 24430949366 ps |
| CPU time | 298.37 seconds |
| Started | Sep 09 02:53:32 PM UTC 24 |
| Finished | Sep 09 02:58:34 PM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396071258 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1396071258 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.199004508 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 13159941 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 02:54:53 PM UTC 24 |
| Finished | Sep 09 02:54:55 PM UTC 24 |
| Peak memory | 226840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199004508 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.199004508 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_app.3765652917 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 6951859927 ps |
| CPU time | 152.58 seconds |
| Started | Sep 09 02:54:07 PM UTC 24 |
| Finished | Sep 09 02:56:42 PM UTC 24 |
| Peak memory | 293520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765652917 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3765652917 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.2093325077 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 21634973140 ps |
| CPU time | 957.77 seconds |
| Started | Sep 09 02:54:07 PM UTC 24 |
| Finished | Sep 09 03:10:17 PM UTC 24 |
| Peak memory | 262692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093325077 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.2093325077 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2715226866 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 12080227134 ps |
| CPU time | 476.17 seconds |
| Started | Sep 09 02:54:23 PM UTC 24 |
| Finished | Sep 09 03:02:26 PM UTC 24 |
| Peak memory | 492220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715226866 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2715226866 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_error.1395879996 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 18253947340 ps |
| CPU time | 247.95 seconds |
| Started | Sep 09 02:54:26 PM UTC 24 |
| Finished | Sep 09 02:58:37 PM UTC 24 |
| Peak memory | 334380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395879996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1395879996 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.282386954 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5200864493 ps |
| CPU time | 13.2 seconds |
| Started | Sep 09 02:54:38 PM UTC 24 |
| Finished | Sep 09 02:54:52 PM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282386954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.282386954 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.3324216543 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 814213439 ps |
| CPU time | 33.46 seconds |
| Started | Sep 09 02:54:40 PM UTC 24 |
| Finished | Sep 09 02:55:15 PM UTC 24 |
| Peak memory | 262628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324216543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3324216543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3920677367 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 333867229778 ps |
| CPU time | 2905.09 seconds |
| Started | Sep 09 02:53:35 PM UTC 24 |
| Finished | Sep 09 03:42:32 PM UTC 24 |
| Peak memory | 3234408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920677367 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3920677367 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.1160962488 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 9679105352 ps |
| CPU time | 253.74 seconds |
| Started | Sep 09 02:53:51 PM UTC 24 |
| Finished | Sep 09 02:58:09 PM UTC 24 |
| Peak memory | 418400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160962488 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1160962488 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.2434643441 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 7106374783 ps |
| CPU time | 59.77 seconds |
| Started | Sep 09 02:53:35 PM UTC 24 |
| Finished | Sep 09 02:54:36 PM UTC 24 |
| Peak memory | 234464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434643441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2434643441 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.1349172074 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3562750334 ps |
| CPU time | 20.77 seconds |
| Started | Sep 09 02:54:45 PM UTC 24 |
| Finished | Sep 09 02:55:07 PM UTC 24 |
| Peak memory | 246684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349172074 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1349172074 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.1204452793 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 121180694 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 02:56:21 PM UTC 24 |
| Finished | Sep 09 02:56:23 PM UTC 24 |
| Peak memory | 226600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204452793 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1204452793 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_app.1292026591 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1987376058 ps |
| CPU time | 57.92 seconds |
| Started | Sep 09 02:55:45 PM UTC 24 |
| Finished | Sep 09 02:56:45 PM UTC 24 |
| Peak memory | 258464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292026591 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1292026591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.2580504412 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 44559810284 ps |
| CPU time | 454.94 seconds |
| Started | Sep 09 02:55:16 PM UTC 24 |
| Finished | Sep 09 03:02:57 PM UTC 24 |
| Peak memory | 246372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580504412 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.2580504412 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.3685217256 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 28670193412 ps |
| CPU time | 96.37 seconds |
| Started | Sep 09 02:55:45 PM UTC 24 |
| Finished | Sep 09 02:57:24 PM UTC 24 |
| Peak memory | 303664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685217256 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3685217256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_error.3963759632 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 11105499996 ps |
| CPU time | 229.79 seconds |
| Started | Sep 09 02:55:54 PM UTC 24 |
| Finished | Sep 09 02:59:48 PM UTC 24 |
| Peak memory | 391852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963759632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3963759632 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.4159178787 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2520509049 ps |
| CPU time | 9.7 seconds |
| Started | Sep 09 02:55:55 PM UTC 24 |
| Finished | Sep 09 02:56:06 PM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159178787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.4159178787 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.620384945 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 24749838 ps |
| CPU time | 1.8 seconds |
| Started | Sep 09 02:56:07 PM UTC 24 |
| Finished | Sep 09 02:56:10 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620384945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.620384945 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.2286239352 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 70948619027 ps |
| CPU time | 1042.02 seconds |
| Started | Sep 09 02:55:04 PM UTC 24 |
| Finished | Sep 09 03:12:39 PM UTC 24 |
| Peak memory | 1528440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286239352 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.2286239352 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.3772313055 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 438803786 ps |
| CPU time | 44.05 seconds |
| Started | Sep 09 02:55:08 PM UTC 24 |
| Finished | Sep 09 02:55:53 PM UTC 24 |
| Peak memory | 244200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772313055 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3772313055 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.1873948047 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2763624099 ps |
| CPU time | 46.03 seconds |
| Started | Sep 09 02:54:56 PM UTC 24 |
| Finished | Sep 09 02:55:44 PM UTC 24 |
| Peak memory | 234300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873948047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1873948047 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.1789265132 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 170243224811 ps |
| CPU time | 569.7 seconds |
| Started | Sep 09 02:56:12 PM UTC 24 |
| Finished | Sep 09 03:05:49 PM UTC 24 |
| Peak memory | 394100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789265132 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1789265132 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.1527406262 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 56316034 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 02:57:24 PM UTC 24 |
| Finished | Sep 09 02:57:27 PM UTC 24 |
| Peak memory | 226600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527406262 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1527406262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_app.3191328513 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 62443299028 ps |
| CPU time | 485.9 seconds |
| Started | Sep 09 02:56:45 PM UTC 24 |
| Finished | Sep 09 03:04:58 PM UTC 24 |
| Peak memory | 541268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191328513 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3191328513 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.522132262 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 17308301479 ps |
| CPU time | 495.89 seconds |
| Started | Sep 09 02:56:43 PM UTC 24 |
| Finished | Sep 09 03:05:06 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522132262 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.522132262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2612001310 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 73053106843 ps |
| CPU time | 329.46 seconds |
| Started | Sep 09 02:56:58 PM UTC 24 |
| Finished | Sep 09 03:02:33 PM UTC 24 |
| Peak memory | 334472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612001310 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2612001310 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_error.3281337329 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 120232838289 ps |
| CPU time | 494.59 seconds |
| Started | Sep 09 02:57:02 PM UTC 24 |
| Finished | Sep 09 03:05:23 PM UTC 24 |
| Peak memory | 563756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281337329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3281337329 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.1429569394 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1178336261 ps |
| CPU time | 15.31 seconds |
| Started | Sep 09 02:57:07 PM UTC 24 |
| Finished | Sep 09 02:57:23 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429569394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1429569394 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.3392295449 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 425736400 ps |
| CPU time | 21.18 seconds |
| Started | Sep 09 02:57:13 PM UTC 24 |
| Finished | Sep 09 02:57:36 PM UTC 24 |
| Peak memory | 246324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392295449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3392295449 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.828603679 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 46870107085 ps |
| CPU time | 750.24 seconds |
| Started | Sep 09 02:56:27 PM UTC 24 |
| Finished | Sep 09 03:09:07 PM UTC 24 |
| Peak memory | 1077852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828603679 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.828603679 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.293830122 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 20568171836 ps |
| CPU time | 433.5 seconds |
| Started | Sep 09 02:56:42 PM UTC 24 |
| Finished | Sep 09 03:04:01 PM UTC 24 |
| Peak memory | 371364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293830122 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.293830122 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.1812097095 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1952295151 ps |
| CPU time | 32.03 seconds |
| Started | Sep 09 02:56:24 PM UTC 24 |
| Finished | Sep 09 02:56:57 PM UTC 24 |
| Peak memory | 235992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812097095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1812097095 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.23348000 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 105923607386 ps |
| CPU time | 1026.5 seconds |
| Started | Sep 09 02:57:18 PM UTC 24 |
| Finished | Sep 09 03:14:39 PM UTC 24 |
| Peak memory | 351132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23348000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.23348000 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.3443889925 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 33517229 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 02:58:43 PM UTC 24 |
| Finished | Sep 09 02:58:45 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443889925 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3443889925 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_app.2416160575 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1324002617 ps |
| CPU time | 96.52 seconds |
| Started | Sep 09 02:58:03 PM UTC 24 |
| Finished | Sep 09 02:59:42 PM UTC 24 |
| Peak memory | 258656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416160575 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2416160575 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.3135706286 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 19296594270 ps |
| CPU time | 460.1 seconds |
| Started | Sep 09 02:57:54 PM UTC 24 |
| Finished | Sep 09 03:05:40 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135706286 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3135706286 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.3003176773 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 16544070996 ps |
| CPU time | 102.77 seconds |
| Started | Sep 09 02:58:09 PM UTC 24 |
| Finished | Sep 09 02:59:54 PM UTC 24 |
| Peak memory | 281216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003176773 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3003176773 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_error.3191172639 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1543352974 ps |
| CPU time | 54.49 seconds |
| Started | Sep 09 02:58:10 PM UTC 24 |
| Finished | Sep 09 02:59:06 PM UTC 24 |
| Peak memory | 262608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191172639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3191172639 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.1101375770 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1296394631 ps |
| CPU time | 6.51 seconds |
| Started | Sep 09 02:58:34 PM UTC 24 |
| Finished | Sep 09 02:58:42 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101375770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1101375770 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.3170506225 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 529232368 ps |
| CPU time | 14.08 seconds |
| Started | Sep 09 02:58:35 PM UTC 24 |
| Finished | Sep 09 02:58:51 PM UTC 24 |
| Peak memory | 246272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170506225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3170506225 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.2813657344 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 49110405406 ps |
| CPU time | 786.87 seconds |
| Started | Sep 09 02:57:27 PM UTC 24 |
| Finished | Sep 09 03:10:45 PM UTC 24 |
| Peak memory | 1102512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813657344 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.2813657344 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.57273299 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 33010298589 ps |
| CPU time | 106.27 seconds |
| Started | Sep 09 02:57:37 PM UTC 24 |
| Finished | Sep 09 02:59:25 PM UTC 24 |
| Peak memory | 316072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57273299 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.57273299 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.4010119031 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 6605999229 ps |
| CPU time | 78.76 seconds |
| Started | Sep 09 02:57:24 PM UTC 24 |
| Finished | Sep 09 02:58:45 PM UTC 24 |
| Peak memory | 236132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010119031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.4010119031 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.2461239454 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 239662105482 ps |
| CPU time | 2276.34 seconds |
| Started | Sep 09 02:58:39 PM UTC 24 |
| Finished | Sep 09 03:37:02 PM UTC 24 |
| Peak memory | 1592244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461239454 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2461239454 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.3426674830 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 13834200 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 02:59:33 PM UTC 24 |
| Finished | Sep 09 02:59:35 PM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426674830 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3426674830 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_app.2389811437 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2090043151 ps |
| CPU time | 90.54 seconds |
| Started | Sep 09 02:59:19 PM UTC 24 |
| Finished | Sep 09 03:00:51 PM UTC 24 |
| Peak memory | 262536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389811437 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.2389811437 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.3590877324 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 22969864634 ps |
| CPU time | 1138.93 seconds |
| Started | Sep 09 02:59:07 PM UTC 24 |
| Finished | Sep 09 03:18:19 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590877324 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3590877324 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.2451153488 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 47116930125 ps |
| CPU time | 111.34 seconds |
| Started | Sep 09 02:59:19 PM UTC 24 |
| Finished | Sep 09 03:01:12 PM UTC 24 |
| Peak memory | 322148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451153488 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2451153488 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_error.2532487932 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2009387151 ps |
| CPU time | 199.83 seconds |
| Started | Sep 09 02:59:19 PM UTC 24 |
| Finished | Sep 09 03:02:42 PM UTC 24 |
| Peak memory | 303528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532487932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2532487932 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.1191030868 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1679315518 ps |
| CPU time | 6.66 seconds |
| Started | Sep 09 02:59:26 PM UTC 24 |
| Finished | Sep 09 02:59:33 PM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191030868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1191030868 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.4013931682 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 29053999 ps |
| CPU time | 2.01 seconds |
| Started | Sep 09 02:59:27 PM UTC 24 |
| Finished | Sep 09 02:59:30 PM UTC 24 |
| Peak memory | 233632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013931682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.4013931682 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.3878512601 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 170572184842 ps |
| CPU time | 4600.35 seconds |
| Started | Sep 09 02:58:46 PM UTC 24 |
| Finished | Sep 09 04:16:22 PM UTC 24 |
| Peak memory | 4127396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878512601 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.3878512601 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.3977719986 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 28352801128 ps |
| CPU time | 228.2 seconds |
| Started | Sep 09 02:58:52 PM UTC 24 |
| Finished | Sep 09 03:02:44 PM UTC 24 |
| Peak memory | 375392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977719986 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3977719986 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.3815668389 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1700196253 ps |
| CPU time | 44.74 seconds |
| Started | Sep 09 02:58:46 PM UTC 24 |
| Finished | Sep 09 02:59:32 PM UTC 24 |
| Peak memory | 236004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815668389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3815668389 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.1621240576 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 34974028259 ps |
| CPU time | 738.52 seconds |
| Started | Sep 09 02:59:31 PM UTC 24 |
| Finished | Sep 09 03:11:59 PM UTC 24 |
| Peak memory | 535408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621240576 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1621240576 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.4062385333 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 71439284 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 03:00:52 PM UTC 24 |
| Finished | Sep 09 03:00:54 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062385333 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.4062385333 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_app.2481553069 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 12603150864 ps |
| CPU time | 207.49 seconds |
| Started | Sep 09 02:59:55 PM UTC 24 |
| Finished | Sep 09 03:03:26 PM UTC 24 |
| Peak memory | 352784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481553069 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2481553069 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.2498520948 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4927070089 ps |
| CPU time | 343.66 seconds |
| Started | Sep 09 02:59:49 PM UTC 24 |
| Finished | Sep 09 03:05:38 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498520948 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2498520948 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.1981079388 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 7418923814 ps |
| CPU time | 222.23 seconds |
| Started | Sep 09 02:59:55 PM UTC 24 |
| Finished | Sep 09 03:03:41 PM UTC 24 |
| Peak memory | 393900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981079388 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1981079388 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_error.4253737142 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 28278307892 ps |
| CPU time | 92.51 seconds |
| Started | Sep 09 03:00:20 PM UTC 24 |
| Finished | Sep 09 03:01:55 PM UTC 24 |
| Peak memory | 301600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253737142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.4253737142 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.1191141796 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 860177729 ps |
| CPU time | 11.96 seconds |
| Started | Sep 09 03:00:28 PM UTC 24 |
| Finished | Sep 09 03:00:41 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191141796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1191141796 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.4038520928 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 27120391 ps |
| CPU time | 2.2 seconds |
| Started | Sep 09 03:00:42 PM UTC 24 |
| Finished | Sep 09 03:00:46 PM UTC 24 |
| Peak memory | 231976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038520928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.4038520928 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.55517644 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 125735908089 ps |
| CPU time | 3328.77 seconds |
| Started | Sep 09 02:59:36 PM UTC 24 |
| Finished | Sep 09 03:55:46 PM UTC 24 |
| Peak memory | 3062364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55517644 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.55517644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.1188775507 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1868755357 ps |
| CPU time | 43.53 seconds |
| Started | Sep 09 02:59:43 PM UTC 24 |
| Finished | Sep 09 03:00:28 PM UTC 24 |
| Peak memory | 254376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188775507 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1188775507 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.1320045576 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 14536659336 ps |
| CPU time | 78.86 seconds |
| Started | Sep 09 02:59:34 PM UTC 24 |
| Finished | Sep 09 03:00:55 PM UTC 24 |
| Peak memory | 236080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320045576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1320045576 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.1497267637 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 31627977277 ps |
| CPU time | 303.17 seconds |
| Started | Sep 09 03:00:47 PM UTC 24 |
| Finished | Sep 09 03:05:54 PM UTC 24 |
| Peak memory | 268944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497267637 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1497267637 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.4166314716 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 31932305 ps |
| CPU time | 1.34 seconds |
| Started | Sep 09 02:11:05 PM UTC 24 |
| Finished | Sep 09 02:11:07 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166314716 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.4166314716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_app.4052426505 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3276639217 ps |
| CPU time | 156.48 seconds |
| Started | Sep 09 02:07:53 PM UTC 24 |
| Finished | Sep 09 02:10:32 PM UTC 24 |
| Peak memory | 281264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052426505 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.4052426505 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.3212032039 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3112044897 ps |
| CPU time | 92.35 seconds |
| Started | Sep 09 02:08:22 PM UTC 24 |
| Finished | Sep 09 02:09:56 PM UTC 24 |
| Peak memory | 279148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212032039 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3212032039 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.2181068211 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 122554698420 ps |
| CPU time | 1323.4 seconds |
| Started | Sep 09 02:05:32 PM UTC 24 |
| Finished | Sep 09 02:27:51 PM UTC 24 |
| Peak memory | 268820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181068211 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2181068211 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.2138739585 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 283341742 ps |
| CPU time | 28.52 seconds |
| Started | Sep 09 02:10:33 PM UTC 24 |
| Finished | Sep 09 02:11:03 PM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138739585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2138739585 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2781193878 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 381185512 ps |
| CPU time | 1.78 seconds |
| Started | Sep 09 02:10:33 PM UTC 24 |
| Finished | Sep 09 02:10:36 PM UTC 24 |
| Peak memory | 224688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781193878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2781193878 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1415598839 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5267148369 ps |
| CPU time | 331.35 seconds |
| Started | Sep 09 02:08:44 PM UTC 24 |
| Finished | Sep 09 02:14:20 PM UTC 24 |
| Peak memory | 313904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415598839 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1415598839 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.2605607834 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1356317534 ps |
| CPU time | 8.58 seconds |
| Started | Sep 09 02:10:33 PM UTC 24 |
| Finished | Sep 09 02:10:43 PM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605607834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2605607834 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.1062992942 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 56758822 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 02:10:39 PM UTC 24 |
| Finished | Sep 09 02:10:42 PM UTC 24 |
| Peak memory | 233636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062992942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1062992942 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1329670680 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 23464268296 ps |
| CPU time | 318.39 seconds |
| Started | Sep 09 02:05:15 PM UTC 24 |
| Finished | Sep 09 02:10:39 PM UTC 24 |
| Peak memory | 508580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329670680 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1329670680 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.1911849409 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 9318207015 ps |
| CPU time | 285.02 seconds |
| Started | Sep 09 02:09:33 PM UTC 24 |
| Finished | Sep 09 02:14:23 PM UTC 24 |
| Peak memory | 324644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911849409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1911849409 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.904781497 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 16915183590 ps |
| CPU time | 112.82 seconds |
| Started | Sep 09 02:10:43 PM UTC 24 |
| Finished | Sep 09 02:12:38 PM UTC 24 |
| Peak memory | 325400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904781497 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.904781497 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.910768717 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 25920054553 ps |
| CPU time | 648.62 seconds |
| Started | Sep 09 02:05:20 PM UTC 24 |
| Finished | Sep 09 02:16:16 PM UTC 24 |
| Peak memory | 639516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910768717 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.910768717 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.369767857 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1937375152 ps |
| CPU time | 14.4 seconds |
| Started | Sep 09 02:05:14 PM UTC 24 |
| Finished | Sep 09 02:05:30 PM UTC 24 |
| Peak memory | 235856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369767857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.369767857 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.973403331 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 61236149078 ps |
| CPU time | 1257.65 seconds |
| Started | Sep 09 02:10:40 PM UTC 24 |
| Finished | Sep 09 02:31:51 PM UTC 24 |
| Peak memory | 922152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973403331 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.973403331 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all_with_rand_reset.2987294614 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2382972998 ps |
| CPU time | 81.43 seconds |
| Started | Sep 09 02:10:43 PM UTC 24 |
| Finished | Sep 09 02:12:07 PM UTC 24 |
| Peak memory | 268356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2987294614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_r and_reset.2987294614 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1261410887 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 166211152 ps |
| CPU time | 3.39 seconds |
| Started | Sep 09 02:07:41 PM UTC 24 |
| Finished | Sep 09 02:07:46 PM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261410887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1261410887 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.2465623334 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 235554650 ps |
| CPU time | 4.64 seconds |
| Started | Sep 09 02:07:46 PM UTC 24 |
| Finished | Sep 09 02:07:52 PM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465623334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2465623334 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.4051483285 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 31320316325 ps |
| CPU time | 1924.8 seconds |
| Started | Sep 09 02:05:50 PM UTC 24 |
| Finished | Sep 09 02:38:15 PM UTC 24 |
| Peak memory | 1196476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051483285 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4051483285 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.3489104790 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4217812591 ps |
| CPU time | 46.1 seconds |
| Started | Sep 09 02:06:20 PM UTC 24 |
| Finished | Sep 09 02:07:08 PM UTC 24 |
| Peak memory | 234244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489104790 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3489104790 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3980797896 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1053446942 ps |
| CPU time | 23.67 seconds |
| Started | Sep 09 02:06:59 PM UTC 24 |
| Finished | Sep 09 02:07:24 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980797896 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3980797896 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.2678450441 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 188239051575 ps |
| CPU time | 1678.67 seconds |
| Started | Sep 09 02:07:09 PM UTC 24 |
| Finished | Sep 09 02:35:27 PM UTC 24 |
| Peak memory | 1722884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678450441 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2678450441 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.2396108159 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 165463611015 ps |
| CPU time | 371.57 seconds |
| Started | Sep 09 02:07:25 PM UTC 24 |
| Finished | Sep 09 02:13:42 PM UTC 24 |
| Peak memory | 285340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396108159 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2396108159 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.3742327072 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 44949348892 ps |
| CPU time | 374.96 seconds |
| Started | Sep 09 02:07:25 PM UTC 24 |
| Finished | Sep 09 02:13:45 PM UTC 24 |
| Peak memory | 270788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742327072 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3742327072 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.677673262 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 12582554 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 03:01:57 PM UTC 24 |
| Finished | Sep 09 03:01:59 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677673262 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.677673262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_app.411572616 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 33144974026 ps |
| CPU time | 444.08 seconds |
| Started | Sep 09 03:01:12 PM UTC 24 |
| Finished | Sep 09 03:08:43 PM UTC 24 |
| Peak memory | 531008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411572616 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.411572616 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.3762985116 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 118034464456 ps |
| CPU time | 1260.52 seconds |
| Started | Sep 09 03:01:04 PM UTC 24 |
| Finished | Sep 09 03:22:19 PM UTC 24 |
| Peak memory | 254632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762985116 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3762985116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.1964703854 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 28552692451 ps |
| CPU time | 246.44 seconds |
| Started | Sep 09 03:01:15 PM UTC 24 |
| Finished | Sep 09 03:05:25 PM UTC 24 |
| Peak memory | 307820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964703854 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1964703854 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_error.1680394782 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 22329878843 ps |
| CPU time | 441.92 seconds |
| Started | Sep 09 03:01:19 PM UTC 24 |
| Finished | Sep 09 03:08:47 PM UTC 24 |
| Peak memory | 514672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680394782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1680394782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2691489873 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 12557934393 ps |
| CPU time | 13.6 seconds |
| Started | Sep 09 03:01:52 PM UTC 24 |
| Finished | Sep 09 03:02:07 PM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691489873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2691489873 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.3742632716 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 50917719 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 03:01:53 PM UTC 24 |
| Finished | Sep 09 03:01:56 PM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742632716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3742632716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.910562772 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 794866648 ps |
| CPU time | 20.8 seconds |
| Started | Sep 09 03:00:56 PM UTC 24 |
| Finished | Sep 09 03:01:18 PM UTC 24 |
| Peak memory | 254352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910562772 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.910562772 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.287571513 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 26089371102 ps |
| CPU time | 152.82 seconds |
| Started | Sep 09 03:00:57 PM UTC 24 |
| Finished | Sep 09 03:03:33 PM UTC 24 |
| Peak memory | 354972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287571513 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.287571513 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.3738045440 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3121538461 ps |
| CPU time | 54.89 seconds |
| Started | Sep 09 03:00:55 PM UTC 24 |
| Finished | Sep 09 03:01:51 PM UTC 24 |
| Peak memory | 236136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738045440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3738045440 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.648738198 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 315138009581 ps |
| CPU time | 3270.77 seconds |
| Started | Sep 09 03:01:56 PM UTC 24 |
| Finished | Sep 09 03:57:07 PM UTC 24 |
| Peak memory | 1458736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648738198 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.648738198 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.2212070470 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 16242698 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 03:02:46 PM UTC 24 |
| Finished | Sep 09 03:02:48 PM UTC 24 |
| Peak memory | 227008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212070470 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2212070470 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_app.1004935078 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3441827313 ps |
| CPU time | 208.56 seconds |
| Started | Sep 09 03:02:15 PM UTC 24 |
| Finished | Sep 09 03:05:47 PM UTC 24 |
| Peak memory | 311916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004935078 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1004935078 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.970844962 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 54132391454 ps |
| CPU time | 370.45 seconds |
| Started | Sep 09 03:02:09 PM UTC 24 |
| Finished | Sep 09 03:08:24 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970844962 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.970844962 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.1310731265 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 130021415966 ps |
| CPU time | 436.19 seconds |
| Started | Sep 09 03:02:26 PM UTC 24 |
| Finished | Sep 09 03:09:48 PM UTC 24 |
| Peak memory | 475816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310731265 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1310731265 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_error.797191643 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 21959971118 ps |
| CPU time | 468.24 seconds |
| Started | Sep 09 03:02:27 PM UTC 24 |
| Finished | Sep 09 03:10:22 PM UTC 24 |
| Peak memory | 387708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797191643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.797191643 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.3956298315 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 785578887 ps |
| CPU time | 10.65 seconds |
| Started | Sep 09 03:02:33 PM UTC 24 |
| Finished | Sep 09 03:02:45 PM UTC 24 |
| Peak memory | 227880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956298315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3956298315 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.2957073613 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 58186107 ps |
| CPU time | 2.25 seconds |
| Started | Sep 09 03:02:43 PM UTC 24 |
| Finished | Sep 09 03:02:46 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957073613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2957073613 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.2078050927 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 183714863092 ps |
| CPU time | 1935.72 seconds |
| Started | Sep 09 03:02:05 PM UTC 24 |
| Finished | Sep 09 03:34:42 PM UTC 24 |
| Peak memory | 2304620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078050927 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.2078050927 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.2215908981 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 40765924599 ps |
| CPU time | 392.53 seconds |
| Started | Sep 09 03:02:08 PM UTC 24 |
| Finished | Sep 09 03:08:46 PM UTC 24 |
| Peak memory | 492136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215908981 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2215908981 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.4008223004 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 4571317843 ps |
| CPU time | 23.11 seconds |
| Started | Sep 09 03:02:00 PM UTC 24 |
| Finished | Sep 09 03:02:25 PM UTC 24 |
| Peak memory | 234236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008223004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.4008223004 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.20019470 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 17011588118 ps |
| CPU time | 432.25 seconds |
| Started | Sep 09 03:02:45 PM UTC 24 |
| Finished | Sep 09 03:10:02 PM UTC 24 |
| Peak memory | 394152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20019470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.20019470 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.4087674391 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 15080867 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 03:04:06 PM UTC 24 |
| Finished | Sep 09 03:04:09 PM UTC 24 |
| Peak memory | 226720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087674391 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.4087674391 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_app.4270366561 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3317210335 ps |
| CPU time | 46.44 seconds |
| Started | Sep 09 03:03:27 PM UTC 24 |
| Finished | Sep 09 03:04:15 PM UTC 24 |
| Peak memory | 242212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270366561 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.4270366561 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.2526655238 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 32857988231 ps |
| CPU time | 1530 seconds |
| Started | Sep 09 03:03:18 PM UTC 24 |
| Finished | Sep 09 03:29:07 PM UTC 24 |
| Peak memory | 277060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526655238 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2526655238 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.3994496267 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2994940188 ps |
| CPU time | 95.19 seconds |
| Started | Sep 09 03:03:34 PM UTC 24 |
| Finished | Sep 09 03:05:11 PM UTC 24 |
| Peak memory | 279140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994496267 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3994496267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_error.1413207503 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 5126456240 ps |
| CPU time | 390.81 seconds |
| Started | Sep 09 03:03:42 PM UTC 24 |
| Finished | Sep 09 03:10:18 PM UTC 24 |
| Peak memory | 379440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413207503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1413207503 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.621182854 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 651344249 ps |
| CPU time | 5.04 seconds |
| Started | Sep 09 03:03:58 PM UTC 24 |
| Finished | Sep 09 03:04:04 PM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621182854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.621182854 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.3851072605 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 60322577 ps |
| CPU time | 1.83 seconds |
| Started | Sep 09 03:04:02 PM UTC 24 |
| Finished | Sep 09 03:04:05 PM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851072605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3851072605 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.438112007 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 34583238622 ps |
| CPU time | 980.01 seconds |
| Started | Sep 09 03:02:49 PM UTC 24 |
| Finished | Sep 09 03:19:21 PM UTC 24 |
| Peak memory | 1415780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438112007 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.438112007 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.4103559785 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 28315085953 ps |
| CPU time | 418.56 seconds |
| Started | Sep 09 03:02:58 PM UTC 24 |
| Finished | Sep 09 03:10:03 PM UTC 24 |
| Peak memory | 535140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103559785 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.4103559785 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.266116035 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2114162017 ps |
| CPU time | 68.22 seconds |
| Started | Sep 09 03:02:47 PM UTC 24 |
| Finished | Sep 09 03:03:57 PM UTC 24 |
| Peak memory | 235928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266116035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.266116035 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.2748176590 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 74782873854 ps |
| CPU time | 2352.27 seconds |
| Started | Sep 09 03:04:05 PM UTC 24 |
| Finished | Sep 09 03:43:45 PM UTC 24 |
| Peak memory | 1444964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748176590 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2748176590 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.1082459037 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 18120986 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 03:05:28 PM UTC 24 |
| Finished | Sep 09 03:05:30 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082459037 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1082459037 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_app.1044120601 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 3313918869 ps |
| CPU time | 159.15 seconds |
| Started | Sep 09 03:04:59 PM UTC 24 |
| Finished | Sep 09 03:07:41 PM UTC 24 |
| Peak memory | 287304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044120601 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1044120601 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.3795747272 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 17658167886 ps |
| CPU time | 501.1 seconds |
| Started | Sep 09 03:04:36 PM UTC 24 |
| Finished | Sep 09 03:13:04 PM UTC 24 |
| Peak memory | 244328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795747272 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3795747272 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2513952871 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 484400098 ps |
| CPU time | 28.04 seconds |
| Started | Sep 09 03:05:04 PM UTC 24 |
| Finished | Sep 09 03:05:34 PM UTC 24 |
| Peak memory | 238080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513952871 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2513952871 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_error.233190975 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 24566577846 ps |
| CPU time | 310.42 seconds |
| Started | Sep 09 03:05:06 PM UTC 24 |
| Finished | Sep 09 03:10:21 PM UTC 24 |
| Peak memory | 516716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233190975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.233190975 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.1798206816 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 993126319 ps |
| CPU time | 14.68 seconds |
| Started | Sep 09 03:05:12 PM UTC 24 |
| Finished | Sep 09 03:05:27 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798206816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1798206816 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.1561743101 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 734084801 ps |
| CPU time | 41.71 seconds |
| Started | Sep 09 03:05:24 PM UTC 24 |
| Finished | Sep 09 03:06:07 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561743101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1561743101 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.14615636 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 451696891890 ps |
| CPU time | 5311.48 seconds |
| Started | Sep 09 03:04:10 PM UTC 24 |
| Finished | Sep 09 04:33:47 PM UTC 24 |
| Peak memory | 4440788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14615636 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.14615636 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.1864319780 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3165974741 ps |
| CPU time | 241.25 seconds |
| Started | Sep 09 03:04:16 PM UTC 24 |
| Finished | Sep 09 03:08:21 PM UTC 24 |
| Peak memory | 311908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864319780 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1864319780 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.101186677 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3014167146 ps |
| CPU time | 79.21 seconds |
| Started | Sep 09 03:04:08 PM UTC 24 |
| Finished | Sep 09 03:05:29 PM UTC 24 |
| Peak memory | 236112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101186677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.101186677 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.4249715404 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 23608382251 ps |
| CPU time | 2516.43 seconds |
| Started | Sep 09 03:05:26 PM UTC 24 |
| Finished | Sep 09 03:47:52 PM UTC 24 |
| Peak memory | 777084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249715404 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4249715404 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.1140366392 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 83984150 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 03:05:59 PM UTC 24 |
| Finished | Sep 09 03:06:02 PM UTC 24 |
| Peak memory | 225100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140366392 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1140366392 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_app.3797674322 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 9927049771 ps |
| CPU time | 282.54 seconds |
| Started | Sep 09 03:05:39 PM UTC 24 |
| Finished | Sep 09 03:10:26 PM UTC 24 |
| Peak memory | 307784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797674322 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3797674322 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.3832983254 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1896839340 ps |
| CPU time | 78.95 seconds |
| Started | Sep 09 03:05:35 PM UTC 24 |
| Finished | Sep 09 03:06:55 PM UTC 24 |
| Peak memory | 236004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832983254 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3832983254 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.177287794 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 11159853660 ps |
| CPU time | 221.05 seconds |
| Started | Sep 09 03:05:41 PM UTC 24 |
| Finished | Sep 09 03:09:25 PM UTC 24 |
| Peak memory | 291428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177287794 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.177287794 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_error.2575762962 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 15612376058 ps |
| CPU time | 276.05 seconds |
| Started | Sep 09 03:05:48 PM UTC 24 |
| Finished | Sep 09 03:10:29 PM UTC 24 |
| Peak memory | 317976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575762962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2575762962 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.711560269 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1124869057 ps |
| CPU time | 7.44 seconds |
| Started | Sep 09 03:05:50 PM UTC 24 |
| Finished | Sep 09 03:05:59 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711560269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.711560269 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.241732903 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 29505260 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 03:05:55 PM UTC 24 |
| Finished | Sep 09 03:05:58 PM UTC 24 |
| Peak memory | 234044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241732903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.241732903 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.1701644075 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 112869466642 ps |
| CPU time | 5220.29 seconds |
| Started | Sep 09 03:05:30 PM UTC 24 |
| Finished | Sep 09 04:33:31 PM UTC 24 |
| Peak memory | 4551200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701644075 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.1701644075 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.3259052326 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 36573222928 ps |
| CPU time | 104.06 seconds |
| Started | Sep 09 03:05:31 PM UTC 24 |
| Finished | Sep 09 03:07:18 PM UTC 24 |
| Peak memory | 313884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259052326 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3259052326 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.2179868938 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 4345915814 ps |
| CPU time | 71.63 seconds |
| Started | Sep 09 03:05:29 PM UTC 24 |
| Finished | Sep 09 03:06:42 PM UTC 24 |
| Peak memory | 236112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179868938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2179868938 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.3434462071 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 70657651087 ps |
| CPU time | 832.66 seconds |
| Started | Sep 09 03:05:59 PM UTC 24 |
| Finished | Sep 09 03:20:03 PM UTC 24 |
| Peak memory | 394100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434462071 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3434462071 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.1844969658 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 207751236 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 03:07:58 PM UTC 24 |
| Finished | Sep 09 03:08:00 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844969658 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1844969658 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_app.152923086 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 33546120080 ps |
| CPU time | 230.55 seconds |
| Started | Sep 09 03:06:56 PM UTC 24 |
| Finished | Sep 09 03:10:50 PM UTC 24 |
| Peak memory | 416356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152923086 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.152923086 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.1891254714 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 29613377769 ps |
| CPU time | 962.61 seconds |
| Started | Sep 09 03:06:43 PM UTC 24 |
| Finished | Sep 09 03:22:58 PM UTC 24 |
| Peak memory | 256548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891254714 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1891254714 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.3836633482 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 28350395934 ps |
| CPU time | 464.67 seconds |
| Started | Sep 09 03:07:18 PM UTC 24 |
| Finished | Sep 09 03:15:10 PM UTC 24 |
| Peak memory | 535052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836633482 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3836633482 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_error.2733589973 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 55825134710 ps |
| CPU time | 438.64 seconds |
| Started | Sep 09 03:07:42 PM UTC 24 |
| Finished | Sep 09 03:15:06 PM UTC 24 |
| Peak memory | 576100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733589973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2733589973 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.2435823026 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1003743099 ps |
| CPU time | 13.34 seconds |
| Started | Sep 09 03:07:42 PM UTC 24 |
| Finished | Sep 09 03:07:56 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435823026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2435823026 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.2663017678 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 89268685 ps |
| CPU time | 1.96 seconds |
| Started | Sep 09 03:07:54 PM UTC 24 |
| Finished | Sep 09 03:07:57 PM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663017678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2663017678 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.2201927701 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 89161126735 ps |
| CPU time | 5405.66 seconds |
| Started | Sep 09 03:06:08 PM UTC 24 |
| Finished | Sep 09 04:37:22 PM UTC 24 |
| Peak memory | 4182700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201927701 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.2201927701 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.2931638681 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 34728739160 ps |
| CPU time | 267.59 seconds |
| Started | Sep 09 03:06:26 PM UTC 24 |
| Finished | Sep 09 03:10:57 PM UTC 24 |
| Peak memory | 451116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931638681 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2931638681 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.1955282020 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 12037374320 ps |
| CPU time | 96.26 seconds |
| Started | Sep 09 03:06:03 PM UTC 24 |
| Finished | Sep 09 03:07:41 PM UTC 24 |
| Peak memory | 236080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955282020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1955282020 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.2759342543 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 28309670181 ps |
| CPU time | 618.66 seconds |
| Started | Sep 09 03:07:57 PM UTC 24 |
| Finished | Sep 09 03:18:24 PM UTC 24 |
| Peak memory | 351148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759342543 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2759342543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.1951289156 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 58904904 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 03:09:09 PM UTC 24 |
| Finished | Sep 09 03:09:11 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951289156 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1951289156 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_app.1160966311 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2155690647 ps |
| CPU time | 66.31 seconds |
| Started | Sep 09 03:08:26 PM UTC 24 |
| Finished | Sep 09 03:09:34 PM UTC 24 |
| Peak memory | 248296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160966311 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1160966311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.321309427 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 112411299368 ps |
| CPU time | 918.2 seconds |
| Started | Sep 09 03:08:22 PM UTC 24 |
| Finished | Sep 09 03:23:51 PM UTC 24 |
| Peak memory | 258572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321309427 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.321309427 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.1639244823 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 19110671459 ps |
| CPU time | 296.2 seconds |
| Started | Sep 09 03:08:44 PM UTC 24 |
| Finished | Sep 09 03:13:45 PM UTC 24 |
| Peak memory | 330284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639244823 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1639244823 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_error.1089120740 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 24569568087 ps |
| CPU time | 265.28 seconds |
| Started | Sep 09 03:08:47 PM UTC 24 |
| Finished | Sep 09 03:13:16 PM UTC 24 |
| Peak memory | 334444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089120740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1089120740 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.3444464274 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1343306037 ps |
| CPU time | 14.32 seconds |
| Started | Sep 09 03:08:48 PM UTC 24 |
| Finished | Sep 09 03:09:04 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444464274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3444464274 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.3322850973 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 43485432 ps |
| CPU time | 1.95 seconds |
| Started | Sep 09 03:09:04 PM UTC 24 |
| Finished | Sep 09 03:09:07 PM UTC 24 |
| Peak memory | 229600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322850973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3322850973 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.2734651935 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1115993192 ps |
| CPU time | 113.43 seconds |
| Started | Sep 09 03:08:19 PM UTC 24 |
| Finished | Sep 09 03:10:15 PM UTC 24 |
| Peak memory | 264692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734651935 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2734651935 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.235392943 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 9639805487 ps |
| CPU time | 18.07 seconds |
| Started | Sep 09 03:07:59 PM UTC 24 |
| Finished | Sep 09 03:08:18 PM UTC 24 |
| Peak memory | 236196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235392943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.235392943 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.1387486774 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 54609056452 ps |
| CPU time | 272 seconds |
| Started | Sep 09 03:09:08 PM UTC 24 |
| Finished | Sep 09 03:13:43 PM UTC 24 |
| Peak memory | 351144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387486774 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1387486774 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.2993213547 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 59649745 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 03:10:22 PM UTC 24 |
| Finished | Sep 09 03:10:24 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993213547 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2993213547 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_app.4042082637 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 20914856928 ps |
| CPU time | 360.4 seconds |
| Started | Sep 09 03:09:50 PM UTC 24 |
| Finished | Sep 09 03:15:55 PM UTC 24 |
| Peak memory | 416352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042082637 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4042082637 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.4241106767 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 119131399582 ps |
| CPU time | 1561.94 seconds |
| Started | Sep 09 03:09:38 PM UTC 24 |
| Finished | Sep 09 03:36:00 PM UTC 24 |
| Peak memory | 272996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241106767 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.4241106767 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1716581450 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 10713516558 ps |
| CPU time | 41.93 seconds |
| Started | Sep 09 03:10:04 PM UTC 24 |
| Finished | Sep 09 03:10:48 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716581450 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1716581450 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_error.1232200081 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 5572831934 ps |
| CPU time | 242.34 seconds |
| Started | Sep 09 03:10:04 PM UTC 24 |
| Finished | Sep 09 03:14:10 PM UTC 24 |
| Peak memory | 375404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232200081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1232200081 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.4186479512 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2828913379 ps |
| CPU time | 15.46 seconds |
| Started | Sep 09 03:10:16 PM UTC 24 |
| Finished | Sep 09 03:10:33 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186479512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.4186479512 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.2185266668 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 156123295 ps |
| CPU time | 2.83 seconds |
| Started | Sep 09 03:10:17 PM UTC 24 |
| Finished | Sep 09 03:10:21 PM UTC 24 |
| Peak memory | 234044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185266668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2185266668 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.18794098 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 269297232339 ps |
| CPU time | 1712.54 seconds |
| Started | Sep 09 03:09:26 PM UTC 24 |
| Finished | Sep 09 03:38:20 PM UTC 24 |
| Peak memory | 1731296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18794098 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.18794098 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.965896133 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5627948132 ps |
| CPU time | 327.1 seconds |
| Started | Sep 09 03:09:35 PM UTC 24 |
| Finished | Sep 09 03:15:07 PM UTC 24 |
| Peak memory | 360992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965896133 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.965896133 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.196760794 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 8897876513 ps |
| CPU time | 94.1 seconds |
| Started | Sep 09 03:09:12 PM UTC 24 |
| Finished | Sep 09 03:10:48 PM UTC 24 |
| Peak memory | 236048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196760794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.196760794 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.2182697006 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 42457244369 ps |
| CPU time | 2255.48 seconds |
| Started | Sep 09 03:10:18 PM UTC 24 |
| Finished | Sep 09 03:48:24 PM UTC 24 |
| Peak memory | 1049620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182697006 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2182697006 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.4286498998 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 25472611 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 03:10:51 PM UTC 24 |
| Finished | Sep 09 03:10:53 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286498998 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.4286498998 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_app.1557440045 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 9135852002 ps |
| CPU time | 154.28 seconds |
| Started | Sep 09 03:10:30 PM UTC 24 |
| Finished | Sep 09 03:13:07 PM UTC 24 |
| Peak memory | 287316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557440045 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1557440045 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.409767280 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 111867834584 ps |
| CPU time | 1494.55 seconds |
| Started | Sep 09 03:10:26 PM UTC 24 |
| Finished | Sep 09 03:35:40 PM UTC 24 |
| Peak memory | 268820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409767280 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.409767280 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.1712676424 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 11544686480 ps |
| CPU time | 348.07 seconds |
| Started | Sep 09 03:10:34 PM UTC 24 |
| Finished | Sep 09 03:16:27 PM UTC 24 |
| Peak memory | 340588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712676424 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1712676424 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_error.34206452 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 6948424596 ps |
| CPU time | 320.08 seconds |
| Started | Sep 09 03:10:46 PM UTC 24 |
| Finished | Sep 09 03:16:11 PM UTC 24 |
| Peak memory | 334592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34206452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.34206452 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.958878274 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1828133964 ps |
| CPU time | 7.72 seconds |
| Started | Sep 09 03:10:46 PM UTC 24 |
| Finished | Sep 09 03:10:55 PM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958878274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.958878274 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.2136949605 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1475041119 ps |
| CPU time | 31.14 seconds |
| Started | Sep 09 03:10:48 PM UTC 24 |
| Finished | Sep 09 03:11:21 PM UTC 24 |
| Peak memory | 254528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136949605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2136949605 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.2474715028 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 28480380690 ps |
| CPU time | 465.87 seconds |
| Started | Sep 09 03:10:23 PM UTC 24 |
| Finished | Sep 09 03:18:16 PM UTC 24 |
| Peak memory | 664080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474715028 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.2474715028 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.3861021124 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6647045808 ps |
| CPU time | 472.5 seconds |
| Started | Sep 09 03:10:25 PM UTC 24 |
| Finished | Sep 09 03:18:25 PM UTC 24 |
| Peak memory | 381464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861021124 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3861021124 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.2106141409 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1378928226 ps |
| CPU time | 21.48 seconds |
| Started | Sep 09 03:10:22 PM UTC 24 |
| Finished | Sep 09 03:10:45 PM UTC 24 |
| Peak memory | 235912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106141409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2106141409 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.2077438538 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 21762159480 ps |
| CPU time | 811.26 seconds |
| Started | Sep 09 03:10:50 PM UTC 24 |
| Finished | Sep 09 03:24:31 PM UTC 24 |
| Peak memory | 388016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077438538 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2077438538 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.4085349276 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 16986304 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 03:13:16 PM UTC 24 |
| Finished | Sep 09 03:13:19 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085349276 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.4085349276 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_app.3612615623 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2359845944 ps |
| CPU time | 105.72 seconds |
| Started | Sep 09 03:12:00 PM UTC 24 |
| Finished | Sep 09 03:13:48 PM UTC 24 |
| Peak memory | 266784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612615623 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3612615623 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.2074545589 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 87168179036 ps |
| CPU time | 1439.05 seconds |
| Started | Sep 09 03:11:21 PM UTC 24 |
| Finished | Sep 09 03:35:39 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074545589 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2074545589 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.610300469 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 131923779291 ps |
| CPU time | 152.98 seconds |
| Started | Sep 09 03:12:32 PM UTC 24 |
| Finished | Sep 09 03:15:08 PM UTC 24 |
| Peak memory | 348712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610300469 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.610300469 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_error.3861973890 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 8817723692 ps |
| CPU time | 258.58 seconds |
| Started | Sep 09 03:12:39 PM UTC 24 |
| Finished | Sep 09 03:17:02 PM UTC 24 |
| Peak memory | 444976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861973890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3861973890 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.1010118277 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4442960602 ps |
| CPU time | 9.68 seconds |
| Started | Sep 09 03:13:05 PM UTC 24 |
| Finished | Sep 09 03:13:16 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010118277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1010118277 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.179561061 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 47565804 ps |
| CPU time | 2.14 seconds |
| Started | Sep 09 03:13:08 PM UTC 24 |
| Finished | Sep 09 03:13:11 PM UTC 24 |
| Peak memory | 234048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179561061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.179561061 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3877856800 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1118585293859 ps |
| CPU time | 4794.51 seconds |
| Started | Sep 09 03:10:56 PM UTC 24 |
| Finished | Sep 09 04:31:49 PM UTC 24 |
| Peak memory | 3783276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877856800 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.3877856800 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.204882742 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 8335913701 ps |
| CPU time | 295.04 seconds |
| Started | Sep 09 03:10:58 PM UTC 24 |
| Finished | Sep 09 03:15:57 PM UTC 24 |
| Peak memory | 449056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204882742 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.204882742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.2390621198 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 10719383282 ps |
| CPU time | 95.26 seconds |
| Started | Sep 09 03:10:54 PM UTC 24 |
| Finished | Sep 09 03:12:31 PM UTC 24 |
| Peak memory | 236132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390621198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2390621198 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.1330838504 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 45893734005 ps |
| CPU time | 1331.44 seconds |
| Started | Sep 09 03:13:12 PM UTC 24 |
| Finished | Sep 09 03:35:39 PM UTC 24 |
| Peak memory | 1508272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330838504 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1330838504 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.2030980088 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 66630623 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 02:12:46 PM UTC 24 |
| Finished | Sep 09 02:12:48 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030980088 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2030980088 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_app.3655985168 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 8293871343 ps |
| CPU time | 257.84 seconds |
| Started | Sep 09 02:11:56 PM UTC 24 |
| Finished | Sep 09 02:16:18 PM UTC 24 |
| Peak memory | 363112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655985168 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3655985168 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.402711233 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 39527182517 ps |
| CPU time | 248.35 seconds |
| Started | Sep 09 02:12:07 PM UTC 24 |
| Finished | Sep 09 02:16:19 PM UTC 24 |
| Peak memory | 402024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402711233 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.402711233 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.59111882 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 7723495964 ps |
| CPU time | 189.95 seconds |
| Started | Sep 09 02:11:49 PM UTC 24 |
| Finished | Sep 09 02:15:02 PM UTC 24 |
| Peak memory | 240232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59111882 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.59111882 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.3479597859 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 147947563 ps |
| CPU time | 1.37 seconds |
| Started | Sep 09 02:12:31 PM UTC 24 |
| Finished | Sep 09 02:12:33 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479597859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3479597859 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.2822104414 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 33752964 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 02:12:34 PM UTC 24 |
| Finished | Sep 09 02:12:36 PM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822104414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2822104414 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.4249748223 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1666774439 ps |
| CPU time | 25.79 seconds |
| Started | Sep 09 02:12:37 PM UTC 24 |
| Finished | Sep 09 02:13:04 PM UTC 24 |
| Peak memory | 232096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249748223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.4249748223 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.1788509872 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 39049473784 ps |
| CPU time | 368.74 seconds |
| Started | Sep 09 02:12:11 PM UTC 24 |
| Finished | Sep 09 02:18:25 PM UTC 24 |
| Peak memory | 502312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788509872 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1788509872 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_error.1699769695 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 18390552287 ps |
| CPU time | 407.61 seconds |
| Started | Sep 09 02:12:20 PM UTC 24 |
| Finished | Sep 09 02:19:13 PM UTC 24 |
| Peak memory | 367216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699769695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1699769695 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.1922315043 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3248359933 ps |
| CPU time | 11.52 seconds |
| Started | Sep 09 02:12:26 PM UTC 24 |
| Finished | Sep 09 02:12:38 PM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922315043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1922315043 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.1577761929 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1216401139 ps |
| CPU time | 20.7 seconds |
| Started | Sep 09 02:12:39 PM UTC 24 |
| Finished | Sep 09 02:13:01 PM UTC 24 |
| Peak memory | 248408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577761929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1577761929 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.3204867852 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 98927608647 ps |
| CPU time | 3473.07 seconds |
| Started | Sep 09 02:11:08 PM UTC 24 |
| Finished | Sep 09 03:09:37 PM UTC 24 |
| Peak memory | 3908280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204867852 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.3204867852 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.143089442 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 13483141634 ps |
| CPU time | 468.94 seconds |
| Started | Sep 09 02:12:19 PM UTC 24 |
| Finished | Sep 09 02:20:15 PM UTC 24 |
| Peak memory | 547764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143089442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.143089442 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.3163717203 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5531299612 ps |
| CPU time | 202.54 seconds |
| Started | Sep 09 02:11:10 PM UTC 24 |
| Finished | Sep 09 02:14:36 PM UTC 24 |
| Peak memory | 299644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163717203 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3163717203 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.3692171245 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4188106142 ps |
| CPU time | 77.16 seconds |
| Started | Sep 09 02:11:06 PM UTC 24 |
| Finished | Sep 09 02:12:25 PM UTC 24 |
| Peak memory | 234300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692171245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3692171245 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.4293817499 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 79695345984 ps |
| CPU time | 530.93 seconds |
| Started | Sep 09 02:12:39 PM UTC 24 |
| Finished | Sep 09 02:21:37 PM UTC 24 |
| Peak memory | 365176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293817499 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.4293817499 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.1291569576 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 66428752 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 02:15:23 PM UTC 24 |
| Finished | Sep 09 02:15:25 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291569576 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1291569576 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_app.4234559913 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 40698806542 ps |
| CPU time | 237.68 seconds |
| Started | Sep 09 02:13:46 PM UTC 24 |
| Finished | Sep 09 02:17:47 PM UTC 24 |
| Peak memory | 420492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234559913 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4234559913 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.2820706041 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 9474750599 ps |
| CPU time | 331.44 seconds |
| Started | Sep 09 02:14:00 PM UTC 24 |
| Finished | Sep 09 02:19:36 PM UTC 24 |
| Peak memory | 311904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820706041 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2820706041 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.2109865669 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 7526126974 ps |
| CPU time | 365.83 seconds |
| Started | Sep 09 02:13:44 PM UTC 24 |
| Finished | Sep 09 02:19:55 PM UTC 24 |
| Peak memory | 242200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109865669 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2109865669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.1833593304 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 47571010 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 02:14:47 PM UTC 24 |
| Finished | Sep 09 02:14:50 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833593304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1833593304 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.2764031742 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 15169040 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 02:14:50 PM UTC 24 |
| Finished | Sep 09 02:14:53 PM UTC 24 |
| Peak memory | 224744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764031742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2764031742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.1949578118 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 149663774 ps |
| CPU time | 5.14 seconds |
| Started | Sep 09 02:14:53 PM UTC 24 |
| Finished | Sep 09 02:15:00 PM UTC 24 |
| Peak memory | 234524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949578118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1949578118 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3001627543 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5669920365 ps |
| CPU time | 37.15 seconds |
| Started | Sep 09 02:14:08 PM UTC 24 |
| Finished | Sep 09 02:14:46 PM UTC 24 |
| Peak memory | 256528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001627543 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3001627543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_error.3392137399 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 68703199217 ps |
| CPU time | 465.39 seconds |
| Started | Sep 09 02:14:23 PM UTC 24 |
| Finished | Sep 09 02:22:14 PM UTC 24 |
| Peak memory | 602772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392137399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3392137399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.1338138572 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 11212938589 ps |
| CPU time | 24.02 seconds |
| Started | Sep 09 02:14:37 PM UTC 24 |
| Finished | Sep 09 02:15:03 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338138572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1338138572 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.2553727299 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3007644345 ps |
| CPU time | 19.77 seconds |
| Started | Sep 09 02:15:01 PM UTC 24 |
| Finished | Sep 09 02:15:22 PM UTC 24 |
| Peak memory | 266848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553727299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2553727299 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.1253673630 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 45944296169 ps |
| CPU time | 1821.79 seconds |
| Started | Sep 09 02:13:02 PM UTC 24 |
| Finished | Sep 09 02:43:45 PM UTC 24 |
| Peak memory | 2327072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253673630 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.1253673630 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.3187847097 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1873167874 ps |
| CPU time | 84.66 seconds |
| Started | Sep 09 02:14:21 PM UTC 24 |
| Finished | Sep 09 02:15:48 PM UTC 24 |
| Peak memory | 279284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187847097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3187847097 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.390183419 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 45753285904 ps |
| CPU time | 420.41 seconds |
| Started | Sep 09 02:13:05 PM UTC 24 |
| Finished | Sep 09 02:20:11 PM UTC 24 |
| Peak memory | 385568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390183419 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.390183419 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.3683962145 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5236886406 ps |
| CPU time | 76.3 seconds |
| Started | Sep 09 02:12:49 PM UTC 24 |
| Finished | Sep 09 02:14:07 PM UTC 24 |
| Peak memory | 234296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683962145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3683962145 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.2639538384 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1596242448 ps |
| CPU time | 150.32 seconds |
| Started | Sep 09 02:15:03 PM UTC 24 |
| Finished | Sep 09 02:17:36 PM UTC 24 |
| Peak memory | 283384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639538384 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2639538384 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.848646792 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2276427612 ps |
| CPU time | 66.4 seconds |
| Started | Sep 09 02:15:04 PM UTC 24 |
| Finished | Sep 09 02:16:12 PM UTC 24 |
| Peak memory | 275056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=848646792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_ra nd_reset.848646792 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.326467365 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 63185367 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 02:18:09 PM UTC 24 |
| Finished | Sep 09 02:18:11 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326467365 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.326467365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_app.3189371190 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 17538324612 ps |
| CPU time | 243.87 seconds |
| Started | Sep 09 02:16:12 PM UTC 24 |
| Finished | Sep 09 02:20:20 PM UTC 24 |
| Peak memory | 309868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189371190 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3189371190 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2035325038 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 99714814945 ps |
| CPU time | 324.46 seconds |
| Started | Sep 09 02:16:17 PM UTC 24 |
| Finished | Sep 09 02:21:47 PM UTC 24 |
| Peak memory | 408168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035325038 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2035325038 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.1154691677 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 8506931793 ps |
| CPU time | 532.72 seconds |
| Started | Sep 09 02:16:03 PM UTC 24 |
| Finished | Sep 09 02:25:03 PM UTC 24 |
| Peak memory | 246376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154691677 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1154691677 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2493818010 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 553762323 ps |
| CPU time | 19.29 seconds |
| Started | Sep 09 02:17:28 PM UTC 24 |
| Finished | Sep 09 02:17:49 PM UTC 24 |
| Peak memory | 235812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493818010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2493818010 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.3092476604 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 31928553 ps |
| CPU time | 1.61 seconds |
| Started | Sep 09 02:17:37 PM UTC 24 |
| Finished | Sep 09 02:17:40 PM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092476604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3092476604 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.184226889 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4897485985 ps |
| CPU time | 70.15 seconds |
| Started | Sep 09 02:17:40 PM UTC 24 |
| Finished | Sep 09 02:18:52 PM UTC 24 |
| Peak memory | 236196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184226889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.184226889 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3059875132 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3109136908 ps |
| CPU time | 138.12 seconds |
| Started | Sep 09 02:16:20 PM UTC 24 |
| Finished | Sep 09 02:18:40 PM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059875132 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3059875132 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_error.653574491 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2199212275 ps |
| CPU time | 74.34 seconds |
| Started | Sep 09 02:16:52 PM UTC 24 |
| Finished | Sep 09 02:18:08 PM UTC 24 |
| Peak memory | 285292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653574491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.653574491 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.1721492885 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 689068026 ps |
| CPU time | 5.4 seconds |
| Started | Sep 09 02:17:21 PM UTC 24 |
| Finished | Sep 09 02:17:28 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721492885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1721492885 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.515452840 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 90458832 ps |
| CPU time | 4.12 seconds |
| Started | Sep 09 02:17:47 PM UTC 24 |
| Finished | Sep 09 02:17:52 PM UTC 24 |
| Peak memory | 232056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515452840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.515452840 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.3786012502 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 96208805856 ps |
| CPU time | 797.08 seconds |
| Started | Sep 09 02:15:28 PM UTC 24 |
| Finished | Sep 09 02:28:55 PM UTC 24 |
| Peak memory | 1063464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786012502 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.3786012502 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.2018128088 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 11116765686 ps |
| CPU time | 259.65 seconds |
| Started | Sep 09 02:16:21 PM UTC 24 |
| Finished | Sep 09 02:20:44 PM UTC 24 |
| Peak memory | 332720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018128088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2018128088 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.304290171 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 9955014037 ps |
| CPU time | 225.27 seconds |
| Started | Sep 09 02:15:49 PM UTC 24 |
| Finished | Sep 09 02:19:38 PM UTC 24 |
| Peak memory | 295464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304290171 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.304290171 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.1658863382 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4476715720 ps |
| CPU time | 35.16 seconds |
| Started | Sep 09 02:15:26 PM UTC 24 |
| Finished | Sep 09 02:16:02 PM UTC 24 |
| Peak memory | 236080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658863382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1658863382 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.3435180740 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 33159184233 ps |
| CPU time | 1144.01 seconds |
| Started | Sep 09 02:17:49 PM UTC 24 |
| Finished | Sep 09 02:37:06 PM UTC 24 |
| Peak memory | 447508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435180740 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3435180740 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.3048509642 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 44354153 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 02:20:16 PM UTC 24 |
| Finished | Sep 09 02:20:18 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048509642 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3048509642 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_app.823089724 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5816183613 ps |
| CPU time | 219.81 seconds |
| Started | Sep 09 02:18:53 PM UTC 24 |
| Finished | Sep 09 02:22:37 PM UTC 24 |
| Peak memory | 350820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823089724 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.823089724 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.662098530 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3088967442 ps |
| CPU time | 80.46 seconds |
| Started | Sep 09 02:19:11 PM UTC 24 |
| Finished | Sep 09 02:20:34 PM UTC 24 |
| Peak memory | 279136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662098530 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.662098530 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.2869764463 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 17607536480 ps |
| CPU time | 230.36 seconds |
| Started | Sep 09 02:18:41 PM UTC 24 |
| Finished | Sep 09 02:22:36 PM UTC 24 |
| Peak memory | 240172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869764463 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2869764463 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.3844191035 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2447077323 ps |
| CPU time | 35.63 seconds |
| Started | Sep 09 02:19:54 PM UTC 24 |
| Finished | Sep 09 02:20:31 PM UTC 24 |
| Peak memory | 235936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844191035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3844191035 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.18298672 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 77153516 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 02:19:56 PM UTC 24 |
| Finished | Sep 09 02:19:58 PM UTC 24 |
| Peak memory | 227900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18298672 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.18298672 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.4042115234 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2026783543 ps |
| CPU time | 35.74 seconds |
| Started | Sep 09 02:20:00 PM UTC 24 |
| Finished | Sep 09 02:20:37 PM UTC 24 |
| Peak memory | 232088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042115234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.4042115234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.3821704257 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1164965423 ps |
| CPU time | 37.57 seconds |
| Started | Sep 09 02:19:14 PM UTC 24 |
| Finished | Sep 09 02:19:53 PM UTC 24 |
| Peak memory | 252332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821704257 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3821704257 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_error.2883969747 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 244413018 ps |
| CPU time | 9.54 seconds |
| Started | Sep 09 02:19:40 PM UTC 24 |
| Finished | Sep 09 02:19:50 PM UTC 24 |
| Peak memory | 246192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883969747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2883969747 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.1305266211 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4850278041 ps |
| CPU time | 19.21 seconds |
| Started | Sep 09 02:19:51 PM UTC 24 |
| Finished | Sep 09 02:20:11 PM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305266211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1305266211 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.1541284512 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 622435755328 ps |
| CPU time | 1116.93 seconds |
| Started | Sep 09 02:18:24 PM UTC 24 |
| Finished | Sep 09 02:37:14 PM UTC 24 |
| Peak memory | 1557016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541284512 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.1541284512 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.747340866 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3853276399 ps |
| CPU time | 188.72 seconds |
| Started | Sep 09 02:19:37 PM UTC 24 |
| Finished | Sep 09 02:22:49 PM UTC 24 |
| Peak memory | 287664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747340866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.747340866 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2649314630 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 20813388166 ps |
| CPU time | 346.44 seconds |
| Started | Sep 09 02:18:26 PM UTC 24 |
| Finished | Sep 09 02:24:17 PM UTC 24 |
| Peak memory | 510568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649314630 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2649314630 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.2253202041 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1280232633 ps |
| CPU time | 56.74 seconds |
| Started | Sep 09 02:18:12 PM UTC 24 |
| Finished | Sep 09 02:19:10 PM UTC 24 |
| Peak memory | 235928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253202041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2253202041 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.3750444333 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 16423847823 ps |
| CPU time | 1295.39 seconds |
| Started | Sep 09 02:20:11 PM UTC 24 |
| Finished | Sep 09 02:42:02 PM UTC 24 |
| Peak memory | 578464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750444333 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3750444333 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.3389527119 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3392710315 ps |
| CPU time | 71.39 seconds |
| Started | Sep 09 02:20:12 PM UTC 24 |
| Finished | Sep 09 02:21:26 PM UTC 24 |
| Peak memory | 265216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3389527119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_r and_reset.3389527119 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.3049556892 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 26069423 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 02:21:30 PM UTC 24 |
| Finished | Sep 09 02:21:32 PM UTC 24 |
| Peak memory | 227012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049556892 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3049556892 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_app.918167102 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2655094105 ps |
| CPU time | 52.24 seconds |
| Started | Sep 09 02:20:35 PM UTC 24 |
| Finished | Sep 09 02:21:29 PM UTC 24 |
| Peak memory | 242212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918167102 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.918167102 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.1860885013 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 39833090613 ps |
| CPU time | 249.54 seconds |
| Started | Sep 09 02:20:35 PM UTC 24 |
| Finished | Sep 09 02:24:48 PM UTC 24 |
| Peak memory | 408184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860885013 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1860885013 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.3938683943 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1872318617 ps |
| CPU time | 90.16 seconds |
| Started | Sep 09 02:20:32 PM UTC 24 |
| Finished | Sep 09 02:22:04 PM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938683943 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3938683943 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.2621408968 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 100015282 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 02:21:01 PM UTC 24 |
| Finished | Sep 09 02:21:03 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621408968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2621408968 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.1906311053 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 37527359 ps |
| CPU time | 1.7 seconds |
| Started | Sep 09 02:21:04 PM UTC 24 |
| Finished | Sep 09 02:21:07 PM UTC 24 |
| Peak memory | 227904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906311053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1906311053 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.691135585 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1794562954 ps |
| CPU time | 40.69 seconds |
| Started | Sep 09 02:21:05 PM UTC 24 |
| Finished | Sep 09 02:21:47 PM UTC 24 |
| Peak memory | 232052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691135585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.691135585 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.1836654090 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 65176282091 ps |
| CPU time | 555.64 seconds |
| Started | Sep 09 02:20:38 PM UTC 24 |
| Finished | Sep 09 02:30:02 PM UTC 24 |
| Peak memory | 535208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836654090 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1836654090 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_error.1936408146 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5783464848 ps |
| CPU time | 44.63 seconds |
| Started | Sep 09 02:20:45 PM UTC 24 |
| Finished | Sep 09 02:21:31 PM UTC 24 |
| Peak memory | 268900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936408146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1936408146 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.640630086 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4452701584 ps |
| CPU time | 13.85 seconds |
| Started | Sep 09 02:20:45 PM UTC 24 |
| Finished | Sep 09 02:21:00 PM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640630086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.640630086 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.1503138332 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 126163069 ps |
| CPU time | 2.13 seconds |
| Started | Sep 09 02:21:07 PM UTC 24 |
| Finished | Sep 09 02:21:11 PM UTC 24 |
| Peak memory | 234044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503138332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1503138332 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.1096658419 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 43895142865 ps |
| CPU time | 1893.07 seconds |
| Started | Sep 09 02:20:21 PM UTC 24 |
| Finished | Sep 09 02:52:17 PM UTC 24 |
| Peak memory | 2302500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096658419 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.1096658419 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.2122315718 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 13641517067 ps |
| CPU time | 266.73 seconds |
| Started | Sep 09 02:20:40 PM UTC 24 |
| Finished | Sep 09 02:25:11 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122315718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2122315718 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.1745314112 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5226512369 ps |
| CPU time | 501.73 seconds |
| Started | Sep 09 02:20:26 PM UTC 24 |
| Finished | Sep 09 02:28:55 PM UTC 24 |
| Peak memory | 381536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745314112 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1745314112 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.4163669490 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 161750210 ps |
| CPU time | 5.03 seconds |
| Started | Sep 09 02:20:19 PM UTC 24 |
| Finished | Sep 09 02:20:25 PM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163669490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.4163669490 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.3666357311 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 54549230722 ps |
| CPU time | 1289.24 seconds |
| Started | Sep 09 02:21:11 PM UTC 24 |
| Finished | Sep 09 02:42:55 PM UTC 24 |
| Peak memory | 645992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666357311 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3666357311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/9.kmac_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |