Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15952657	1			T9	16		T11	68		T12	86
all_values[1]	15952657	1			T9	16		T11	68		T12	86
all_values[2]	15952657	1			T9	16		T11	68		T12	86

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

547692

1

T9

16

T11

80

T12

28

auto[1]

47310279

1

T9

32

T11

124

T12

230

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47628576

1

T9

48

T11

189

T12

243

auto[1]

229395

1

T11

15

T12

15

T17

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	179487	1			T12	10		T24	271		T48	4
all_values[0]	auto[0]	auto[1]	1343	1			T12	4		T48	2		T25	4
all_values[0]	auto[1]	auto[0]	15696705	1			T9	16		T11	63		T12	71
all_values[0]	auto[1]	auto[1]	75122	1			T11	5		T12	1		T17	3
all_values[1]	auto[0]	auto[0]	190661	1			T9	16		T11	63		T24	231
all_values[1]	auto[0]	auto[1]	1037	1			T11	5		T57	1		T87	1
all_values[1]	auto[1]	auto[0]	15685531	1			T12	81		T17	82		T24	275
all_values[1]	auto[1]	auto[1]	75428	1			T12	5		T17	3		T48	5
all_values[2]	auto[0]	auto[0]	174152	1			T11	9		T12	10		T17	8
all_values[2]	auto[0]	auto[1]	1012	1			T11	3		T12	4		T17	1
all_values[2]	auto[1]	auto[0]	15702040	1			T9	16		T11	54		T12	71
all_values[2]	auto[1]	auto[1]	75453	1			T11	2		T12	1		T17	2