Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 0 3 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 0 18 100.00 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56002 1 T9 2 T11 6 T12 2
auto[1] 59788 1 T12 4 T24 6 T48 4



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 28903 1 T17 2 T24 3 T48 2
lower_val 28400 1 T9 1 T11 2 T12 4
zero_val 934 1 T9 1 T11 1 T12 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for wait_timer_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 42874 1 T9 2 T11 2 T12 2
lower_val 42790 1 T11 4 T12 2 T17 4
zero_val 30126 1 T12 2 T24 6 T48 2



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for entropy_timer_cross

Bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 6989 1 T17 1 T48 1 T33 28
higher_val higher_val auto[1] 3764 1 T24 1 T57 23 T62 9
higher_val lower_val auto[0] 6880 1 T17 1 T33 32 T47 9
higher_val lower_val auto[1] 3873 1 T57 21 T62 16 T26 4
higher_val zero_val auto[0] 61 1 T24 1 T46 1 T52 1
higher_val zero_val auto[1] 7336 1 T24 1 T48 1 T57 34
lower_val higher_val auto[0] 6857 1 T9 1 T11 1 T17 1
lower_val higher_val auto[1] 3720 1 T12 2 T24 1 T57 25
lower_val lower_val auto[0] 6864 1 T11 1 T12 1 T17 1
lower_val lower_val auto[1] 3635 1 T57 19 T62 21 T26 2
lower_val zero_val auto[0] 59 1 T24 1 T26 1 T63 1
lower_val zero_val auto[1] 7265 1 T12 1 T57 32 T62 26
zero_val higher_val auto[0] 274 1 T9 1 T48 1 T25 1
zero_val higher_val auto[1] 71 1 T24 2 T52 3 T193 1
zero_val lower_val auto[0] 274 1 T11 1 T12 1 T17 1
zero_val lower_val auto[1] 78 1 T52 2 T53 3 T194 1
zero_val zero_val auto[0] 157 1 T24 2 T26 1 T5 1
zero_val zero_val auto[1] 80 1 T24 1 T57 2 T5 2

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