Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15952657	1			T9	16		T11	68		T12	86
all_pins[1]	15952657	1			T9	16		T11	68		T12	86
all_pins[2]	15952657	1			T9	16		T11	68		T12	86

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47453545	1			T9	48		T11	199		T12	257
values[0x1]	404426	1			T11	5		T12	1		T17	4
transitions[0x0=>0x1]	402305	1			T11	5		T12	1		T17	4
transitions[0x1=>0x0]	402326	1			T11	5		T12	1		T17	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15877535	1			T9	16		T11	63		T12	85
all_pins[0]	values[0x1]	75122	1			T11	5		T12	1		T17	3
all_pins[0]	transitions[0x0=>0x1]	75109	1			T11	5		T12	1		T17	3
all_pins[0]	transitions[0x1=>0x0]	4719	1			T17	1		T25	2		T16	15
all_pins[1]	values[0x0]	15947925	1			T9	16		T11	68		T12	86
all_pins[1]	values[0x1]	4732	1			T17	1		T25	2		T16	15
all_pins[1]	transitions[0x0=>0x1]	4599	1			T17	1		T25	2		T16	15
all_pins[1]	transitions[0x1=>0x0]	324439	1			T34	8573		T28	131		T35	8679
all_pins[2]	values[0x0]	15628085	1			T9	16		T11	68		T12	86
all_pins[2]	values[0x1]	324572	1			T34	8573		T28	131		T35	8679
all_pins[2]	transitions[0x0=>0x1]	322597	1			T34	8511		T28	131		T35	8618
all_pins[2]	transitions[0x1=>0x0]	73168	1			T11	5		T12	1		T17	3