Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6480042 |
1 |
|
|
T11 |
24 |
|
T12 |
24 |
|
T17 |
24 |
auto[1] |
6480008 |
1 |
|
|
T11 |
24 |
|
T12 |
24 |
|
T17 |
24 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
12891096 |
1 |
|
|
T11 |
48 |
|
T12 |
48 |
|
T17 |
48 |
triple_byte_access |
23382 |
1 |
|
|
T33 |
52 |
|
T10 |
4 |
|
T58 |
56 |
halfword_access |
22982 |
1 |
|
|
T25 |
4 |
|
T33 |
72 |
|
T10 |
6 |
byte_access |
22590 |
1 |
|
|
T33 |
56 |
|
T10 |
4 |
|
T58 |
64 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6445565 |
1 |
|
|
T11 |
24 |
|
T12 |
24 |
|
T17 |
24 |
auto[0] |
triple_byte_access |
11691 |
1 |
|
|
T33 |
26 |
|
T10 |
2 |
|
T58 |
28 |
auto[0] |
halfword_access |
11491 |
1 |
|
|
T25 |
2 |
|
T33 |
36 |
|
T10 |
3 |
auto[0] |
byte_access |
11295 |
1 |
|
|
T33 |
28 |
|
T10 |
2 |
|
T58 |
32 |
auto[1] |
word_access |
6445531 |
1 |
|
|
T11 |
24 |
|
T12 |
24 |
|
T17 |
24 |
auto[1] |
triple_byte_access |
11691 |
1 |
|
|
T33 |
26 |
|
T10 |
2 |
|
T58 |
28 |
auto[1] |
halfword_access |
11491 |
1 |
|
|
T25 |
2 |
|
T33 |
36 |
|
T10 |
3 |
auto[1] |
byte_access |
11295 |
1 |
|
|
T33 |
28 |
|
T10 |
2 |
|
T58 |
32 |