| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.23 | 97.91 | 92.65 | 99.89 | 76.76 | 95.59 | 99.05 | 97.73 |
| T761 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3235952593 | Sep 11 08:39:25 AM UTC 24 | Sep 11 08:39:27 AM UTC 24 | 24507250 ps | ||
| T762 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.4974458 | Sep 11 08:39:25 AM UTC 24 | Sep 11 08:39:27 AM UTC 24 | 46643431 ps | ||
| T763 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1213894360 | Sep 11 08:39:24 AM UTC 24 | Sep 11 08:39:27 AM UTC 24 | 387878602 ps | ||
| T764 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2508435472 | Sep 11 08:39:24 AM UTC 24 | Sep 11 08:39:27 AM UTC 24 | 228096231 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4004492003 | Sep 11 08:39:25 AM UTC 24 | Sep 11 08:39:28 AM UTC 24 | 871492301 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1204521941 | Sep 11 08:39:23 AM UTC 24 | Sep 11 08:39:29 AM UTC 24 | 353515311 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.251952072 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:46 AM UTC 24 | 137519848 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.3094006081 | Sep 11 08:39:23 AM UTC 24 | Sep 11 08:39:29 AM UTC 24 | 1021884752 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.2147998206 | Sep 11 08:39:21 AM UTC 24 | Sep 11 08:39:29 AM UTC 24 | 143232731 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.1124476504 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:29 AM UTC 24 | 28455660 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3771214305 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:29 AM UTC 24 | 13037604 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.4173978787 | Sep 11 08:39:24 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 219328387 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1806981056 | Sep 11 08:39:27 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 61634165 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.456701090 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 27369390 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2989653511 | Sep 11 08:39:27 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 312577224 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.748946838 | Sep 11 08:39:27 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 29733744 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.267339734 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 25396308 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.886935720 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 23466232 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2613293604 | Sep 11 08:39:27 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 224843001 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4176764942 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 28842501 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.925922753 | Sep 11 08:39:27 AM UTC 24 | Sep 11 08:39:30 AM UTC 24 | 64672908 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1258887883 | Sep 11 08:39:25 AM UTC 24 | Sep 11 08:39:31 AM UTC 24 | 889447792 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.968356924 | Sep 11 08:39:27 AM UTC 24 | Sep 11 08:39:31 AM UTC 24 | 103367814 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.4142229041 | Sep 11 08:39:23 AM UTC 24 | Sep 11 08:39:32 AM UTC 24 | 286918875 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2332312573 | Sep 11 08:39:23 AM UTC 24 | Sep 11 08:39:32 AM UTC 24 | 559978193 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.64397592 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:32 AM UTC 24 | 152741925 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2263663471 | Sep 11 08:39:04 AM UTC 24 | Sep 11 08:39:32 AM UTC 24 | 5343790121 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3290218368 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:34 AM UTC 24 | 46350266 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1906880487 | Sep 11 08:39:33 AM UTC 24 | Sep 11 08:39:35 AM UTC 24 | 59980388 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1408753477 | Sep 11 08:39:33 AM UTC 24 | Sep 11 08:39:36 AM UTC 24 | 19628093 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3906797660 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:36 AM UTC 24 | 23836166 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2617485538 | Sep 11 08:39:34 AM UTC 24 | Sep 11 08:39:36 AM UTC 24 | 107056392 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3468973997 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:36 AM UTC 24 | 54535527 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2639992053 | Sep 11 08:39:33 AM UTC 24 | Sep 11 08:39:36 AM UTC 24 | 236631088 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2192204427 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:36 AM UTC 24 | 31271130 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.48882309 | Sep 11 08:39:33 AM UTC 24 | Sep 11 08:39:37 AM UTC 24 | 38125936 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1356913552 | Sep 11 08:39:34 AM UTC 24 | Sep 11 08:39:37 AM UTC 24 | 82968234 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3386647795 | Sep 11 08:39:33 AM UTC 24 | Sep 11 08:39:37 AM UTC 24 | 171255937 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.4249664237 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:37 AM UTC 24 | 498460119 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.1458410725 | Sep 11 08:39:23 AM UTC 24 | Sep 11 08:39:38 AM UTC 24 | 2567499386 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4265376822 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:38 AM UTC 24 | 57869131 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3244151856 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:39 AM UTC 24 | 15446906 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1363857184 | Sep 11 08:39:33 AM UTC 24 | Sep 11 08:39:39 AM UTC 24 | 397623551 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1325060462 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:39 AM UTC 24 | 15054076 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.312280636 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:39 AM UTC 24 | 26465301 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.4093829972 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:39 AM UTC 24 | 63876857 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.391749356 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:39 AM UTC 24 | 14132365 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1627389749 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:39 AM UTC 24 | 155972885 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3933489083 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 384170984 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3164487972 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:46 AM UTC 24 | 115371661 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1887155503 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 12473006 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.704582678 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 19415869 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1081292156 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 59920165 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.836598851 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 209529298 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3222890006 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 45486656 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2049172172 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 156716231 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3679055520 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 15246470 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1612169678 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 200205026 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3086561040 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 143065240 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.97749539 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:40 AM UTC 24 | 166168208 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3199529105 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:41 AM UTC 24 | 181270842 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2441801780 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:41 AM UTC 24 | 258312164 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.474381559 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:41 AM UTC 24 | 278608280 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1961394915 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:42 AM UTC 24 | 148361475 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1226316957 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:43 AM UTC 24 | 867976988 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.386066210 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:43 AM UTC 24 | 255686132 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1074815104 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 102394375 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.4117321208 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 33189132 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2007433344 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 15798439 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3741945587 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 17123332 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.278448553 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 15579951 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2070102163 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 23175775 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3798470742 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:46 AM UTC 24 | 37319210 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3394860846 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 20017837 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1761327124 | Sep 11 08:39:43 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 47763975 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.231504985 | Sep 11 08:39:42 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 55484949 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.853284660 | Sep 11 08:39:43 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 19442284 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3143005532 | Sep 11 08:39:43 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 17259524 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1014317347 | Sep 11 08:39:43 AM UTC 24 | Sep 11 08:39:44 AM UTC 24 | 50957078 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.95410536 | Sep 11 08:39:43 AM UTC 24 | Sep 11 08:39:45 AM UTC 24 | 16112985 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.645331483 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:45 AM UTC 24 | 21468888 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.887045393 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:45 AM UTC 24 | 13815674 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.864218839 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:45 AM UTC 24 | 67431439 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2356552059 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:45 AM UTC 24 | 13214185 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.54250951 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:45 AM UTC 24 | 32755085 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1258872984 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:45 AM UTC 24 | 45764339 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2768665701 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:46 AM UTC 24 | 45372588 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4177485217 | Sep 11 08:39:36 AM UTC 24 | Sep 11 08:39:46 AM UTC 24 | 50575964 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2927170823 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:46 AM UTC 24 | 37288761 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3599288734 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:46 AM UTC 24 | 53730705 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3643904033 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 65644800 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2367498085 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 36369685 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3161766015 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 14249989 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1279033066 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 184220451 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.454864405 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 16047823 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.967798168 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 15813010 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2662537932 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 171438233 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.868559166 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 49367594 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.2657979377 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 14425947 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1772466439 | Sep 11 08:39:31 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 437549240 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1510549606 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 48031571 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.147451894 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 18539063 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.3010717939 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 116461662 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1000112153 | Sep 11 08:39:45 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 11849514 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1416465584 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 18283836 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.682765903 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 411913137 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1339715677 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 410432573 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1923893015 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 251664189 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2355825004 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 25222805 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1068207137 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:47 AM UTC 24 | 16693792 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.857854399 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 83990984 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3963033422 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 44572719 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3623010830 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 13928047 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2780666985 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 77695068 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1201199770 | Sep 11 08:39:40 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 1029159307 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.125682691 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 205809733 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3877728413 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 50682909 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1431868868 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 118439844 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4248189087 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 731914894 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.4036501799 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 67562058 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3613582597 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 89585849 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2227016431 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:48 AM UTC 24 | 94193954 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1755478354 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 97487575 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3219988558 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 111932660 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1405180729 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 175914055 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2165991542 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 37516364 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3220098967 | Sep 11 08:39:47 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 52551472 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.873178716 | Sep 11 08:39:47 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 42688095 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1822826147 | Sep 11 08:39:47 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 24299478 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2531306644 | Sep 11 08:39:47 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 15556325 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.4057269698 | Sep 11 08:39:47 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 13400692 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3566453043 | Sep 11 08:39:38 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 513863476 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3840881608 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:49 AM UTC 24 | 1048304933 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2833041958 | Sep 11 08:39:28 AM UTC 24 | Sep 11 08:39:51 AM UTC 24 | 429693888 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.4121591189 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 352448318 ps |
| CPU time | 10.01 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:32:01 AM UTC 24 |
| Peak memory | 244408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4121591189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_r and_reset.4121591189 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.1865847063 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4106588218 ps |
| CPU time | 86.72 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:33:18 AM UTC 24 |
| Peak memory | 297500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865847063 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1865847063 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.3808143903 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11033760720 ps |
| CPU time | 45.81 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:32:13 AM UTC 24 |
| Peak memory | 236124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808143903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3808143903 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.69565347 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 538438970 ps |
| CPU time | 2.62 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:28 AM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69565347 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.69565347 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.3602805468 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3683695320 ps |
| CPU time | 44.88 seconds |
| Started | Sep 11 10:32:16 AM UTC 24 |
| Finished | Sep 11 10:33:02 AM UTC 24 |
| Peak memory | 278280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602805468 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3602805468 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.4177390334 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3728681544 ps |
| CPU time | 57.4 seconds |
| Started | Sep 11 10:32:13 AM UTC 24 |
| Finished | Sep 11 10:33:12 AM UTC 24 |
| Peak memory | 234268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177390334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.4177390334 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.3680014403 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29738154 ps |
| CPU time | 2.03 seconds |
| Started | Sep 11 10:33:37 AM UTC 24 |
| Finished | Sep 11 10:33:40 AM UTC 24 |
| Peak memory | 234080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680014403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3680014403 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.545756293 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4471223262 ps |
| CPU time | 8.75 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:31:59 AM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545756293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.545756293 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_error.1765413389 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6913500511 ps |
| CPU time | 200.81 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:35:13 AM UTC 24 |
| Peak memory | 385624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765413389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1765413389 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.2265605567 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 110348920766 ps |
| CPU time | 682.38 seconds |
| Started | Sep 11 10:36:04 AM UTC 24 |
| Finished | Sep 11 10:47:35 AM UTC 24 |
| Peak memory | 400240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265605567 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2265605567 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.120312277 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 64670628 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 10:54:15 AM UTC 24 |
| Finished | Sep 11 10:54:18 AM UTC 24 |
| Peak memory | 232116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120312277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.120312277 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3152572164 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 353034507 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152572164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.3152572164 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.2627170967 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15723632 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:31:51 AM UTC 24 |
| Peak memory | 227148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627170967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2627170967 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.3544219015 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2491086036 ps |
| CPU time | 47.51 seconds |
| Started | Sep 11 10:33:40 AM UTC 24 |
| Finished | Sep 11 10:34:29 AM UTC 24 |
| Peak memory | 252152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3544219015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_r and_reset.3544219015 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1022679809 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 11849781 ps |
| CPU time | 0.77 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022679809 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1022679809 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.1246277173 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 371050714 ps |
| CPU time | 13.01 seconds |
| Started | Sep 11 10:35:59 AM UTC 24 |
| Finished | Sep 11 10:36:13 AM UTC 24 |
| Peak memory | 244396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246277173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1246277173 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.1468518083 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 28426872 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:31:52 AM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468518083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1468518083 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.1251934486 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 53480939 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:31:52 AM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251934486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1251934486 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.579356256 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 157175499 ps |
| CPU time | 2.41 seconds |
| Started | Sep 11 12:06:20 PM UTC 24 |
| Finished | Sep 11 12:06:24 PM UTC 24 |
| Peak memory | 234036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579356256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.579356256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.2618021213 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 52548506 ps |
| CPU time | 1.02 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618021213 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.2618021213 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.3339482018 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 12224439585 ps |
| CPU time | 41.46 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:32:32 AM UTC 24 |
| Peak memory | 256528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339482018 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3339482018 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_error.4181827278 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 19330468236 ps |
| CPU time | 623.17 seconds |
| Started | Sep 11 10:55:18 AM UTC 24 |
| Finished | Sep 11 11:05:49 AM UTC 24 |
| Peak memory | 629284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181827278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.4181827278 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.2802847810 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 50267852 ps |
| CPU time | 2.08 seconds |
| Started | Sep 11 11:10:13 AM UTC 24 |
| Finished | Sep 11 11:10:17 AM UTC 24 |
| Peak memory | 232060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802847810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2802847810 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.511390632 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 57106034 ps |
| CPU time | 2.33 seconds |
| Started | Sep 11 11:23:07 AM UTC 24 |
| Finished | Sep 11 11:23:11 AM UTC 24 |
| Peak memory | 234100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511390632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.511390632 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.3199956263 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 32456215 ps |
| CPU time | 1.83 seconds |
| Started | Sep 11 11:29:45 AM UTC 24 |
| Finished | Sep 11 11:29:47 AM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199956263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3199956263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.3912318469 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 56231713 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:31:52 AM UTC 24 |
| Peak memory | 226356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912318469 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3912318469 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.386066210 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 255686132 ps |
| CPU time | 4.46 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:43 AM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386066210 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.386066210 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1652690475 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 188895197 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652690475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.1652690475 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1509018259 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 80932190 ps |
| CPU time | 0.77 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509018259 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1509018259 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.2986917630 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1564333660 ps |
| CPU time | 12.4 seconds |
| Started | Sep 11 12:06:17 PM UTC 24 |
| Finished | Sep 11 12:06:31 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986917630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2986917630 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.2720377831 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 497473607 ps |
| CPU time | 4.6 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:16 AM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720377831 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.2720377831 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.4243135818 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 15778769263 ps |
| CPU time | 293.23 seconds |
| Started | Sep 11 10:31:53 AM UTC 24 |
| Finished | Sep 11 10:36:50 AM UTC 24 |
| Peak memory | 244236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243135818 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.4243135818 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.3716325174 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 22881574344 ps |
| CPU time | 57.75 seconds |
| Started | Sep 11 10:33:34 AM UTC 24 |
| Finished | Sep 11 10:34:33 AM UTC 24 |
| Peak memory | 236104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716325174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3716325174 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3290218368 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 46350266 ps |
| CPU time | 0.94 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:34 AM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290218368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.3290218368 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.4095483111 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 20100474092 ps |
| CPU time | 162.99 seconds |
| Started | Sep 11 10:44:39 AM UTC 24 |
| Finished | Sep 11 10:47:25 AM UTC 24 |
| Peak memory | 312300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4095483111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_r and_reset.4095483111 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2775036912 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 10565141031 ps |
| CPU time | 260.73 seconds |
| Started | Sep 11 11:46:46 AM UTC 24 |
| Finished | Sep 11 11:51:10 AM UTC 24 |
| Peak memory | 399972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775036912 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2775036912 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1363857184 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 397623551 ps |
| CPU time | 4.19 seconds |
| Started | Sep 11 08:39:33 AM UTC 24 |
| Finished | Sep 11 08:39:39 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363857184 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1363857184 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.887045393 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 13815674 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:45 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887045393 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.887045393 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1204521941 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 353515311 ps |
| CPU time | 4.02 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:29 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204521941 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1204521941 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.624857808 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 10683664820 ps |
| CPU time | 50.98 seconds |
| Started | Sep 11 10:31:48 AM UTC 24 |
| Finished | Sep 11 10:32:40 AM UTC 24 |
| Peak memory | 262620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624857808 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.624857808 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3932032382 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 91685874 ps |
| CPU time | 2.23 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932032382 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.3932 032382 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_app.2239181863 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9890491346 ps |
| CPU time | 94.52 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:33:26 AM UTC 24 |
| Peak memory | 277084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239181863 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2239181863 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.4132611808 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 753220718 ps |
| CPU time | 6.9 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:18 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132611808 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.4132611808 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2253740060 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 159719329 ps |
| CPU time | 6.95 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:18 AM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253740060 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2253740060 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2989682850 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 36357528 ps |
| CPU time | 0.87 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989682850 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2989682850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3071625213 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 639194451 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3071625213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_ rw_with_rand_reset.3071625213 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.152005150 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 47129611 ps |
| CPU time | 0.99 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152005150 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.152005150 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2215183088 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 30909127 ps |
| CPU time | 0.68 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:11 AM UTC 24 |
| Peak memory | 224436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215183088 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2215183088 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2283075681 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 137118690 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283075681 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.2283075681 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1682708532 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 56984618 ps |
| CPU time | 0.87 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682708532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1682708532 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.3807499764 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 58922852 ps |
| CPU time | 3.25 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:14 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807499764 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3807499764 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.2962666363 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1369946898 ps |
| CPU time | 2.9 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:14 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962666363 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.2962666363 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2670641439 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1462133514 ps |
| CPU time | 5.2 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:17 AM UTC 24 |
| Peak memory | 225472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670641439 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2670641439 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.1539102278 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 787733500 ps |
| CPU time | 9.37 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:21 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539102278 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1539102278 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2048667993 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 35577314 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048667993 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2048667993 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.13063909 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 36650629 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:14 AM UTC 24 |
| Peak memory | 230752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=13063909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw _with_rand_reset.13063909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.1916210848 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 39339628 ps |
| CPU time | 0.84 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916210848 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1916210848 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3968869056 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 40498367 ps |
| CPU time | 0.77 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968869056 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3968869056 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2745498755 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 62762787 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745498755 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2745498755 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.3595840525 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 15275595 ps |
| CPU time | 0.69 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 223328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595840525 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3595840525 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1092211956 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 247834753 ps |
| CPU time | 2.54 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:14 AM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092211956 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1092211956 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3889675238 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 28882120 ps |
| CPU time | 0.98 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889675238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.3889675238 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1542736779 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 107669179 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542736779 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.1542 736779 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.2324478035 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 29086746 ps |
| CPU time | 1.57 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324478035 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2324478035 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2780666985 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 77695068 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2780666985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem _rw_with_rand_reset.2780666985 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.3010717939 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 116461662 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010717939 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3010717939 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1510549606 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 48031571 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510549606 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1510549606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2227016431 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 94193954 ps |
| CPU time | 2.36 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 225672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227016431 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.2227016431 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.456701090 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 27369390 ps |
| CPU time | 0.93 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456701090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.456701090 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4176764942 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 28842501 ps |
| CPU time | 1.44 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176764942 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.417 6764942 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.64397592 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 152741925 ps |
| CPU time | 3.38 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:32 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64397592 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.64397592 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.474381559 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 278608280 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:41 AM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474381559 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.474381559 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.97749539 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 166168208 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=97749539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_r w_with_rand_reset.97749539 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3679055520 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 15246470 ps |
| CPU time | 0.95 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679055520 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3679055520 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2355825004 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 25222805 ps |
| CPU time | 0.78 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355825004 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2355825004 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3877728413 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 50682909 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877728413 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3877728413 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1923893015 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 251664189 ps |
| CPU time | 0.99 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923893015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1923893015 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.857854399 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 83990984 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857854399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.8578 54399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.4036501799 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 67562058 ps |
| CPU time | 1.82 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036501799 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.4036501799 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3840881608 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 1048304933 ps |
| CPU time | 2.89 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840881608 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3840881608 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1755478354 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 97487575 ps |
| CPU time | 1.61 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 226536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1755478354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem _rw_with_rand_reset.1755478354 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3623010830 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 13928047 ps |
| CPU time | 0.87 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623010830 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3623010830 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1068207137 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 16693792 ps |
| CPU time | 0.79 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068207137 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1068207137 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2165991542 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 37516364 ps |
| CPU time | 1.94 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165991542 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.2165991542 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.125682691 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 205809733 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125682691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.125682691 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1431868868 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 118439844 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431868868 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.143 1868868 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3219988558 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 111932660 ps |
| CPU time | 1.82 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219988558 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3219988558 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2833041958 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 429693888 ps |
| CPU time | 4.31 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:51 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833041958 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2833041958 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1627389749 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 155972885 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:39 AM UTC 24 |
| Peak memory | 228648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1627389749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem _rw_with_rand_reset.1627389749 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3906797660 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 23836166 ps |
| CPU time | 1 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:36 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906797660 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3906797660 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3244151856 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 15446906 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:39 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244151856 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3244151856 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3222890006 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 45486656 ps |
| CPU time | 1.89 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222890006 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3222890006 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3468973997 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 54535527 ps |
| CPU time | 1.03 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:36 AM UTC 24 |
| Peak memory | 224404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468973997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.3468973997 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2192204427 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 31271130 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:36 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192204427 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.219 2204427 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4265376822 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 57869131 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:38 AM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265376822 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4265376822 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.4249664237 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 498460119 ps |
| CPU time | 2.35 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:37 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249664237 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.4249664237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2049172172 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 156716231 ps |
| CPU time | 1.56 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2049172172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem _rw_with_rand_reset.2049172172 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.4093829972 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 63876857 ps |
| CPU time | 0.91 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:39 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093829972 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.4093829972 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1325060462 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 15054076 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:39 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325060462 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1325060462 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1081292156 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 59920165 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081292156 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.1081292156 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.312280636 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 26465301 ps |
| CPU time | 0.87 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:39 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312280636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.312280636 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2441801780 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 258312164 ps |
| CPU time | 2.7 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:41 AM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441801780 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.244 1801780 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.836598851 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 209529298 ps |
| CPU time | 1.72 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 223872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836598851 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.836598851 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1226316957 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 867976988 ps |
| CPU time | 4.48 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:43 AM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226316957 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1226316957 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.645331483 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 21468888 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:45 AM UTC 24 |
| Peak memory | 226528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=645331483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_ rw_with_rand_reset.645331483 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2768665701 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 45372588 ps |
| CPU time | 0.8 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:46 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768665701 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2768665701 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.391749356 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 14132365 ps |
| CPU time | 0.76 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:39 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391749356 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.391749356 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1772466439 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 437549240 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772466439 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1772466439 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3933489083 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 384170984 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933489083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.3933489083 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1612169678 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 200205026 ps |
| CPU time | 1.56 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612169678 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.161 2169678 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3086561040 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 143065240 ps |
| CPU time | 1.99 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086561040 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3086561040 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3199529105 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 181270842 ps |
| CPU time | 2.25 seconds |
| Started | Sep 11 08:39:31 AM UTC 24 |
| Finished | Sep 11 08:39:41 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199529105 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3199529105 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1356913552 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 82968234 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 08:39:34 AM UTC 24 |
| Finished | Sep 11 08:39:37 AM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1356913552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem _rw_with_rand_reset.1356913552 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1408753477 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 19628093 ps |
| CPU time | 0.94 seconds |
| Started | Sep 11 08:39:33 AM UTC 24 |
| Finished | Sep 11 08:39:36 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408753477 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1408753477 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1906880487 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 59980388 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:39:33 AM UTC 24 |
| Finished | Sep 11 08:39:35 AM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906880487 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1906880487 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.48882309 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 38125936 ps |
| CPU time | 1.91 seconds |
| Started | Sep 11 08:39:33 AM UTC 24 |
| Finished | Sep 11 08:39:37 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48882309 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.48882309 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2639992053 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 236631088 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 08:39:33 AM UTC 24 |
| Finished | Sep 11 08:39:36 AM UTC 24 |
| Peak memory | 226480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639992053 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.263 9992053 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3386647795 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 171255937 ps |
| CPU time | 2.49 seconds |
| Started | Sep 11 08:39:33 AM UTC 24 |
| Finished | Sep 11 08:39:37 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386647795 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3386647795 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4248189087 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 731914894 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 231680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4248189087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem _rw_with_rand_reset.4248189087 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.704582678 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 19415869 ps |
| CPU time | 1.02 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704582678 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.704582678 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1887155503 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 12473006 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:40 AM UTC 24 |
| Peak memory | 224264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887155503 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1887155503 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3613582597 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 89585849 ps |
| CPU time | 2.26 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 225472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613582597 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.3613582597 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2617485538 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 107056392 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 08:39:34 AM UTC 24 |
| Finished | Sep 11 08:39:36 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617485538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2617485538 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4177485217 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 50575964 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:39:36 AM UTC 24 |
| Finished | Sep 11 08:39:46 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177485217 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.417 7485217 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1961394915 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 148361475 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:42 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961394915 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1961394915 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2927170823 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 37288761 ps |
| CPU time | 1.41 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:46 AM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2927170823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem _rw_with_rand_reset.2927170823 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.864218839 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 67431439 ps |
| CPU time | 0.91 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:45 AM UTC 24 |
| Peak memory | 224532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864218839 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.864218839 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.251952072 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 137519848 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:46 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251952072 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.251952072 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1416465584 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 18283836 ps |
| CPU time | 0.91 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416465584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.1416465584 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3963033422 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 44572719 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963033422 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.396 3033422 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3566453043 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 513863476 ps |
| CPU time | 2.81 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566453043 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3566453043 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1405180729 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 175914055 ps |
| CPU time | 2.27 seconds |
| Started | Sep 11 08:39:38 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405180729 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1405180729 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1339715677 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 410432573 ps |
| CPU time | 2.54 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 231712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1339715677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem _rw_with_rand_reset.1339715677 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1258872984 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 45764339 ps |
| CPU time | 0.94 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:45 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258872984 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1258872984 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2356552059 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 13214185 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:45 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356552059 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2356552059 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2662537932 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 171438233 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662537932 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.2662537932 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.54250951 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 32755085 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:45 AM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54250951 -assert nopostproc + UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.54250951 +enable_masking=1 +s w_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3599288734 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 53730705 ps |
| CPU time | 2.08 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:46 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599288734 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.359 9288734 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1201199770 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1029159307 ps |
| CPU time | 3.34 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:48 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201199770 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1201199770 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.682765903 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 411913137 ps |
| CPU time | 2.67 seconds |
| Started | Sep 11 08:39:40 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682765903 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.682765903 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.2147998206 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 143232731 ps |
| CPU time | 6.94 seconds |
| Started | Sep 11 08:39:21 AM UTC 24 |
| Finished | Sep 11 08:39:29 AM UTC 24 |
| Peak memory | 225268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147998206 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2147998206 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2263663471 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5343790121 ps |
| CPU time | 19.2 seconds |
| Started | Sep 11 08:39:04 AM UTC 24 |
| Finished | Sep 11 08:39:32 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263663471 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2263663471 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.2296981220 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 81206486 ps |
| CPU time | 1.01 seconds |
| Started | Sep 11 08:39:04 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296981220 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2296981220 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1376523481 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 63689965 ps |
| CPU time | 1.93 seconds |
| Started | Sep 11 08:39:22 AM UTC 24 |
| Finished | Sep 11 08:39:24 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1376523481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_ rw_with_rand_reset.1376523481 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.2939475075 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 15532845 ps |
| CPU time | 0.98 seconds |
| Started | Sep 11 08:39:04 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939475075 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2939475075 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3220225030 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 32254663 ps |
| CPU time | 0.77 seconds |
| Started | Sep 11 08:39:04 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220225030 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3220225030 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.607712524 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 33888499 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607712524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.607712524 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.462775992 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 13546803 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:12 AM UTC 24 |
| Peak memory | 224428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462775992 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.462775992 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3668093121 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 25263064 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 08:39:21 AM UTC 24 |
| Finished | Sep 11 08:39:24 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668093121 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3668093121 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.965079470 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 364348511 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 224256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965079470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.965079470 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2986928366 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 183025553 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:14 AM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986928366 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.2986 928366 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.1449047938 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 190752657 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:13 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449047938 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1449047938 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.650555431 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 786552561 ps |
| CPU time | 2.48 seconds |
| Started | Sep 11 08:39:03 AM UTC 24 |
| Finished | Sep 11 08:39:14 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650555431 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.650555431 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2007433344 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 15798439 ps |
| CPU time | 0.7 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007433344 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2007433344 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.4117321208 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 33189132 ps |
| CPU time | 0.76 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117321208 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.4117321208 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1074815104 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 102394375 ps |
| CPU time | 0.65 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074815104 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1074815104 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.278448553 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 15579951 ps |
| CPU time | 0.76 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278448553 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.278448553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.231504985 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 55484949 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231504985 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.231504985 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3394860846 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 20017837 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394860846 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3394860846 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3741945587 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 17123332 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741945587 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3741945587 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2070102163 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 23175775 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:39:42 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070102163 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2070102163 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3143005532 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 17259524 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:39:43 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143005532 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3143005532 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1761327124 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 47763975 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:39:43 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761327124 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1761327124 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.3094006081 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 1021884752 ps |
| CPU time | 4.93 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:29 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094006081 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3094006081 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.1458410725 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 2567499386 ps |
| CPU time | 13.85 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:38 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458410725 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1458410725 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.3759134670 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 23852192 ps |
| CPU time | 0.97 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759134670 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3759134670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1781532073 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 151658727 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1781532073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_ rw_with_rand_reset.1781532073 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.1309522711 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 59880100 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309522711 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1309522711 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.1849156956 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 22090388 ps |
| CPU time | 0.76 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849156956 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1849156956 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3659601909 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 72468702 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659601909 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3659601909 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1152396121 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 83286752 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:24 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152396121 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1152396121 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2679498651 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 223804730 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679498651 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2679498651 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1857811267 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 64416907 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 08:39:22 AM UTC 24 |
| Finished | Sep 11 08:39:24 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857811267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.1857811267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1567436649 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 159655074 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 08:39:22 AM UTC 24 |
| Finished | Sep 11 08:39:24 AM UTC 24 |
| Peak memory | 228464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567436649 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.1567 436649 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2893257162 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 150912513 ps |
| CPU time | 2.59 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893257162 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2893257162 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.2723099445 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 221317666 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723099445 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.2723099445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1014317347 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 50957078 ps |
| CPU time | 0.69 seconds |
| Started | Sep 11 08:39:43 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014317347 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1014317347 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.853284660 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 19442284 ps |
| CPU time | 0.68 seconds |
| Started | Sep 11 08:39:43 AM UTC 24 |
| Finished | Sep 11 08:39:44 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853284660 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.853284660 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.95410536 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 16112985 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:39:43 AM UTC 24 |
| Finished | Sep 11 08:39:45 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95410536 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.95410536 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3798470742 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 37319210 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:46 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798470742 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3798470742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3164487972 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 115371661 ps |
| CPU time | 0.68 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:46 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164487972 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3164487972 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3643904033 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 65644800 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643904033 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3643904033 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3161766015 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 14249989 ps |
| CPU time | 0.8 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161766015 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3161766015 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1279033066 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 184220451 ps |
| CPU time | 0.78 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279033066 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1279033066 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2367498085 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 36369685 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367498085 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2367498085 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.967798168 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 15813010 ps |
| CPU time | 0.78 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967798168 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.967798168 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.4142229041 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 286918875 ps |
| CPU time | 7.06 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:32 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142229041 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.4142229041 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2332312573 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 559978193 ps |
| CPU time | 7.46 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:32 AM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332312573 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2332312573 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.1980553472 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 38596579 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980553472 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1980553472 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1216323022 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 138991038 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1216323022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_ rw_with_rand_reset.1216323022 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.1378119356 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 19545492 ps |
| CPU time | 0.86 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378119356 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1378119356 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2431001169 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 43124312 ps |
| CPU time | 0.82 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431001169 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2431001169 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.1501111303 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 147172477 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501111303 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.1501111303 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.371380251 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 146462461 ps |
| CPU time | 0.68 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:25 AM UTC 24 |
| Peak memory | 224608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371380251 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.371380251 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1602541316 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 70836142 ps |
| CPU time | 1.91 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602541316 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.1602541316 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4081977590 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 152366382 ps |
| CPU time | 2.71 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081977590 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.4081 977590 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3061477340 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 118289595 ps |
| CPU time | 2.92 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061477340 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3061477340 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1514027670 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 335436086 ps |
| CPU time | 3.8 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:28 AM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514027670 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.1514027670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.868559166 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 49367594 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868559166 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.868559166 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.454864405 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 16047823 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454864405 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.454864405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.147451894 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 18539063 ps |
| CPU time | 0.78 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147451894 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.147451894 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.2657979377 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 14425947 ps |
| CPU time | 0.7 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657979377 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2657979377 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1000112153 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 11849514 ps |
| CPU time | 0.78 seconds |
| Started | Sep 11 08:39:45 AM UTC 24 |
| Finished | Sep 11 08:39:47 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000112153 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1000112153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3220098967 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 52551472 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 224956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220098967 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3220098967 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2531306644 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 15556325 ps |
| CPU time | 0.79 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531306644 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2531306644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.873178716 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 42688095 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 224224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873178716 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.873178716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.4057269698 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 13400692 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057269698 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.4057269698 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1822826147 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 24299478 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822826147 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1822826147 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3797425692 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 129660760 ps |
| CPU time | 1.89 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 230748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3797425692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_ rw_with_rand_reset.3797425692 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.1745759532 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 50795561 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745759532 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1745759532 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1550609980 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 127182991 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550609980 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1550609980 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3574160943 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 216739731 ps |
| CPU time | 2.49 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574160943 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.3574 160943 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.2772976790 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 61722522 ps |
| CPU time | 3.59 seconds |
| Started | Sep 11 08:39:23 AM UTC 24 |
| Finished | Sep 11 08:39:28 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772976790 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2772976790 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1509146958 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 101460777 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1509146958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_ rw_with_rand_reset.1509146958 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3190258065 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 25428003 ps |
| CPU time | 1.01 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190258065 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3190258065 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.4017453414 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 19993584 ps |
| CPU time | 0.99 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017453414 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.4017453414 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1175909337 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 28074164 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175909337 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1175909337 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3629756954 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 91898822 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629756954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.3629756954 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1941823107 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 28487516 ps |
| CPU time | 1.52 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941823107 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.1941 823107 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.3923497521 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 721993934 ps |
| CPU time | 3.43 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:28 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923497521 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3923497521 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.4173978787 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 219328387 ps |
| CPU time | 4.62 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173978787 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.4173978787 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2508435472 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 228096231 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2508435472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_ rw_with_rand_reset.2508435472 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.818723660 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 15651148 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818723660 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.818723660 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3189858578 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 21979849 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 224608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189858578 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3189858578 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2836482771 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 120326193 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836482771 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.2836482771 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.741738047 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 502155371 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:26 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741738047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.741738047 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1213894360 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 387878602 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213894360 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.1213 894360 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1488989807 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 72465137 ps |
| CPU time | 1.77 seconds |
| Started | Sep 11 08:39:24 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488989807 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1488989807 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.925922753 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 64672908 ps |
| CPU time | 2.03 seconds |
| Started | Sep 11 08:39:27 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 231432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=925922753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_r w_with_rand_reset.925922753 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.4974458 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 46643431 ps |
| CPU time | 0.88 seconds |
| Started | Sep 11 08:39:25 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4974458 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4974458 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.30091064 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 27435677 ps |
| CPU time | 0.84 seconds |
| Started | Sep 11 08:39:25 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30091064 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.30091064 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2989653511 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 312577224 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:39:27 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 224320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989653511 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.2989653511 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3235952593 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 24507250 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 08:39:25 AM UTC 24 |
| Finished | Sep 11 08:39:27 AM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235952593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.3235952593 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4004492003 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 871492301 ps |
| CPU time | 2.35 seconds |
| Started | Sep 11 08:39:25 AM UTC 24 |
| Finished | Sep 11 08:39:28 AM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004492003 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.4004 492003 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.834076379 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 111357074 ps |
| CPU time | 2.4 seconds |
| Started | Sep 11 08:39:25 AM UTC 24 |
| Finished | Sep 11 08:39:29 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834076379 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.834076379 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1258887883 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 889447792 ps |
| CPU time | 4.45 seconds |
| Started | Sep 11 08:39:25 AM UTC 24 |
| Finished | Sep 11 08:39:31 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258887883 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.1258887883 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.886935720 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 23466232 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 226540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=886935720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_r w_with_rand_reset.886935720 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3771214305 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 13037604 ps |
| CPU time | 0.87 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:29 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771214305 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3771214305 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.1124476504 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 28455660 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:29 AM UTC 24 |
| Peak memory | 224548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124476504 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1124476504 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.267339734 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 25396308 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 08:39:28 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267339734 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.267339734 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1806981056 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 61634165 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 08:39:27 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806981056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.1806981056 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.748946838 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 29733744 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 08:39:27 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748946838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.74894 6838 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2613293604 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 224843001 ps |
| CPU time | 1.64 seconds |
| Started | Sep 11 08:39:27 AM UTC 24 |
| Finished | Sep 11 08:39:30 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613293604 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2613293604 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.968356924 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 103367814 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 08:39:27 AM UTC 24 |
| Finished | Sep 11 08:39:31 AM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968356924 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.968356924 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.3205010204 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 18240086338 ps |
| CPU time | 773.42 seconds |
| Started | Sep 11 10:31:48 AM UTC 24 |
| Finished | Sep 11 10:44:50 AM UTC 24 |
| Peak memory | 258648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205010204 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3205010204 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.1260917093 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8143904003 ps |
| CPU time | 30.84 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:32:22 AM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260917093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1260917093 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.514935488 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 31791612416 ps |
| CPU time | 149.47 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:34:21 AM UTC 24 |
| Peak memory | 283236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514935488 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.514935488 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.3593185683 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 479792254782 ps |
| CPU time | 1182.21 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:51:21 AM UTC 24 |
| Peak memory | 1339996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593185683 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.3593185683 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.804285417 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 18218438484 ps |
| CPU time | 164.4 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:34:36 AM UTC 24 |
| Peak memory | 361316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804285417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.804285417 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.3612477505 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 35229071901 ps |
| CPU time | 101.76 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:33:33 AM UTC 24 |
| Peak memory | 317204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612477505 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3612477505 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.224347845 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1894551808 ps |
| CPU time | 57.3 seconds |
| Started | Sep 11 10:31:48 AM UTC 24 |
| Finished | Sep 11 10:32:47 AM UTC 24 |
| Peak memory | 276952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224347845 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.224347845 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.2074395518 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6125906159 ps |
| CPU time | 40.97 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:32:32 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074395518 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2074395518 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.1959870399 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 171992872 ps |
| CPU time | 3.37 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:31:53 AM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959870399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.1959870399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3944460501 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 91076104 ps |
| CPU time | 3.46 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:31:54 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944460501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3944460501 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1347668483 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3036879811 ps |
| CPU time | 53.33 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:32:44 AM UTC 24 |
| Peak memory | 242124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347668483 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1347668483 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.2691914442 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 31269468678 ps |
| CPU time | 1130.2 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:50:54 AM UTC 24 |
| Peak memory | 717256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691914442 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2691914442 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.1767619634 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 212123377883 ps |
| CPU time | 3573.82 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 11:32:01 AM UTC 24 |
| Peak memory | 3766728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767619634 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1767619634 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.2918546253 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2815894643 ps |
| CPU time | 107.79 seconds |
| Started | Sep 11 10:31:49 AM UTC 24 |
| Finished | Sep 11 10:33:39 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918546253 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2918546253 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.2593773309 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 201153660 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 10:32:17 AM UTC 24 |
| Finished | Sep 11 10:32:19 AM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593773309 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2593773309 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_app.171832486 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 28325808983 ps |
| CPU time | 86.74 seconds |
| Started | Sep 11 10:32:01 AM UTC 24 |
| Finished | Sep 11 10:33:30 AM UTC 24 |
| Peak memory | 266776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171832486 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.171832486 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1475544582 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15700374948 ps |
| CPU time | 126.41 seconds |
| Started | Sep 11 10:32:01 AM UTC 24 |
| Finished | Sep 11 10:34:10 AM UTC 24 |
| Peak memory | 295512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475544582 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1475544582 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.235394106 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 10335150338 ps |
| CPU time | 500.61 seconds |
| Started | Sep 11 10:31:50 AM UTC 24 |
| Finished | Sep 11 10:40:17 AM UTC 24 |
| Peak memory | 244284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235394106 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.235394106 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.2547313092 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 27089523 ps |
| CPU time | 1.47 seconds |
| Started | Sep 11 10:32:10 AM UTC 24 |
| Finished | Sep 11 10:32:12 AM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547313092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2547313092 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.1574272956 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 57499795 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 10:32:10 AM UTC 24 |
| Finished | Sep 11 10:32:12 AM UTC 24 |
| Peak memory | 227880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574272956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1574272956 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.1574255062 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 11882746809 ps |
| CPU time | 370.99 seconds |
| Started | Sep 11 10:32:01 AM UTC 24 |
| Finished | Sep 11 10:38:17 AM UTC 24 |
| Peak memory | 498212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574255062 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1574255062 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_error.1584914968 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 169436634 ps |
| CPU time | 6.26 seconds |
| Started | Sep 11 10:32:01 AM UTC 24 |
| Finished | Sep 11 10:32:09 AM UTC 24 |
| Peak memory | 234480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584914968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1584914968 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.4013481063 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 722473019 ps |
| CPU time | 4.76 seconds |
| Started | Sep 11 10:32:06 AM UTC 24 |
| Finished | Sep 11 10:32:12 AM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013481063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.4013481063 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.3746113015 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 39011331 ps |
| CPU time | 2.13 seconds |
| Started | Sep 11 10:32:13 AM UTC 24 |
| Finished | Sep 11 10:32:16 AM UTC 24 |
| Peak memory | 234092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746113015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3746113015 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.354681924 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 368730488741 ps |
| CPU time | 3124.98 seconds |
| Started | Sep 11 10:31:50 AM UTC 24 |
| Finished | Sep 11 11:24:28 AM UTC 24 |
| Peak memory | 3543548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354681924 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.354681924 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.3118724605 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 26452403621 ps |
| CPU time | 237.51 seconds |
| Started | Sep 11 10:32:01 AM UTC 24 |
| Finished | Sep 11 10:36:03 AM UTC 24 |
| Peak memory | 367524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118724605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3118724605 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.3872241153 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3851473579 ps |
| CPU time | 328.17 seconds |
| Started | Sep 11 10:31:50 AM UTC 24 |
| Finished | Sep 11 10:37:23 AM UTC 24 |
| Peak memory | 344656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872241153 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.3872241153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.1156682744 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2325809077 ps |
| CPU time | 48.13 seconds |
| Started | Sep 11 10:31:50 AM UTC 24 |
| Finished | Sep 11 10:32:39 AM UTC 24 |
| Peak memory | 234228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156682744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1156682744 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.3152598302 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 33745270488 ps |
| CPU time | 1426.5 seconds |
| Started | Sep 11 10:32:13 AM UTC 24 |
| Finished | Sep 11 10:56:16 AM UTC 24 |
| Peak memory | 687012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152598302 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3152598302 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.1857412839 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31921152974 ps |
| CPU time | 102.9 seconds |
| Started | Sep 11 10:32:14 AM UTC 24 |
| Finished | Sep 11 10:33:59 AM UTC 24 |
| Peak memory | 295604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1857412839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_r and_reset.1857412839 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.1275626926 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 42150570 ps |
| CPU time | 3.28 seconds |
| Started | Sep 11 10:31:53 AM UTC 24 |
| Finished | Sep 11 10:31:57 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275626926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.1275626926 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.706256350 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 360166768 ps |
| CPU time | 4.03 seconds |
| Started | Sep 11 10:32:01 AM UTC 24 |
| Finished | Sep 11 10:32:06 AM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706256350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.706256350 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.2649816492 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 60741114346 ps |
| CPU time | 2831.13 seconds |
| Started | Sep 11 10:31:50 AM UTC 24 |
| Finished | Sep 11 11:19:32 AM UTC 24 |
| Peak memory | 3131908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649816492 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2649816492 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.1184739154 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 58210784361 ps |
| CPU time | 2519.91 seconds |
| Started | Sep 11 10:31:50 AM UTC 24 |
| Finished | Sep 11 11:14:17 AM UTC 24 |
| Peak memory | 2980292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184739154 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1184739154 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.1847460186 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 16057530159 ps |
| CPU time | 95.26 seconds |
| Started | Sep 11 10:31:50 AM UTC 24 |
| Finished | Sep 11 10:33:27 AM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847460186 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1847460186 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.220782953 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4214638487 ps |
| CPU time | 20.99 seconds |
| Started | Sep 11 10:31:53 AM UTC 24 |
| Finished | Sep 11 10:32:15 AM UTC 24 |
| Peak memory | 234344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220782953 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.220782953 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1827249227 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 37258989365 ps |
| CPU time | 383.81 seconds |
| Started | Sep 11 10:31:53 AM UTC 24 |
| Finished | Sep 11 10:38:22 AM UTC 24 |
| Peak memory | 369160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827249227 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1827249227 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.3901997966 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 52706641 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 10:54:28 AM UTC 24 |
| Finished | Sep 11 10:54:31 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901997966 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3901997966 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_app.758044227 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 22122873012 ps |
| CPU time | 325.44 seconds |
| Started | Sep 11 10:53:13 AM UTC 24 |
| Finished | Sep 11 10:58:43 AM UTC 24 |
| Peak memory | 340584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758044227 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.758044227 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.1233896205 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 34555476837 ps |
| CPU time | 865.75 seconds |
| Started | Sep 11 10:53:02 AM UTC 24 |
| Finished | Sep 11 11:07:38 AM UTC 24 |
| Peak memory | 260692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233896205 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1233896205 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.714474234 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 7487027739 ps |
| CPU time | 38.65 seconds |
| Started | Sep 11 10:54:05 AM UTC 24 |
| Finished | Sep 11 10:54:45 AM UTC 24 |
| Peak memory | 236024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714474234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.714474234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.2425372564 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 91741909 ps |
| CPU time | 1.37 seconds |
| Started | Sep 11 10:54:12 AM UTC 24 |
| Finished | Sep 11 10:54:15 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425372564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2425372564 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.1856184713 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1703483015 ps |
| CPU time | 40.58 seconds |
| Started | Sep 11 10:53:14 AM UTC 24 |
| Finished | Sep 11 10:53:56 AM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856184713 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1856184713 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_error.4169083047 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6332350534 ps |
| CPU time | 148.48 seconds |
| Started | Sep 11 10:53:19 AM UTC 24 |
| Finished | Sep 11 10:55:50 AM UTC 24 |
| Peak memory | 320032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169083047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.4169083047 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.3412004169 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1496416886 ps |
| CPU time | 6.77 seconds |
| Started | Sep 11 10:53:57 AM UTC 24 |
| Finished | Sep 11 10:54:05 AM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412004169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3412004169 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.614048201 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 8683592889 ps |
| CPU time | 699.44 seconds |
| Started | Sep 11 10:51:57 AM UTC 24 |
| Finished | Sep 11 11:03:45 AM UTC 24 |
| Peak memory | 592480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614048201 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.614048201 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.2578495152 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5264180689 ps |
| CPU time | 186.37 seconds |
| Started | Sep 11 10:52:08 AM UTC 24 |
| Finished | Sep 11 10:55:17 AM UTC 24 |
| Peak memory | 361056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578495152 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2578495152 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.270783731 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 6306834174 ps |
| CPU time | 74.59 seconds |
| Started | Sep 11 10:51:57 AM UTC 24 |
| Finished | Sep 11 10:53:13 AM UTC 24 |
| Peak memory | 236068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270783731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.270783731 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.3548233571 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 19497650038 ps |
| CPU time | 86.75 seconds |
| Started | Sep 11 10:54:19 AM UTC 24 |
| Finished | Sep 11 10:55:48 AM UTC 24 |
| Peak memory | 277408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548233571 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3548233571 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.3197296352 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 79456140 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 10:56:04 AM UTC 24 |
| Finished | Sep 11 10:56:06 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197296352 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3197296352 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_app.3332405821 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 12731016696 ps |
| CPU time | 360.67 seconds |
| Started | Sep 11 10:54:59 AM UTC 24 |
| Finished | Sep 11 11:01:04 AM UTC 24 |
| Peak memory | 547412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332405821 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3332405821 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.2989384605 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 12744450622 ps |
| CPU time | 1224.28 seconds |
| Started | Sep 11 10:54:46 AM UTC 24 |
| Finished | Sep 11 11:15:25 AM UTC 24 |
| Peak memory | 256528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989384605 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2989384605 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.73347628 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 204505280 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 10:55:49 AM UTC 24 |
| Finished | Sep 11 10:55:52 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73347628 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/k mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.73347628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.556893617 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5809718250 ps |
| CPU time | 45.96 seconds |
| Started | Sep 11 10:55:51 AM UTC 24 |
| Finished | Sep 11 10:56:39 AM UTC 24 |
| Peak memory | 235932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556893617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.556893617 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.1291747696 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 45189239310 ps |
| CPU time | 326.18 seconds |
| Started | Sep 11 10:55:08 AM UTC 24 |
| Finished | Sep 11 11:00:39 AM UTC 24 |
| Peak memory | 434796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291747696 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1291747696 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.3721741954 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 917153324 ps |
| CPU time | 10.49 seconds |
| Started | Sep 11 10:55:47 AM UTC 24 |
| Finished | Sep 11 10:55:59 AM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721741954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3721741954 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.2241737810 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 209946830 ps |
| CPU time | 9.23 seconds |
| Started | Sep 11 10:55:52 AM UTC 24 |
| Finished | Sep 11 10:56:03 AM UTC 24 |
| Peak memory | 246264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241737810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2241737810 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.3366465152 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 211302747655 ps |
| CPU time | 2276.82 seconds |
| Started | Sep 11 10:54:34 AM UTC 24 |
| Finished | Sep 11 11:32:55 AM UTC 24 |
| Peak memory | 2613792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366465152 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.3366465152 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.1723218269 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 16229847461 ps |
| CPU time | 281.42 seconds |
| Started | Sep 11 10:54:46 AM UTC 24 |
| Finished | Sep 11 10:59:32 AM UTC 24 |
| Peak memory | 436764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723218269 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1723218269 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.63799750 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3351170598 ps |
| CPU time | 73.01 seconds |
| Started | Sep 11 10:54:32 AM UTC 24 |
| Finished | Sep 11 10:55:46 AM UTC 24 |
| Peak memory | 236064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63799750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.63799750 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.36878803 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 157439199224 ps |
| CPU time | 1209.54 seconds |
| Started | Sep 11 10:56:00 AM UTC 24 |
| Finished | Sep 11 11:16:23 AM UTC 24 |
| Peak memory | 705440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36878803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.36878803 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.192325953 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 19651561 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 10:59:56 AM UTC 24 |
| Finished | Sep 11 10:59:59 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192325953 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.192325953 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_app.1550981052 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 26814013455 ps |
| CPU time | 396.66 seconds |
| Started | Sep 11 10:57:47 AM UTC 24 |
| Finished | Sep 11 11:04:30 AM UTC 24 |
| Peak memory | 326324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550981052 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1550981052 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.3484910419 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 49493510725 ps |
| CPU time | 1570.65 seconds |
| Started | Sep 11 10:56:52 AM UTC 24 |
| Finished | Sep 11 11:23:21 AM UTC 24 |
| Peak memory | 270888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484910419 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3484910419 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.1995316650 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 358107514 ps |
| CPU time | 16.17 seconds |
| Started | Sep 11 10:59:34 AM UTC 24 |
| Finished | Sep 11 10:59:51 AM UTC 24 |
| Peak memory | 248188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995316650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1995316650 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1891901457 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 42430534 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 10:59:49 AM UTC 24 |
| Finished | Sep 11 10:59:51 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891901457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1891901457 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.4196466808 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 14450434000 ps |
| CPU time | 102.75 seconds |
| Started | Sep 11 10:57:48 AM UTC 24 |
| Finished | Sep 11 10:59:33 AM UTC 24 |
| Peak memory | 279112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196466808 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.4196466808 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_error.2399554294 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 18163672996 ps |
| CPU time | 477.55 seconds |
| Started | Sep 11 10:58:44 AM UTC 24 |
| Finished | Sep 11 11:06:47 AM UTC 24 |
| Peak memory | 629344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399554294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2399554294 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.8707794 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3497648653 ps |
| CPU time | 21.22 seconds |
| Started | Sep 11 10:59:33 AM UTC 24 |
| Finished | Sep 11 10:59:55 AM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8707794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.8707794 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.2312385002 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 613213498 ps |
| CPU time | 22.96 seconds |
| Started | Sep 11 10:59:52 AM UTC 24 |
| Finished | Sep 11 11:00:17 AM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312385002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2312385002 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.1014814749 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 25932928519 ps |
| CPU time | 2980.51 seconds |
| Started | Sep 11 10:56:17 AM UTC 24 |
| Finished | Sep 11 11:46:30 AM UTC 24 |
| Peak memory | 1780220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014814749 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.1014814749 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.684849974 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5338216901 ps |
| CPU time | 406.11 seconds |
| Started | Sep 11 10:56:40 AM UTC 24 |
| Finished | Sep 11 11:03:31 AM UTC 24 |
| Peak memory | 375320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684849974 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.684849974 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.2138472540 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4411701120 ps |
| CPU time | 98.59 seconds |
| Started | Sep 11 10:56:07 AM UTC 24 |
| Finished | Sep 11 10:57:47 AM UTC 24 |
| Peak memory | 238172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138472540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2138472540 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.2172695314 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 122948484038 ps |
| CPU time | 5021.14 seconds |
| Started | Sep 11 10:59:52 AM UTC 24 |
| Finished | Sep 11 12:24:31 PM UTC 24 |
| Peak memory | 1444480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172695314 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2172695314 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.2355228053 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 16737623 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 11:03:34 AM UTC 24 |
| Finished | Sep 11 11:03:37 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355228053 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2355228053 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_app.1093912466 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2324374910 ps |
| CPU time | 152.26 seconds |
| Started | Sep 11 11:00:40 AM UTC 24 |
| Finished | Sep 11 11:03:15 AM UTC 24 |
| Peak memory | 279132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093912466 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1093912466 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.2248980474 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 29491274852 ps |
| CPU time | 744.92 seconds |
| Started | Sep 11 11:00:24 AM UTC 24 |
| Finished | Sep 11 11:12:58 AM UTC 24 |
| Peak memory | 256544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248980474 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2248980474 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2167589745 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 22955667 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 11:03:27 AM UTC 24 |
| Finished | Sep 11 11:03:29 AM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167589745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2167589745 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.2830377413 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3662706140 ps |
| CPU time | 41.34 seconds |
| Started | Sep 11 11:03:29 AM UTC 24 |
| Finished | Sep 11 11:04:12 AM UTC 24 |
| Peak memory | 235900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830377413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2830377413 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.1171840604 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2489466461 ps |
| CPU time | 81.08 seconds |
| Started | Sep 11 11:01:05 AM UTC 24 |
| Finished | Sep 11 11:02:28 AM UTC 24 |
| Peak memory | 256584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171840604 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1171840604 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_error.1243265116 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 14550117947 ps |
| CPU time | 548.54 seconds |
| Started | Sep 11 11:02:29 AM UTC 24 |
| Finished | Sep 11 11:11:45 AM UTC 24 |
| Peak memory | 627232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243265116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1243265116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.3207267936 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1264439028 ps |
| CPU time | 8.78 seconds |
| Started | Sep 11 11:03:16 AM UTC 24 |
| Finished | Sep 11 11:03:26 AM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207267936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3207267936 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.1825437688 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 123285723 ps |
| CPU time | 2.05 seconds |
| Started | Sep 11 11:03:30 AM UTC 24 |
| Finished | Sep 11 11:03:33 AM UTC 24 |
| Peak memory | 232056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825437688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1825437688 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.3410962233 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 17009846504 ps |
| CPU time | 1927.34 seconds |
| Started | Sep 11 11:00:17 AM UTC 24 |
| Finished | Sep 11 11:32:47 AM UTC 24 |
| Peak memory | 1227296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410962233 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.3410962233 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.1881013391 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4391498949 ps |
| CPU time | 338.77 seconds |
| Started | Sep 11 11:00:18 AM UTC 24 |
| Finished | Sep 11 11:06:01 AM UTC 24 |
| Peak memory | 363036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881013391 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1881013391 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.785784853 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 669658142 ps |
| CPU time | 16.9 seconds |
| Started | Sep 11 11:00:00 AM UTC 24 |
| Finished | Sep 11 11:00:22 AM UTC 24 |
| Peak memory | 235936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785784853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.785784853 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.3180715211 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 26373672810 ps |
| CPU time | 1070.51 seconds |
| Started | Sep 11 11:03:32 AM UTC 24 |
| Finished | Sep 11 11:21:36 AM UTC 24 |
| Peak memory | 903760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180715211 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3180715211 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.2357978974 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 35922060 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 11:05:54 AM UTC 24 |
| Finished | Sep 11 11:05:56 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357978974 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2357978974 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_app.2890373299 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 6790231212 ps |
| CPU time | 226.02 seconds |
| Started | Sep 11 11:04:13 AM UTC 24 |
| Finished | Sep 11 11:08:02 AM UTC 24 |
| Peak memory | 387684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890373299 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2890373299 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.2320741410 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 7393027505 ps |
| CPU time | 799.57 seconds |
| Started | Sep 11 11:03:49 AM UTC 24 |
| Finished | Sep 11 11:17:18 AM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320741410 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2320741410 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.1651566358 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 22842768 ps |
| CPU time | 1.63 seconds |
| Started | Sep 11 11:05:49 AM UTC 24 |
| Finished | Sep 11 11:05:51 AM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651566358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1651566358 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.1614941062 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 51180517 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 11:05:51 AM UTC 24 |
| Finished | Sep 11 11:05:53 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614941062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1614941062 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.79462181 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 8176456918 ps |
| CPU time | 99.63 seconds |
| Started | Sep 11 11:04:31 AM UTC 24 |
| Finished | Sep 11 11:06:13 AM UTC 24 |
| Peak memory | 289452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79462181 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.79462181 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_error.4027934225 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 25931809842 ps |
| CPU time | 476.73 seconds |
| Started | Sep 11 11:04:33 AM UTC 24 |
| Finished | Sep 11 11:12:36 AM UTC 24 |
| Peak memory | 662048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027934225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.4027934225 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.3548413877 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 891915936 ps |
| CPU time | 10.27 seconds |
| Started | Sep 11 11:05:40 AM UTC 24 |
| Finished | Sep 11 11:05:52 AM UTC 24 |
| Peak memory | 227960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548413877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3548413877 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.4283598588 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 156748600 ps |
| CPU time | 2.04 seconds |
| Started | Sep 11 11:05:52 AM UTC 24 |
| Finished | Sep 11 11:05:55 AM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283598588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.4283598588 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.462332902 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 548868812737 ps |
| CPU time | 5162.77 seconds |
| Started | Sep 11 11:03:37 AM UTC 24 |
| Finished | Sep 11 12:30:37 PM UTC 24 |
| Peak memory | 4950664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462332902 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.462332902 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.1653052585 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 64634902098 ps |
| CPU time | 575.83 seconds |
| Started | Sep 11 11:03:46 AM UTC 24 |
| Finished | Sep 11 11:13:29 AM UTC 24 |
| Peak memory | 586336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653052585 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1653052585 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.425299988 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1404487802 ps |
| CPU time | 12.01 seconds |
| Started | Sep 11 11:03:34 AM UTC 24 |
| Finished | Sep 11 11:03:48 AM UTC 24 |
| Peak memory | 235976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425299988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.425299988 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.649193385 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 147762287465 ps |
| CPU time | 1711.45 seconds |
| Started | Sep 11 11:05:53 AM UTC 24 |
| Finished | Sep 11 11:34:44 AM UTC 24 |
| Peak memory | 660392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649193385 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.649193385 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.4229549165 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 29898090 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 11:07:51 AM UTC 24 |
| Finished | Sep 11 11:07:54 AM UTC 24 |
| Peak memory | 225332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229549165 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.4229549165 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_app.3548072717 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 7314537828 ps |
| CPU time | 226.91 seconds |
| Started | Sep 11 11:06:21 AM UTC 24 |
| Finished | Sep 11 11:10:12 AM UTC 24 |
| Peak memory | 367188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548072717 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3548072717 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.834576696 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2779560547 ps |
| CPU time | 200.85 seconds |
| Started | Sep 11 11:06:13 AM UTC 24 |
| Finished | Sep 11 11:09:37 AM UTC 24 |
| Peak memory | 238176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834576696 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.834576696 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.3877177735 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 647319462 ps |
| CPU time | 14.48 seconds |
| Started | Sep 11 11:07:35 AM UTC 24 |
| Finished | Sep 11 11:07:50 AM UTC 24 |
| Peak memory | 232108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877177735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3877177735 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.1088733989 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 62200717 ps |
| CPU time | 1.37 seconds |
| Started | Sep 11 11:07:39 AM UTC 24 |
| Finished | Sep 11 11:07:41 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088733989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1088733989 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.3706649894 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 9042396674 ps |
| CPU time | 170.02 seconds |
| Started | Sep 11 11:06:27 AM UTC 24 |
| Finished | Sep 11 11:09:20 AM UTC 24 |
| Peak memory | 330340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706649894 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3706649894 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_error.3215125306 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 922250890 ps |
| CPU time | 25.55 seconds |
| Started | Sep 11 11:06:49 AM UTC 24 |
| Finished | Sep 11 11:07:15 AM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215125306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3215125306 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.1493415732 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2752923915 ps |
| CPU time | 16.56 seconds |
| Started | Sep 11 11:07:17 AM UTC 24 |
| Finished | Sep 11 11:07:34 AM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493415732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1493415732 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.1114527337 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 109653705 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 11:07:42 AM UTC 24 |
| Finished | Sep 11 11:07:45 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114527337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1114527337 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.1649273401 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 187022356467 ps |
| CPU time | 1622.79 seconds |
| Started | Sep 11 11:05:57 AM UTC 24 |
| Finished | Sep 11 11:33:18 AM UTC 24 |
| Peak memory | 1968736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649273401 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.1649273401 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.725282411 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2327773786 ps |
| CPU time | 22.64 seconds |
| Started | Sep 11 11:06:02 AM UTC 24 |
| Finished | Sep 11 11:06:27 AM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725282411 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.725282411 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.1983068936 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1657880843 ps |
| CPU time | 22.6 seconds |
| Started | Sep 11 11:05:56 AM UTC 24 |
| Finished | Sep 11 11:06:20 AM UTC 24 |
| Peak memory | 234096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983068936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1983068936 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.3763184442 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 153622575059 ps |
| CPU time | 777.01 seconds |
| Started | Sep 11 11:07:46 AM UTC 24 |
| Finished | Sep 11 11:20:53 AM UTC 24 |
| Peak memory | 480100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763184442 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3763184442 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.1459665776 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 81750035 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 11:10:18 AM UTC 24 |
| Finished | Sep 11 11:10:20 AM UTC 24 |
| Peak memory | 224852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459665776 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1459665776 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_app.4194772956 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 17755777295 ps |
| CPU time | 190.12 seconds |
| Started | Sep 11 11:09:20 AM UTC 24 |
| Finished | Sep 11 11:12:33 AM UTC 24 |
| Peak memory | 303652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194772956 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.4194772956 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.1326062419 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 40332256256 ps |
| CPU time | 621.72 seconds |
| Started | Sep 11 11:08:31 AM UTC 24 |
| Finished | Sep 11 11:19:01 AM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326062419 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.1326062419 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2180063519 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 831943187 ps |
| CPU time | 42.98 seconds |
| Started | Sep 11 11:09:55 AM UTC 24 |
| Finished | Sep 11 11:10:40 AM UTC 24 |
| Peak memory | 235664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180063519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2180063519 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.4199562608 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 22563296 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 11:10:12 AM UTC 24 |
| Finished | Sep 11 11:10:15 AM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199562608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4199562608 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.4222806604 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3272838595 ps |
| CPU time | 228.4 seconds |
| Started | Sep 11 11:09:21 AM UTC 24 |
| Finished | Sep 11 11:13:13 AM UTC 24 |
| Peak memory | 289400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222806604 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.4222806604 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_error.2178816098 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1439966418 ps |
| CPU time | 39.59 seconds |
| Started | Sep 11 11:09:30 AM UTC 24 |
| Finished | Sep 11 11:10:11 AM UTC 24 |
| Peak memory | 252292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178816098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2178816098 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.1264038972 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5642967741 ps |
| CPU time | 15.11 seconds |
| Started | Sep 11 11:09:38 AM UTC 24 |
| Finished | Sep 11 11:09:54 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264038972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1264038972 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.3131061564 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 61434110865 ps |
| CPU time | 3407.24 seconds |
| Started | Sep 11 11:08:03 AM UTC 24 |
| Finished | Sep 11 12:05:27 PM UTC 24 |
| Peak memory | 2099728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131061564 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.3131061564 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.179499573 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4847488529 ps |
| CPU time | 154.75 seconds |
| Started | Sep 11 11:08:16 AM UTC 24 |
| Finished | Sep 11 11:10:55 AM UTC 24 |
| Peak memory | 338516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179499573 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.179499573 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.2176767462 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 12917354676 ps |
| CPU time | 82.46 seconds |
| Started | Sep 11 11:07:54 AM UTC 24 |
| Finished | Sep 11 11:09:19 AM UTC 24 |
| Peak memory | 236064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176767462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2176767462 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.3023566202 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 213917858653 ps |
| CPU time | 2252.54 seconds |
| Started | Sep 11 11:10:16 AM UTC 24 |
| Finished | Sep 11 11:48:15 AM UTC 24 |
| Peak memory | 1169960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023566202 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3023566202 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.1972112458 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 23067232 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 11:12:41 AM UTC 24 |
| Finished | Sep 11 11:12:43 AM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972112458 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1972112458 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_app.3791391237 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6252549175 ps |
| CPU time | 125.41 seconds |
| Started | Sep 11 11:11:33 AM UTC 24 |
| Finished | Sep 11 11:13:41 AM UTC 24 |
| Peak memory | 291360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791391237 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3791391237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.1492823908 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 11800179741 ps |
| CPU time | 1227.45 seconds |
| Started | Sep 11 11:10:56 AM UTC 24 |
| Finished | Sep 11 11:31:37 AM UTC 24 |
| Peak memory | 254576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492823908 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1492823908 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.4158983404 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 21494674 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 11:12:34 AM UTC 24 |
| Finished | Sep 11 11:12:36 AM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158983404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4158983404 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.172959119 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 20825957 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 11:12:37 AM UTC 24 |
| Finished | Sep 11 11:12:39 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172959119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.172959119 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2924006170 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 31845992593 ps |
| CPU time | 340.88 seconds |
| Started | Sep 11 11:11:45 AM UTC 24 |
| Finished | Sep 11 11:17:31 AM UTC 24 |
| Peak memory | 451236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924006170 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2924006170 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_error.3866883572 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 971207167 ps |
| CPU time | 44.27 seconds |
| Started | Sep 11 11:12:14 AM UTC 24 |
| Finished | Sep 11 11:13:00 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866883572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3866883572 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.4091652861 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 13235079228 ps |
| CPU time | 17.69 seconds |
| Started | Sep 11 11:12:22 AM UTC 24 |
| Finished | Sep 11 11:12:41 AM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091652861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.4091652861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.2777978658 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 34162852 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 11:12:37 AM UTC 24 |
| Finished | Sep 11 11:12:40 AM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777978658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2777978658 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.878505280 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 97466044301 ps |
| CPU time | 2994.57 seconds |
| Started | Sep 11 11:10:41 AM UTC 24 |
| Finished | Sep 11 12:01:05 PM UTC 24 |
| Peak memory | 3664456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878505280 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.878505280 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.1131771063 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5738732513 ps |
| CPU time | 115.62 seconds |
| Started | Sep 11 11:10:42 AM UTC 24 |
| Finished | Sep 11 11:12:40 AM UTC 24 |
| Peak memory | 305760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131771063 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1131771063 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.910696657 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1477131580 ps |
| CPU time | 70.05 seconds |
| Started | Sep 11 11:10:21 AM UTC 24 |
| Finished | Sep 11 11:11:33 AM UTC 24 |
| Peak memory | 235912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910696657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.910696657 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.53871472 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 29359455433 ps |
| CPU time | 786.78 seconds |
| Started | Sep 11 11:12:40 AM UTC 24 |
| Finished | Sep 11 11:25:57 AM UTC 24 |
| Peak memory | 596908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53871472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.53871472 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.2515370518 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 16485674 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 11:14:00 AM UTC 24 |
| Finished | Sep 11 11:14:03 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515370518 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2515370518 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_app.484853699 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3391846443 ps |
| CPU time | 206.4 seconds |
| Started | Sep 11 11:13:01 AM UTC 24 |
| Finished | Sep 11 11:16:30 AM UTC 24 |
| Peak memory | 295528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484853699 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.484853699 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.3058159296 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 36458100614 ps |
| CPU time | 919.37 seconds |
| Started | Sep 11 11:12:58 AM UTC 24 |
| Finished | Sep 11 11:28:29 AM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058159296 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3058159296 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.842659466 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1422536041 ps |
| CPU time | 23.09 seconds |
| Started | Sep 11 11:13:42 AM UTC 24 |
| Finished | Sep 11 11:14:06 AM UTC 24 |
| Peak memory | 245176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842659466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.842659466 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.3498236468 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 74100097 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 11:13:55 AM UTC 24 |
| Finished | Sep 11 11:13:57 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498236468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3498236468 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.3958111993 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1030125641 ps |
| CPU time | 39.12 seconds |
| Started | Sep 11 11:13:14 AM UTC 24 |
| Finished | Sep 11 11:13:54 AM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958111993 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3958111993 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.2611135552 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2313614180 ps |
| CPU time | 16.73 seconds |
| Started | Sep 11 11:13:38 AM UTC 24 |
| Finished | Sep 11 11:13:56 AM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611135552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2611135552 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.2302522753 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 220100332 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 11:13:56 AM UTC 24 |
| Finished | Sep 11 11:13:59 AM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302522753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2302522753 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.2273535632 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 226134679089 ps |
| CPU time | 2673.62 seconds |
| Started | Sep 11 11:12:41 AM UTC 24 |
| Finished | Sep 11 11:57:44 AM UTC 24 |
| Peak memory | 2779812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273535632 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.2273535632 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.3940176324 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 18640692628 ps |
| CPU time | 638.89 seconds |
| Started | Sep 11 11:12:44 AM UTC 24 |
| Finished | Sep 11 11:23:31 AM UTC 24 |
| Peak memory | 653904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940176324 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3940176324 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.3072199656 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1054718706 ps |
| CPU time | 53.88 seconds |
| Started | Sep 11 11:12:41 AM UTC 24 |
| Finished | Sep 11 11:13:37 AM UTC 24 |
| Peak memory | 234096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072199656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3072199656 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.335513998 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 45859978282 ps |
| CPU time | 1344.3 seconds |
| Started | Sep 11 11:13:58 AM UTC 24 |
| Finished | Sep 11 11:36:38 AM UTC 24 |
| Peak memory | 1464940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335513998 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.335513998 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.3480689425 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 21396484 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 11:18:03 AM UTC 24 |
| Finished | Sep 11 11:18:05 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480689425 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3480689425 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_app.3063331024 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 9493465498 ps |
| CPU time | 351.62 seconds |
| Started | Sep 11 11:15:26 AM UTC 24 |
| Finished | Sep 11 11:21:23 AM UTC 24 |
| Peak memory | 332376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063331024 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3063331024 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.1758406528 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 49420021436 ps |
| CPU time | 860.31 seconds |
| Started | Sep 11 11:14:38 AM UTC 24 |
| Finished | Sep 11 11:29:08 AM UTC 24 |
| Peak memory | 250460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758406528 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1758406528 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3522226639 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 400375553 ps |
| CPU time | 27.89 seconds |
| Started | Sep 11 11:17:32 AM UTC 24 |
| Finished | Sep 11 11:18:02 AM UTC 24 |
| Peak memory | 235800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522226639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3522226639 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2966385390 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 28114334 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 11:17:36 AM UTC 24 |
| Finished | Sep 11 11:17:39 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966385390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2966385390 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1136979697 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 29862538166 ps |
| CPU time | 260.28 seconds |
| Started | Sep 11 11:16:25 AM UTC 24 |
| Finished | Sep 11 11:20:49 AM UTC 24 |
| Peak memory | 322080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136979697 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1136979697 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_error.2194954177 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4839164151 ps |
| CPU time | 385.95 seconds |
| Started | Sep 11 11:16:31 AM UTC 24 |
| Finished | Sep 11 11:23:02 AM UTC 24 |
| Peak memory | 371292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194954177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2194954177 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.70577697 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5849777113 ps |
| CPU time | 14.84 seconds |
| Started | Sep 11 11:17:19 AM UTC 24 |
| Finished | Sep 11 11:17:35 AM UTC 24 |
| Peak memory | 227932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70577697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.70577697 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.159494815 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 337806798 ps |
| CPU time | 1.99 seconds |
| Started | Sep 11 11:17:40 AM UTC 24 |
| Finished | Sep 11 11:17:43 AM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159494815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.159494815 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1459531802 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 28777648720 ps |
| CPU time | 3432.8 seconds |
| Started | Sep 11 11:14:07 AM UTC 24 |
| Finished | Sep 11 12:11:59 PM UTC 24 |
| Peak memory | 1892892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459531802 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1459531802 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.4055158063 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 10719369238 ps |
| CPU time | 521.02 seconds |
| Started | Sep 11 11:14:19 AM UTC 24 |
| Finished | Sep 11 11:23:07 AM UTC 24 |
| Peak memory | 514648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055158063 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.4055158063 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.2588658530 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1020843774 ps |
| CPU time | 32.36 seconds |
| Started | Sep 11 11:14:03 AM UTC 24 |
| Finished | Sep 11 11:14:37 AM UTC 24 |
| Peak memory | 236020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588658530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2588658530 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.2080631222 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 28591862012 ps |
| CPU time | 969.91 seconds |
| Started | Sep 11 11:17:44 AM UTC 24 |
| Finished | Sep 11 11:34:07 AM UTC 24 |
| Peak memory | 711568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080631222 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2080631222 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.765619709 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 15451698 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 10:33:43 AM UTC 24 |
| Finished | Sep 11 10:33:46 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765619709 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.765619709 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_app.2403449621 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 134807886930 ps |
| CPU time | 479.93 seconds |
| Started | Sep 11 10:33:16 AM UTC 24 |
| Finished | Sep 11 10:41:22 AM UTC 24 |
| Peak memory | 582156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403449621 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2403449621 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3314131975 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 17360913376 ps |
| CPU time | 153.27 seconds |
| Started | Sep 11 10:33:18 AM UTC 24 |
| Finished | Sep 11 10:35:54 AM UTC 24 |
| Peak memory | 307736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314131975 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3314131975 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.3747549405 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 40640890178 ps |
| CPU time | 452.71 seconds |
| Started | Sep 11 10:32:42 AM UTC 24 |
| Finished | Sep 11 10:40:20 AM UTC 24 |
| Peak memory | 250396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747549405 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3747549405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1341801161 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 18783547 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 10:33:31 AM UTC 24 |
| Finished | Sep 11 10:33:33 AM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341801161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1341801161 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.1316237534 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 137592332 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 10:33:34 AM UTC 24 |
| Finished | Sep 11 10:33:36 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316237534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1316237534 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3770718742 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 35710963723 ps |
| CPU time | 565.01 seconds |
| Started | Sep 11 10:33:18 AM UTC 24 |
| Finished | Sep 11 10:42:51 AM UTC 24 |
| Peak memory | 365152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770718742 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3770718742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_error.3847919970 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6864913283 ps |
| CPU time | 203.79 seconds |
| Started | Sep 11 10:33:27 AM UTC 24 |
| Finished | Sep 11 10:36:54 AM UTC 24 |
| Peak memory | 399964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847919970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3847919970 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.3487765514 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1579898600 ps |
| CPU time | 13.32 seconds |
| Started | Sep 11 10:33:28 AM UTC 24 |
| Finished | Sep 11 10:33:42 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487765514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3487765514 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.2471484261 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 136482132544 ps |
| CPU time | 2113.37 seconds |
| Started | Sep 11 10:32:41 AM UTC 24 |
| Finished | Sep 11 11:08:16 AM UTC 24 |
| Peak memory | 2765336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471484261 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.2471484261 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.1863548931 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 23829360648 ps |
| CPU time | 177.26 seconds |
| Started | Sep 11 10:33:18 AM UTC 24 |
| Finished | Sep 11 10:36:19 AM UTC 24 |
| Peak memory | 347052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863548931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1863548931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.2719024441 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5479467322 ps |
| CPU time | 106.18 seconds |
| Started | Sep 11 10:33:41 AM UTC 24 |
| Finished | Sep 11 10:35:30 AM UTC 24 |
| Peak memory | 288604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719024441 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2719024441 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.1535517035 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 7435005488 ps |
| CPU time | 113.24 seconds |
| Started | Sep 11 10:32:41 AM UTC 24 |
| Finished | Sep 11 10:34:37 AM UTC 24 |
| Peak memory | 264792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535517035 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1535517035 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.3077421076 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1612277657 ps |
| CPU time | 53.85 seconds |
| Started | Sep 11 10:32:20 AM UTC 24 |
| Finished | Sep 11 10:33:16 AM UTC 24 |
| Peak memory | 235916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077421076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3077421076 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.2483879030 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 63752892256 ps |
| CPU time | 1901.71 seconds |
| Started | Sep 11 10:33:38 AM UTC 24 |
| Finished | Sep 11 11:05:40 AM UTC 24 |
| Peak memory | 1201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483879030 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2483879030 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.676257737 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 372183746 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 10:33:12 AM UTC 24 |
| Finished | Sep 11 10:33:18 AM UTC 24 |
| Peak memory | 230072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676257737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.676257737 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.721646979 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 147778688 ps |
| CPU time | 3.33 seconds |
| Started | Sep 11 10:33:13 AM UTC 24 |
| Finished | Sep 11 10:33:17 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721646979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.721646979 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.3800501844 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5950518612 ps |
| CPU time | 54.14 seconds |
| Started | Sep 11 10:32:42 AM UTC 24 |
| Finished | Sep 11 10:33:37 AM UTC 24 |
| Peak memory | 235896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800501844 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3800501844 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.210372418 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 169783347474 ps |
| CPU time | 2777.6 seconds |
| Started | Sep 11 10:32:42 AM UTC 24 |
| Finished | Sep 11 11:19:30 AM UTC 24 |
| Peak memory | 2998716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210372418 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.210372418 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3291721035 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 6860730385 ps |
| CPU time | 28.91 seconds |
| Started | Sep 11 10:32:42 AM UTC 24 |
| Finished | Sep 11 10:33:12 AM UTC 24 |
| Peak memory | 242132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291721035 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3291721035 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.678307120 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 9483196922 ps |
| CPU time | 1078.72 seconds |
| Started | Sep 11 10:32:45 AM UTC 24 |
| Finished | Sep 11 10:50:56 AM UTC 24 |
| Peak memory | 702916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678307120 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.678307120 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1999968917 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 13412470514 ps |
| CPU time | 260.01 seconds |
| Started | Sep 11 10:32:48 AM UTC 24 |
| Finished | Sep 11 10:37:12 AM UTC 24 |
| Peak memory | 285116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999968917 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1999968917 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.3182243436 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 69257632243 ps |
| CPU time | 2102.83 seconds |
| Started | Sep 11 10:33:03 AM UTC 24 |
| Finished | Sep 11 11:08:31 AM UTC 24 |
| Peak memory | 1143232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182243436 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3182243436 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.3041276301 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 44255102 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 11:21:10 AM UTC 24 |
| Finished | Sep 11 11:21:12 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041276301 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3041276301 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_app.3475792899 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 7459290770 ps |
| CPU time | 269.76 seconds |
| Started | Sep 11 11:19:31 AM UTC 24 |
| Finished | Sep 11 11:24:07 AM UTC 24 |
| Peak memory | 313888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475792899 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3475792899 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.4137596926 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3187628235 ps |
| CPU time | 164.29 seconds |
| Started | Sep 11 11:19:14 AM UTC 24 |
| Finished | Sep 11 11:22:01 AM UTC 24 |
| Peak memory | 248336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137596926 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.4137596926 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2972899822 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2048716423 ps |
| CPU time | 56.69 seconds |
| Started | Sep 11 11:19:33 AM UTC 24 |
| Finished | Sep 11 11:20:32 AM UTC 24 |
| Peak memory | 274916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972899822 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2972899822 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_error.3356378895 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 43986538334 ps |
| CPU time | 725.39 seconds |
| Started | Sep 11 11:20:33 AM UTC 24 |
| Finished | Sep 11 11:32:48 AM UTC 24 |
| Peak memory | 698972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356378895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3356378895 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.4060027987 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4998037901 ps |
| CPU time | 18.6 seconds |
| Started | Sep 11 11:20:50 AM UTC 24 |
| Finished | Sep 11 11:21:10 AM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060027987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.4060027987 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.2173113991 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 107841887 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 11:20:54 AM UTC 24 |
| Finished | Sep 11 11:20:57 AM UTC 24 |
| Peak memory | 231640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173113991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2173113991 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2632785231 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 57690546129 ps |
| CPU time | 497.43 seconds |
| Started | Sep 11 11:18:58 AM UTC 24 |
| Finished | Sep 11 11:27:22 AM UTC 24 |
| Peak memory | 741888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632785231 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2632785231 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.21193945 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 39955240635 ps |
| CPU time | 470.31 seconds |
| Started | Sep 11 11:19:02 AM UTC 24 |
| Finished | Sep 11 11:26:59 AM UTC 24 |
| Peak memory | 522848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21193945 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.21193945 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.3147767234 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3302335086 ps |
| CPU time | 66.09 seconds |
| Started | Sep 11 11:18:06 AM UTC 24 |
| Finished | Sep 11 11:19:14 AM UTC 24 |
| Peak memory | 236172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147767234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3147767234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.2627272755 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 180652912409 ps |
| CPU time | 1508.96 seconds |
| Started | Sep 11 11:20:58 AM UTC 24 |
| Finished | Sep 11 11:46:25 AM UTC 24 |
| Peak memory | 496540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627272755 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2627272755 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.3633524331 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 26015914 ps |
| CPU time | 1 seconds |
| Started | Sep 11 11:23:16 AM UTC 24 |
| Finished | Sep 11 11:23:18 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633524331 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3633524331 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_app.3814075644 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 7839694186 ps |
| CPU time | 134.89 seconds |
| Started | Sep 11 11:22:03 AM UTC 24 |
| Finished | Sep 11 11:24:20 AM UTC 24 |
| Peak memory | 272928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814075644 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3814075644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.2517992723 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 20742159284 ps |
| CPU time | 303.84 seconds |
| Started | Sep 11 11:22:40 AM UTC 24 |
| Finished | Sep 11 11:27:48 AM UTC 24 |
| Peak memory | 324196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517992723 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2517992723 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_error.927548931 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2744610879 ps |
| CPU time | 106.56 seconds |
| Started | Sep 11 11:22:51 AM UTC 24 |
| Finished | Sep 11 11:24:40 AM UTC 24 |
| Peak memory | 305804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927548931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.927548931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.486837593 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5873316932 ps |
| CPU time | 11.26 seconds |
| Started | Sep 11 11:23:03 AM UTC 24 |
| Finished | Sep 11 11:23:15 AM UTC 24 |
| Peak memory | 229980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486837593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.486837593 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.149540495 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 10322397513 ps |
| CPU time | 396.46 seconds |
| Started | Sep 11 11:21:14 AM UTC 24 |
| Finished | Sep 11 11:27:56 AM UTC 24 |
| Peak memory | 590372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149540495 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.149540495 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.4019692800 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4079868623 ps |
| CPU time | 74.42 seconds |
| Started | Sep 11 11:21:23 AM UTC 24 |
| Finished | Sep 11 11:22:39 AM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019692800 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.4019692800 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.2086404097 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 10212171382 ps |
| CPU time | 94.82 seconds |
| Started | Sep 11 11:21:13 AM UTC 24 |
| Finished | Sep 11 11:22:50 AM UTC 24 |
| Peak memory | 236068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086404097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2086404097 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.4084998917 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 107550168191 ps |
| CPU time | 798.33 seconds |
| Started | Sep 11 11:23:12 AM UTC 24 |
| Finished | Sep 11 11:36:40 AM UTC 24 |
| Peak memory | 484264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084998917 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.4084998917 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.2704040127 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 26786423 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 11:24:40 AM UTC 24 |
| Finished | Sep 11 11:24:43 AM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704040127 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2704040127 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_app.2822459719 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 58588666190 ps |
| CPU time | 412.37 seconds |
| Started | Sep 11 11:24:08 AM UTC 24 |
| Finished | Sep 11 11:31:06 AM UTC 24 |
| Peak memory | 543328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822459719 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2822459719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.415519391 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 14198320205 ps |
| CPU time | 1352.53 seconds |
| Started | Sep 11 11:24:07 AM UTC 24 |
| Finished | Sep 11 11:46:55 AM UTC 24 |
| Peak memory | 254556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415519391 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.415519391 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1478230876 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 109664338 ps |
| CPU time | 4.83 seconds |
| Started | Sep 11 11:24:21 AM UTC 24 |
| Finished | Sep 11 11:24:27 AM UTC 24 |
| Peak memory | 234032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478230876 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1478230876 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_error.3170323691 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 12763309565 ps |
| CPU time | 153.32 seconds |
| Started | Sep 11 11:24:28 AM UTC 24 |
| Finished | Sep 11 11:27:04 AM UTC 24 |
| Peak memory | 322144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170323691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3170323691 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.1719119600 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 7746259543 ps |
| CPU time | 17.38 seconds |
| Started | Sep 11 11:24:29 AM UTC 24 |
| Finished | Sep 11 11:24:48 AM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719119600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1719119600 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.3672460531 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 87651261 ps |
| CPU time | 1.93 seconds |
| Started | Sep 11 11:24:32 AM UTC 24 |
| Finished | Sep 11 11:24:35 AM UTC 24 |
| Peak memory | 231640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672460531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3672460531 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.877330219 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 9785397280 ps |
| CPU time | 1145.46 seconds |
| Started | Sep 11 11:23:22 AM UTC 24 |
| Finished | Sep 11 11:42:41 AM UTC 24 |
| Peak memory | 795236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877330219 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.877330219 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.3009427085 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 53841037255 ps |
| CPU time | 437.5 seconds |
| Started | Sep 11 11:23:32 AM UTC 24 |
| Finished | Sep 11 11:30:56 AM UTC 24 |
| Peak memory | 559712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009427085 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3009427085 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.1709676447 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4092543506 ps |
| CPU time | 44.98 seconds |
| Started | Sep 11 11:23:19 AM UTC 24 |
| Finished | Sep 11 11:24:06 AM UTC 24 |
| Peak memory | 236132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709676447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1709676447 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.4279401149 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 113787190312 ps |
| CPU time | 1032.46 seconds |
| Started | Sep 11 11:24:36 AM UTC 24 |
| Finished | Sep 11 11:42:01 AM UTC 24 |
| Peak memory | 783280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279401149 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.4279401149 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.1361009423 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 30529803 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 11:27:43 AM UTC 24 |
| Finished | Sep 11 11:27:45 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361009423 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1361009423 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_app.1101634379 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3236622743 ps |
| CPU time | 89.51 seconds |
| Started | Sep 11 11:26:33 AM UTC 24 |
| Finished | Sep 11 11:28:05 AM UTC 24 |
| Peak memory | 285272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101634379 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1101634379 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.2788965023 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 14653485522 ps |
| CPU time | 1740.36 seconds |
| Started | Sep 11 11:25:58 AM UTC 24 |
| Finished | Sep 11 11:55:19 AM UTC 24 |
| Peak memory | 256680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788965023 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2788965023 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.2222748593 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 4066155977 ps |
| CPU time | 35.34 seconds |
| Started | Sep 11 11:27:00 AM UTC 24 |
| Finished | Sep 11 11:27:37 AM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222748593 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2222748593 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_error.2209040462 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2963655523 ps |
| CPU time | 257.34 seconds |
| Started | Sep 11 11:27:04 AM UTC 24 |
| Finished | Sep 11 11:31:26 AM UTC 24 |
| Peak memory | 318048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209040462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2209040462 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.452183007 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1965251282 ps |
| CPU time | 18.63 seconds |
| Started | Sep 11 11:27:22 AM UTC 24 |
| Finished | Sep 11 11:27:42 AM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452183007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.452183007 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.2345496578 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 41774083 ps |
| CPU time | 1.7 seconds |
| Started | Sep 11 11:27:38 AM UTC 24 |
| Finished | Sep 11 11:27:40 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345496578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2345496578 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1493052158 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 47735743545 ps |
| CPU time | 1190.22 seconds |
| Started | Sep 11 11:24:48 AM UTC 24 |
| Finished | Sep 11 11:44:52 AM UTC 24 |
| Peak memory | 948760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493052158 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1493052158 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.541737046 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 11932970065 ps |
| CPU time | 294.55 seconds |
| Started | Sep 11 11:24:59 AM UTC 24 |
| Finished | Sep 11 11:29:58 AM UTC 24 |
| Peak memory | 455252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541737046 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.541737046 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.65262587 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 7935039229 ps |
| CPU time | 105.88 seconds |
| Started | Sep 11 11:24:43 AM UTC 24 |
| Finished | Sep 11 11:26:32 AM UTC 24 |
| Peak memory | 236064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65262587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.65262587 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.1078167172 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 70123515754 ps |
| CPU time | 2174.42 seconds |
| Started | Sep 11 11:27:41 AM UTC 24 |
| Finished | Sep 11 12:04:19 PM UTC 24 |
| Peak memory | 1319456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078167172 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1078167172 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.3476138290 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 17990884 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 11:30:00 AM UTC 24 |
| Finished | Sep 11 11:30:02 AM UTC 24 |
| Peak memory | 227000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476138290 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3476138290 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_app.3519782430 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5607814572 ps |
| CPU time | 161.58 seconds |
| Started | Sep 11 11:28:25 AM UTC 24 |
| Finished | Sep 11 11:31:10 AM UTC 24 |
| Peak memory | 320092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519782430 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3519782430 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.3932333527 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 53480206204 ps |
| CPU time | 1527.71 seconds |
| Started | Sep 11 11:28:06 AM UTC 24 |
| Finished | Sep 11 11:53:52 AM UTC 24 |
| Peak memory | 256628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932333527 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3932333527 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.4289770023 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 8086019612 ps |
| CPU time | 53.99 seconds |
| Started | Sep 11 11:28:29 AM UTC 24 |
| Finished | Sep 11 11:29:25 AM UTC 24 |
| Peak memory | 260672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289770023 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.4289770023 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_error.1763744040 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 21302296233 ps |
| CPU time | 553.21 seconds |
| Started | Sep 11 11:29:09 AM UTC 24 |
| Finished | Sep 11 11:38:30 AM UTC 24 |
| Peak memory | 666272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763744040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1763744040 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.1887182679 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1516699733 ps |
| CPU time | 15.9 seconds |
| Started | Sep 11 11:29:27 AM UTC 24 |
| Finished | Sep 11 11:29:44 AM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887182679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1887182679 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.1569197016 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 15162273690 ps |
| CPU time | 133.42 seconds |
| Started | Sep 11 11:27:49 AM UTC 24 |
| Finished | Sep 11 11:30:05 AM UTC 24 |
| Peak memory | 393812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569197016 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.1569197016 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.1404876694 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 14165370609 ps |
| CPU time | 643.55 seconds |
| Started | Sep 11 11:27:57 AM UTC 24 |
| Finished | Sep 11 11:38:49 AM UTC 24 |
| Peak memory | 596576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404876694 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1404876694 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.1712164048 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1885937702 ps |
| CPU time | 36.72 seconds |
| Started | Sep 11 11:27:46 AM UTC 24 |
| Finished | Sep 11 11:28:24 AM UTC 24 |
| Peak memory | 235940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712164048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1712164048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.987247299 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 154259264197 ps |
| CPU time | 1658.07 seconds |
| Started | Sep 11 11:29:49 AM UTC 24 |
| Finished | Sep 11 11:57:45 AM UTC 24 |
| Peak memory | 406432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987247299 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.987247299 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.309703791 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 16444900 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 11:31:42 AM UTC 24 |
| Finished | Sep 11 11:31:44 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309703791 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.309703791 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_app.3834267208 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3274438046 ps |
| CPU time | 184.22 seconds |
| Started | Sep 11 11:30:57 AM UTC 24 |
| Finished | Sep 11 11:34:05 AM UTC 24 |
| Peak memory | 289304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834267208 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3834267208 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.2805667260 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 8623403504 ps |
| CPU time | 361.46 seconds |
| Started | Sep 11 11:30:40 AM UTC 24 |
| Finished | Sep 11 11:36:47 AM UTC 24 |
| Peak memory | 246368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805667260 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2805667260 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.1070675964 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 14390826237 ps |
| CPU time | 232.37 seconds |
| Started | Sep 11 11:31:06 AM UTC 24 |
| Finished | Sep 11 11:35:03 AM UTC 24 |
| Peak memory | 295520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070675964 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1070675964 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_error.3022622508 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 8720017539 ps |
| CPU time | 232.29 seconds |
| Started | Sep 11 11:31:10 AM UTC 24 |
| Finished | Sep 11 11:35:06 AM UTC 24 |
| Peak memory | 395808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022622508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3022622508 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.3851937712 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2897507940 ps |
| CPU time | 9.72 seconds |
| Started | Sep 11 11:31:27 AM UTC 24 |
| Finished | Sep 11 11:31:38 AM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851937712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3851937712 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.1322811850 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 28792649 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 11:31:38 AM UTC 24 |
| Finished | Sep 11 11:31:41 AM UTC 24 |
| Peak memory | 233600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322811850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1322811850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3379650304 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 398242818110 ps |
| CPU time | 4901.61 seconds |
| Started | Sep 11 11:30:06 AM UTC 24 |
| Finished | Sep 11 12:52:44 PM UTC 24 |
| Peak memory | 4412040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379650304 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3379650304 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.1285457758 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1933611299 ps |
| CPU time | 84.53 seconds |
| Started | Sep 11 11:30:25 AM UTC 24 |
| Finished | Sep 11 11:31:52 AM UTC 24 |
| Peak memory | 258488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285457758 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1285457758 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.1667912146 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2113729797 ps |
| CPU time | 35.01 seconds |
| Started | Sep 11 11:30:03 AM UTC 24 |
| Finished | Sep 11 11:30:39 AM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667912146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1667912146 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.263720975 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 12519957623 ps |
| CPU time | 1098.49 seconds |
| Started | Sep 11 11:31:39 AM UTC 24 |
| Finished | Sep 11 11:50:11 AM UTC 24 |
| Peak memory | 390068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263720975 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.263720975 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.2452561432 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 166184444 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 11:34:06 AM UTC 24 |
| Finished | Sep 11 11:34:08 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452561432 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2452561432 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_app.246945890 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 28386504409 ps |
| CPU time | 197.05 seconds |
| Started | Sep 11 11:32:48 AM UTC 24 |
| Finished | Sep 11 11:36:08 AM UTC 24 |
| Peak memory | 285264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246945890 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.246945890 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.2432813294 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 9734077634 ps |
| CPU time | 946.78 seconds |
| Started | Sep 11 11:32:27 AM UTC 24 |
| Finished | Sep 11 11:48:25 AM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432813294 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2432813294 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2042969432 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 26017000366 ps |
| CPU time | 168.93 seconds |
| Started | Sep 11 11:32:49 AM UTC 24 |
| Finished | Sep 11 11:35:41 AM UTC 24 |
| Peak memory | 336392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042969432 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2042969432 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_error.1039137347 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 31930564465 ps |
| CPU time | 225.36 seconds |
| Started | Sep 11 11:32:57 AM UTC 24 |
| Finished | Sep 11 11:36:46 AM UTC 24 |
| Peak memory | 373336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039137347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1039137347 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.3496321326 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 6566531608 ps |
| CPU time | 12.84 seconds |
| Started | Sep 11 11:33:19 AM UTC 24 |
| Finished | Sep 11 11:33:33 AM UTC 24 |
| Peak memory | 230156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496321326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3496321326 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.1587015693 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 158112078 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 11:33:34 AM UTC 24 |
| Finished | Sep 11 11:33:38 AM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587015693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1587015693 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3379097174 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 22865703900 ps |
| CPU time | 2908.28 seconds |
| Started | Sep 11 11:31:53 AM UTC 24 |
| Finished | Sep 11 12:20:54 PM UTC 24 |
| Peak memory | 1616400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379097174 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3379097174 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.3264421201 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 30948253508 ps |
| CPU time | 383.05 seconds |
| Started | Sep 11 11:32:02 AM UTC 24 |
| Finished | Sep 11 11:38:30 AM UTC 24 |
| Peak memory | 471584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264421201 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3264421201 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.1011598062 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 14673559903 ps |
| CPU time | 39.86 seconds |
| Started | Sep 11 11:31:45 AM UTC 24 |
| Finished | Sep 11 11:32:26 AM UTC 24 |
| Peak memory | 236128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011598062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1011598062 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.2433380784 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 24410012202 ps |
| CPU time | 609.43 seconds |
| Started | Sep 11 11:33:38 AM UTC 24 |
| Finished | Sep 11 11:43:55 AM UTC 24 |
| Peak memory | 987680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433380784 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2433380784 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.3570448895 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 45834646 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 11:36:39 AM UTC 24 |
| Finished | Sep 11 11:36:42 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570448895 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3570448895 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_app.881085434 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 46034366165 ps |
| CPU time | 245.61 seconds |
| Started | Sep 11 11:35:03 AM UTC 24 |
| Finished | Sep 11 11:39:12 AM UTC 24 |
| Peak memory | 453216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881085434 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.881085434 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.2152039769 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 26732314742 ps |
| CPU time | 721.5 seconds |
| Started | Sep 11 11:34:52 AM UTC 24 |
| Finished | Sep 11 11:47:03 AM UTC 24 |
| Peak memory | 248416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152039769 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2152039769 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.221650535 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 14421774281 ps |
| CPU time | 156.03 seconds |
| Started | Sep 11 11:35:08 AM UTC 24 |
| Finished | Sep 11 11:37:46 AM UTC 24 |
| Peak memory | 268956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221650535 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.221650535 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_error.169379063 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 113420261517 ps |
| CPU time | 271.48 seconds |
| Started | Sep 11 11:35:42 AM UTC 24 |
| Finished | Sep 11 11:40:17 AM UTC 24 |
| Peak memory | 354904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169379063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.169379063 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.4123967820 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 990333022 ps |
| CPU time | 7.27 seconds |
| Started | Sep 11 11:36:09 AM UTC 24 |
| Finished | Sep 11 11:36:17 AM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123967820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.4123967820 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.1423376005 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 67859952 ps |
| CPU time | 2.41 seconds |
| Started | Sep 11 11:36:18 AM UTC 24 |
| Finished | Sep 11 11:36:22 AM UTC 24 |
| Peak memory | 232056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423376005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1423376005 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.991804697 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 35888895009 ps |
| CPU time | 1420.93 seconds |
| Started | Sep 11 11:34:09 AM UTC 24 |
| Finished | Sep 11 11:58:06 AM UTC 24 |
| Peak memory | 1907304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991804697 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.991804697 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.1050902279 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 4302957069 ps |
| CPU time | 309.39 seconds |
| Started | Sep 11 11:34:45 AM UTC 24 |
| Finished | Sep 11 11:39:59 AM UTC 24 |
| Peak memory | 344736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050902279 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1050902279 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.4273457627 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 4448597292 ps |
| CPU time | 41.85 seconds |
| Started | Sep 11 11:34:08 AM UTC 24 |
| Finished | Sep 11 11:34:51 AM UTC 24 |
| Peak memory | 236124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273457627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.4273457627 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.2076795241 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 191800722832 ps |
| CPU time | 2960.3 seconds |
| Started | Sep 11 11:36:22 AM UTC 24 |
| Finished | Sep 11 12:26:16 PM UTC 24 |
| Peak memory | 2816944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076795241 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2076795241 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.433172605 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 16621267 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 11:38:31 AM UTC 24 |
| Finished | Sep 11 11:38:33 AM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433172605 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.433172605 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_app.3944288703 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3020058455 ps |
| CPU time | 23.45 seconds |
| Started | Sep 11 11:37:04 AM UTC 24 |
| Finished | Sep 11 11:37:29 AM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944288703 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3944288703 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.2118686723 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 14722091666 ps |
| CPU time | 864.52 seconds |
| Started | Sep 11 11:36:48 AM UTC 24 |
| Finished | Sep 11 11:51:23 AM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118686723 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2118686723 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.1392249858 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 15294351784 ps |
| CPU time | 394.62 seconds |
| Started | Sep 11 11:37:21 AM UTC 24 |
| Finished | Sep 11 11:44:01 AM UTC 24 |
| Peak memory | 526916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392249858 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1392249858 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_error.50555754 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2815888975 ps |
| CPU time | 108.37 seconds |
| Started | Sep 11 11:37:29 AM UTC 24 |
| Finished | Sep 11 11:39:20 AM UTC 24 |
| Peak memory | 311900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50555754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.50555754 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.3777945785 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2706621011 ps |
| CPU time | 5.51 seconds |
| Started | Sep 11 11:37:48 AM UTC 24 |
| Finished | Sep 11 11:37:54 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777945785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3777945785 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.499528478 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2468913805 ps |
| CPU time | 56.42 seconds |
| Started | Sep 11 11:37:55 AM UTC 24 |
| Finished | Sep 11 11:38:53 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499528478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.499528478 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.3387146228 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 787214053401 ps |
| CPU time | 4462.74 seconds |
| Started | Sep 11 11:36:43 AM UTC 24 |
| Finished | Sep 11 12:51:56 PM UTC 24 |
| Peak memory | 3531356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387146228 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.3387146228 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.1767549772 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 37349567280 ps |
| CPU time | 468.39 seconds |
| Started | Sep 11 11:36:47 AM UTC 24 |
| Finished | Sep 11 11:44:41 AM UTC 24 |
| Peak memory | 641696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767549772 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1767549772 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.3179968062 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2119704520 ps |
| CPU time | 38.38 seconds |
| Started | Sep 11 11:36:41 AM UTC 24 |
| Finished | Sep 11 11:37:20 AM UTC 24 |
| Peak memory | 232108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179968062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3179968062 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.2845833256 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 333708072824 ps |
| CPU time | 2797.02 seconds |
| Started | Sep 11 11:38:31 AM UTC 24 |
| Finished | Sep 11 12:25:39 PM UTC 24 |
| Peak memory | 1350544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845833256 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2845833256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.813271275 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 20094398 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 11:40:48 AM UTC 24 |
| Finished | Sep 11 11:40:50 AM UTC 24 |
| Peak memory | 227004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813271275 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.813271275 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_app.603949553 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 46037714883 ps |
| CPU time | 402.56 seconds |
| Started | Sep 11 11:39:21 AM UTC 24 |
| Finished | Sep 11 11:46:09 AM UTC 24 |
| Peak memory | 463384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603949553 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.603949553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.3490833623 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 695119313 ps |
| CPU time | 90.24 seconds |
| Started | Sep 11 11:39:14 AM UTC 24 |
| Finished | Sep 11 11:40:46 AM UTC 24 |
| Peak memory | 235996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490833623 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3490833623 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.2722766762 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 6085879858 ps |
| CPU time | 181.35 seconds |
| Started | Sep 11 11:39:39 AM UTC 24 |
| Finished | Sep 11 11:42:44 AM UTC 24 |
| Peak memory | 322140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722766762 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2722766762 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_error.1121232261 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2045173591 ps |
| CPU time | 179.91 seconds |
| Started | Sep 11 11:40:00 AM UTC 24 |
| Finished | Sep 11 11:43:03 AM UTC 24 |
| Peak memory | 295408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121232261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1121232261 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.3694506768 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1021424908 ps |
| CPU time | 14.97 seconds |
| Started | Sep 11 11:40:18 AM UTC 24 |
| Finished | Sep 11 11:40:35 AM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694506768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3694506768 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.253567911 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 55813558 ps |
| CPU time | 2.31 seconds |
| Started | Sep 11 11:40:36 AM UTC 24 |
| Finished | Sep 11 11:40:39 AM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253567911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.253567911 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.976227331 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 21431949581 ps |
| CPU time | 394.28 seconds |
| Started | Sep 11 11:38:49 AM UTC 24 |
| Finished | Sep 11 11:45:30 AM UTC 24 |
| Peak memory | 703012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976227331 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.976227331 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.2635927365 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1696475827 ps |
| CPU time | 126.7 seconds |
| Started | Sep 11 11:38:54 AM UTC 24 |
| Finished | Sep 11 11:41:03 AM UTC 24 |
| Peak memory | 279000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635927365 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2635927365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.1451455750 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1805969821 ps |
| CPU time | 62.1 seconds |
| Started | Sep 11 11:38:34 AM UTC 24 |
| Finished | Sep 11 11:39:38 AM UTC 24 |
| Peak memory | 236020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451455750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1451455750 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.4167680355 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 80203807448 ps |
| CPU time | 1556.49 seconds |
| Started | Sep 11 11:40:40 AM UTC 24 |
| Finished | Sep 11 12:06:54 PM UTC 24 |
| Peak memory | 908144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167680355 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.4167680355 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.484953597 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 43034775 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 10:36:20 AM UTC 24 |
| Finished | Sep 11 10:36:22 AM UTC 24 |
| Peak memory | 226588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484953597 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.484953597 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_app.4187114529 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4281947663 ps |
| CPU time | 121.91 seconds |
| Started | Sep 11 10:34:57 AM UTC 24 |
| Finished | Sep 11 10:37:01 AM UTC 24 |
| Peak memory | 303716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187114529 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.4187114529 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3845484890 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2922085327 ps |
| CPU time | 53.93 seconds |
| Started | Sep 11 10:35:14 AM UTC 24 |
| Finished | Sep 11 10:36:09 AM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845484890 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3845484890 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.567372628 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 81132971203 ps |
| CPU time | 792.92 seconds |
| Started | Sep 11 10:34:11 AM UTC 24 |
| Finished | Sep 11 10:47:33 AM UTC 24 |
| Peak memory | 256612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567372628 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.567372628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2643820188 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1672172824 ps |
| CPU time | 20.14 seconds |
| Started | Sep 11 10:35:36 AM UTC 24 |
| Finished | Sep 11 10:35:58 AM UTC 24 |
| Peak memory | 235584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643820188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2643820188 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.4008066665 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 66997644 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 10:35:56 AM UTC 24 |
| Finished | Sep 11 10:35:58 AM UTC 24 |
| Peak memory | 225272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008066665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4008066665 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.1860907839 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 27422755111 ps |
| CPU time | 71.6 seconds |
| Started | Sep 11 10:35:59 AM UTC 24 |
| Finished | Sep 11 10:37:12 AM UTC 24 |
| Peak memory | 236136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860907839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1860907839 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.2868852021 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 7017538107 ps |
| CPU time | 126.73 seconds |
| Started | Sep 11 10:35:14 AM UTC 24 |
| Finished | Sep 11 10:37:23 AM UTC 24 |
| Peak memory | 273060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868852021 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2868852021 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_error.567659322 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3864342296 ps |
| CPU time | 96.5 seconds |
| Started | Sep 11 10:35:29 AM UTC 24 |
| Finished | Sep 11 10:37:08 AM UTC 24 |
| Peak memory | 326312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567659322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.567659322 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.2693053042 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 994654069 ps |
| CPU time | 4.06 seconds |
| Started | Sep 11 10:35:30 AM UTC 24 |
| Finished | Sep 11 10:35:35 AM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693053042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2693053042 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.3007835501 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 125484897796 ps |
| CPU time | 1410.89 seconds |
| Started | Sep 11 10:33:59 AM UTC 24 |
| Finished | Sep 11 10:57:46 AM UTC 24 |
| Peak memory | 1761868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007835501 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3007835501 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.3992641311 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 9783055395 ps |
| CPU time | 375.5 seconds |
| Started | Sep 11 10:35:19 AM UTC 24 |
| Finished | Sep 11 10:41:40 AM UTC 24 |
| Peak memory | 478044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992641311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3992641311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.3501300341 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 14529055038 ps |
| CPU time | 99 seconds |
| Started | Sep 11 10:36:14 AM UTC 24 |
| Finished | Sep 11 10:37:55 AM UTC 24 |
| Peak memory | 311080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501300341 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3501300341 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.3093491241 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 4728974437 ps |
| CPU time | 87.16 seconds |
| Started | Sep 11 10:34:00 AM UTC 24 |
| Finished | Sep 11 10:35:29 AM UTC 24 |
| Peak memory | 266760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093491241 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3093491241 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.498691302 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 6273992707 ps |
| CPU time | 52.7 seconds |
| Started | Sep 11 10:33:46 AM UTC 24 |
| Finished | Sep 11 10:34:41 AM UTC 24 |
| Peak memory | 236072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498691302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.498691302 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.1551279983 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 150816546 ps |
| CPU time | 4.59 seconds |
| Started | Sep 11 10:34:45 AM UTC 24 |
| Finished | Sep 11 10:34:50 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551279983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.1551279983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2793089197 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 292133082 ps |
| CPU time | 3.85 seconds |
| Started | Sep 11 10:34:51 AM UTC 24 |
| Finished | Sep 11 10:34:56 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793089197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2793089197 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1416590715 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4822827648 ps |
| CPU time | 48.84 seconds |
| Started | Sep 11 10:34:22 AM UTC 24 |
| Finished | Sep 11 10:35:13 AM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416590715 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1416590715 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3871091153 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13679040369 ps |
| CPU time | 45.27 seconds |
| Started | Sep 11 10:34:31 AM UTC 24 |
| Finished | Sep 11 10:35:18 AM UTC 24 |
| Peak memory | 258516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871091153 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3871091153 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2471152042 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 58599535230 ps |
| CPU time | 2141.43 seconds |
| Started | Sep 11 10:34:35 AM UTC 24 |
| Finished | Sep 11 11:10:41 AM UTC 24 |
| Peak memory | 2388412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471152042 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2471152042 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3193840550 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 939411712710 ps |
| CPU time | 1522.77 seconds |
| Started | Sep 11 10:34:37 AM UTC 24 |
| Finished | Sep 11 11:00:17 AM UTC 24 |
| Peak memory | 1722884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193840550 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3193840550 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3306133698 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 577550031588 ps |
| CPU time | 2959.42 seconds |
| Started | Sep 11 10:34:39 AM UTC 24 |
| Finished | Sep 11 11:24:31 AM UTC 24 |
| Peak memory | 3541452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306133698 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3306133698 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.1717173988 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 11736587654 ps |
| CPU time | 165.24 seconds |
| Started | Sep 11 10:34:42 AM UTC 24 |
| Finished | Sep 11 10:37:30 AM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717173988 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1717173988 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.3414281369 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 97662843 ps |
| CPU time | 1.47 seconds |
| Started | Sep 11 11:44:05 AM UTC 24 |
| Finished | Sep 11 11:44:08 AM UTC 24 |
| Peak memory | 225812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414281369 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3414281369 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_app.1854287944 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 28786888769 ps |
| CPU time | 239.47 seconds |
| Started | Sep 11 11:42:42 AM UTC 24 |
| Finished | Sep 11 11:46:45 AM UTC 24 |
| Peak memory | 385624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854287944 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1854287944 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.3430596336 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 14399188988 ps |
| CPU time | 1440.28 seconds |
| Started | Sep 11 11:42:03 AM UTC 24 |
| Finished | Sep 11 12:06:20 PM UTC 24 |
| Peak memory | 254496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430596336 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3430596336 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.348674976 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 25839826196 ps |
| CPU time | 114.27 seconds |
| Started | Sep 11 11:42:44 AM UTC 24 |
| Finished | Sep 11 11:44:41 AM UTC 24 |
| Peak memory | 317980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348674976 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.348674976 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_error.3343090019 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 36671741502 ps |
| CPU time | 506.02 seconds |
| Started | Sep 11 11:43:04 AM UTC 24 |
| Finished | Sep 11 11:51:37 AM UTC 24 |
| Peak memory | 606812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343090019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3343090019 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.3624367011 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 363340548 ps |
| CPU time | 2.1 seconds |
| Started | Sep 11 11:43:57 AM UTC 24 |
| Finished | Sep 11 11:44:00 AM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624367011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3624367011 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.1319294476 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 40559402 ps |
| CPU time | 2 seconds |
| Started | Sep 11 11:44:01 AM UTC 24 |
| Finished | Sep 11 11:44:04 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319294476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1319294476 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.993376738 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 162474635977 ps |
| CPU time | 3015.42 seconds |
| Started | Sep 11 11:41:03 AM UTC 24 |
| Finished | Sep 11 12:31:51 PM UTC 24 |
| Peak memory | 3367460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993376738 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.993376738 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.3068066142 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 28634888494 ps |
| CPU time | 187.22 seconds |
| Started | Sep 11 11:41:06 AM UTC 24 |
| Finished | Sep 11 11:44:17 AM UTC 24 |
| Peak memory | 346656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068066142 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3068066142 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.932931315 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 394536113 ps |
| CPU time | 13.34 seconds |
| Started | Sep 11 11:40:51 AM UTC 24 |
| Finished | Sep 11 11:41:06 AM UTC 24 |
| Peak memory | 235972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932931315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.932931315 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.3213665173 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 171118201322 ps |
| CPU time | 2406.56 seconds |
| Started | Sep 11 11:44:02 AM UTC 24 |
| Finished | Sep 11 12:24:34 PM UTC 24 |
| Peak memory | 1793012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213665173 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3213665173 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.3925825400 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 56451803 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 11:45:55 AM UTC 24 |
| Finished | Sep 11 11:45:57 AM UTC 24 |
| Peak memory | 224852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925825400 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3925825400 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_app.1613044614 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 8590121539 ps |
| CPU time | 328.65 seconds |
| Started | Sep 11 11:44:42 AM UTC 24 |
| Finished | Sep 11 11:50:15 AM UTC 24 |
| Peak memory | 316060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613044614 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1613044614 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.1682154240 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 11231244966 ps |
| CPU time | 416.06 seconds |
| Started | Sep 11 11:44:42 AM UTC 24 |
| Finished | Sep 11 11:51:43 AM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682154240 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1682154240 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.2738404022 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 27279429424 ps |
| CPU time | 184.57 seconds |
| Started | Sep 11 11:44:53 AM UTC 24 |
| Finished | Sep 11 11:48:01 AM UTC 24 |
| Peak memory | 291404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738404022 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2738404022 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_error.2804832331 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 6156983325 ps |
| CPU time | 47.01 seconds |
| Started | Sep 11 11:45:05 AM UTC 24 |
| Finished | Sep 11 11:45:54 AM UTC 24 |
| Peak memory | 279200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804832331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2804832331 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.292353672 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 823577513 ps |
| CPU time | 11.73 seconds |
| Started | Sep 11 11:45:30 AM UTC 24 |
| Finished | Sep 11 11:45:43 AM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292353672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.292353672 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.3873987971 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 33807111 ps |
| CPU time | 2.52 seconds |
| Started | Sep 11 11:45:44 AM UTC 24 |
| Finished | Sep 11 11:45:48 AM UTC 24 |
| Peak memory | 234168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873987971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3873987971 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.662648742 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 209213541204 ps |
| CPU time | 2281.67 seconds |
| Started | Sep 11 11:44:15 AM UTC 24 |
| Finished | Sep 11 12:22:41 PM UTC 24 |
| Peak memory | 2658956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662648742 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.662648742 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.175238543 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 10247798127 ps |
| CPU time | 226.25 seconds |
| Started | Sep 11 11:44:18 AM UTC 24 |
| Finished | Sep 11 11:48:07 AM UTC 24 |
| Peak memory | 303652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175238543 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.175238543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.369362908 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 5579088263 ps |
| CPU time | 52.61 seconds |
| Started | Sep 11 11:44:09 AM UTC 24 |
| Finished | Sep 11 11:45:04 AM UTC 24 |
| Peak memory | 236068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369362908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.369362908 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.1723010843 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 15691890313 ps |
| CPU time | 360.45 seconds |
| Started | Sep 11 11:45:49 AM UTC 24 |
| Finished | Sep 11 11:51:54 AM UTC 24 |
| Peak memory | 416632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723010843 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1723010843 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.1795688765 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 85737748 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 11:48:02 AM UTC 24 |
| Finished | Sep 11 11:48:04 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795688765 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1795688765 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_app.3145294044 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 12269130060 ps |
| CPU time | 335.27 seconds |
| Started | Sep 11 11:46:31 AM UTC 24 |
| Finished | Sep 11 11:52:11 AM UTC 24 |
| Peak memory | 494176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145294044 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3145294044 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.1593188223 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 67908988569 ps |
| CPU time | 1681.58 seconds |
| Started | Sep 11 11:46:26 AM UTC 24 |
| Finished | Sep 11 12:14:48 PM UTC 24 |
| Peak memory | 275108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593188223 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1593188223 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_error.2502709487 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 27570935980 ps |
| CPU time | 167.79 seconds |
| Started | Sep 11 11:46:56 AM UTC 24 |
| Finished | Sep 11 11:49:47 AM UTC 24 |
| Peak memory | 383584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502709487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2502709487 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.935937415 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3140220190 ps |
| CPU time | 10.12 seconds |
| Started | Sep 11 11:47:04 AM UTC 24 |
| Finished | Sep 11 11:47:15 AM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935937415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.935937415 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.2543007141 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 34007869 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 11:47:16 AM UTC 24 |
| Finished | Sep 11 11:47:19 AM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543007141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2543007141 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.42612589 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 105035033465 ps |
| CPU time | 1239.45 seconds |
| Started | Sep 11 11:46:03 AM UTC 24 |
| Finished | Sep 11 12:06:59 PM UTC 24 |
| Peak memory | 1589852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42612589 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.42612589 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.1086825037 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1561699787 ps |
| CPU time | 111.69 seconds |
| Started | Sep 11 11:46:10 AM UTC 24 |
| Finished | Sep 11 11:48:04 AM UTC 24 |
| Peak memory | 268768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086825037 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1086825037 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.2926873537 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 101027264 ps |
| CPU time | 2.88 seconds |
| Started | Sep 11 11:45:58 AM UTC 24 |
| Finished | Sep 11 11:46:02 AM UTC 24 |
| Peak memory | 232052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926873537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2926873537 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.2274755958 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 91714256085 ps |
| CPU time | 1042.77 seconds |
| Started | Sep 11 11:47:20 AM UTC 24 |
| Finished | Sep 11 12:04:56 PM UTC 24 |
| Peak memory | 383988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274755958 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2274755958 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.3473798761 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 35520790 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 11:50:17 AM UTC 24 |
| Finished | Sep 11 11:50:19 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473798761 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3473798761 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_app.2547185022 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 501506177 ps |
| CPU time | 16.35 seconds |
| Started | Sep 11 11:48:16 AM UTC 24 |
| Finished | Sep 11 11:48:34 AM UTC 24 |
| Peak memory | 244396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547185022 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2547185022 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.84424055 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 7479510395 ps |
| CPU time | 734.17 seconds |
| Started | Sep 11 11:48:11 AM UTC 24 |
| Finished | Sep 11 12:00:34 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84424055 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.84424055 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.1055421439 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 21181354188 ps |
| CPU time | 288.09 seconds |
| Started | Sep 11 11:48:25 AM UTC 24 |
| Finished | Sep 11 11:53:18 AM UTC 24 |
| Peak memory | 442916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055421439 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1055421439 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_error.3927539522 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 19102505646 ps |
| CPU time | 530.14 seconds |
| Started | Sep 11 11:48:35 AM UTC 24 |
| Finished | Sep 11 11:57:32 AM UTC 24 |
| Peak memory | 582176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927539522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3927539522 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.203329255 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 17546573843 ps |
| CPU time | 26.76 seconds |
| Started | Sep 11 11:49:48 AM UTC 24 |
| Finished | Sep 11 11:50:16 AM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203329255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.203329255 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.2575726136 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 57022621 ps |
| CPU time | 1.99 seconds |
| Started | Sep 11 11:50:11 AM UTC 24 |
| Finished | Sep 11 11:50:14 AM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575726136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2575726136 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.268695241 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 142068753118 ps |
| CPU time | 2130.23 seconds |
| Started | Sep 11 11:48:05 AM UTC 24 |
| Finished | Sep 11 12:23:59 PM UTC 24 |
| Peak memory | 2603616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268695241 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.268695241 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.3787061793 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 10033014838 ps |
| CPU time | 295.48 seconds |
| Started | Sep 11 11:48:08 AM UTC 24 |
| Finished | Sep 11 11:53:07 AM UTC 24 |
| Peak memory | 492060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787061793 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3787061793 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.2315612364 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 66211726 ps |
| CPU time | 4.27 seconds |
| Started | Sep 11 11:48:05 AM UTC 24 |
| Finished | Sep 11 11:48:10 AM UTC 24 |
| Peak memory | 235788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315612364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2315612364 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.1837161383 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2985182063 ps |
| CPU time | 22.56 seconds |
| Started | Sep 11 11:50:15 AM UTC 24 |
| Finished | Sep 11 11:50:39 AM UTC 24 |
| Peak memory | 248484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837161383 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1837161383 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.3979679829 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 17665557 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 11:51:57 AM UTC 24 |
| Finished | Sep 11 11:52:00 AM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979679829 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3979679829 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_app.884011490 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 384622218 ps |
| CPU time | 3.2 seconds |
| Started | Sep 11 11:51:11 AM UTC 24 |
| Finished | Sep 11 11:51:15 AM UTC 24 |
| Peak memory | 232052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884011490 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.884011490 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.3194771931 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 18567979922 ps |
| CPU time | 843.25 seconds |
| Started | Sep 11 11:51:05 AM UTC 24 |
| Finished | Sep 11 12:05:18 PM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194771931 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3194771931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2398376243 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 21710756737 ps |
| CPU time | 136.45 seconds |
| Started | Sep 11 11:51:16 AM UTC 24 |
| Finished | Sep 11 11:53:35 AM UTC 24 |
| Peak memory | 307728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398376243 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2398376243 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_error.73202106 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 13034246044 ps |
| CPU time | 375.46 seconds |
| Started | Sep 11 11:51:25 AM UTC 24 |
| Finished | Sep 11 11:57:45 AM UTC 24 |
| Peak memory | 535140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73202106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.73202106 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.179886445 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 4877547528 ps |
| CPU time | 17.36 seconds |
| Started | Sep 11 11:51:38 AM UTC 24 |
| Finished | Sep 11 11:51:56 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179886445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.179886445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.3635380824 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1981727415 ps |
| CPU time | 26.1 seconds |
| Started | Sep 11 11:51:44 AM UTC 24 |
| Finished | Sep 11 11:52:12 AM UTC 24 |
| Peak memory | 246292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635380824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3635380824 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.2599384259 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 337747827639 ps |
| CPU time | 2213.4 seconds |
| Started | Sep 11 11:50:20 AM UTC 24 |
| Finished | Sep 11 12:27:38 PM UTC 24 |
| Peak memory | 1243676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599384259 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.2599384259 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.753867532 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 12960423396 ps |
| CPU time | 416.25 seconds |
| Started | Sep 11 11:50:40 AM UTC 24 |
| Finished | Sep 11 11:57:42 AM UTC 24 |
| Peak memory | 580188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753867532 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.753867532 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.4209999362 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 4817773469 ps |
| CPU time | 45.54 seconds |
| Started | Sep 11 11:50:17 AM UTC 24 |
| Finished | Sep 11 11:51:04 AM UTC 24 |
| Peak memory | 236068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209999362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.4209999362 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.1937576522 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 27071449116 ps |
| CPU time | 673.22 seconds |
| Started | Sep 11 11:51:55 AM UTC 24 |
| Finished | Sep 11 12:03:17 PM UTC 24 |
| Peak memory | 611240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937576522 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1937576522 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.1528238650 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 17051372 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 11:53:53 AM UTC 24 |
| Finished | Sep 11 11:53:55 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528238650 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1528238650 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_app.3101953977 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 4426438741 ps |
| CPU time | 266.22 seconds |
| Started | Sep 11 11:53:08 AM UTC 24 |
| Finished | Sep 11 11:57:39 AM UTC 24 |
| Peak memory | 305700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101953977 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3101953977 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.3596008243 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 468371827 ps |
| CPU time | 25.82 seconds |
| Started | Sep 11 11:52:41 AM UTC 24 |
| Finished | Sep 11 11:53:08 AM UTC 24 |
| Peak memory | 234100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596008243 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3596008243 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.3976237893 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 63155922271 ps |
| CPU time | 362.77 seconds |
| Started | Sep 11 11:53:09 AM UTC 24 |
| Finished | Sep 11 11:59:17 AM UTC 24 |
| Peak memory | 512620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976237893 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3976237893 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_error.3881465068 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3297908816 ps |
| CPU time | 357.32 seconds |
| Started | Sep 11 11:53:18 AM UTC 24 |
| Finished | Sep 11 11:59:21 AM UTC 24 |
| Peak memory | 330268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881465068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3881465068 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.2920794413 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 962625072 ps |
| CPU time | 3.79 seconds |
| Started | Sep 11 11:53:36 AM UTC 24 |
| Finished | Sep 11 11:53:42 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920794413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2920794413 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.3835807595 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 42117853 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 11:53:43 AM UTC 24 |
| Finished | Sep 11 11:53:46 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835807595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3835807595 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.1831924673 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 648976107866 ps |
| CPU time | 4328.96 seconds |
| Started | Sep 11 11:52:13 AM UTC 24 |
| Finished | Sep 11 01:05:09 PM UTC 24 |
| Peak memory | 4196996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831924673 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.1831924673 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.2903403909 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3103410022 ps |
| CPU time | 337.93 seconds |
| Started | Sep 11 11:52:13 AM UTC 24 |
| Finished | Sep 11 11:57:55 AM UTC 24 |
| Peak memory | 322128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903403909 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2903403909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.2206935346 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 7304231975 ps |
| CPU time | 38.28 seconds |
| Started | Sep 11 11:52:00 AM UTC 24 |
| Finished | Sep 11 11:52:40 AM UTC 24 |
| Peak memory | 236040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206935346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2206935346 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.3326113495 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 35758069772 ps |
| CPU time | 1098.54 seconds |
| Started | Sep 11 11:53:47 AM UTC 24 |
| Finished | Sep 11 12:12:19 PM UTC 24 |
| Peak memory | 983892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326113495 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3326113495 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.2133510247 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 61580647 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 11:57:56 AM UTC 24 |
| Finished | Sep 11 11:57:59 AM UTC 24 |
| Peak memory | 226592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133510247 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2133510247 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_app.2266397286 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 6409078080 ps |
| CPU time | 43.73 seconds |
| Started | Sep 11 11:57:40 AM UTC 24 |
| Finished | Sep 11 11:58:25 AM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266397286 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2266397286 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.660515945 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 9865613591 ps |
| CPU time | 1034.47 seconds |
| Started | Sep 11 11:57:32 AM UTC 24 |
| Finished | Sep 11 12:15:00 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660515945 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.660515945 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.3199585876 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 65831179220 ps |
| CPU time | 498.56 seconds |
| Started | Sep 11 11:57:43 AM UTC 24 |
| Finished | Sep 11 12:06:08 PM UTC 24 |
| Peak memory | 551456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199585876 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3199585876 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_error.2139903060 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 15995039002 ps |
| CPU time | 504.63 seconds |
| Started | Sep 11 11:57:45 AM UTC 24 |
| Finished | Sep 11 12:06:16 PM UTC 24 |
| Peak memory | 533004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139903060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2139903060 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.2182274113 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1931526054 ps |
| CPU time | 8.3 seconds |
| Started | Sep 11 11:57:46 AM UTC 24 |
| Finished | Sep 11 11:57:56 AM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182274113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2182274113 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2882054978 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 127543384 ps |
| CPU time | 2.59 seconds |
| Started | Sep 11 11:57:46 AM UTC 24 |
| Finished | Sep 11 11:57:50 AM UTC 24 |
| Peak memory | 234096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882054978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2882054978 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3434759561 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 72499277086 ps |
| CPU time | 1395.17 seconds |
| Started | Sep 11 11:54:25 AM UTC 24 |
| Finished | Sep 11 12:17:57 PM UTC 24 |
| Peak memory | 1839644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434759561 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3434759561 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.1312753146 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 5843386023 ps |
| CPU time | 286.22 seconds |
| Started | Sep 11 11:55:20 AM UTC 24 |
| Finished | Sep 11 12:00:10 PM UTC 24 |
| Peak memory | 322084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312753146 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1312753146 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.3278245965 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1236212090 ps |
| CPU time | 26.87 seconds |
| Started | Sep 11 11:53:56 AM UTC 24 |
| Finished | Sep 11 11:54:24 AM UTC 24 |
| Peak memory | 232048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278245965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3278245965 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.3687648608 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 41216446715 ps |
| CPU time | 388.53 seconds |
| Started | Sep 11 11:57:51 AM UTC 24 |
| Finished | Sep 11 12:04:25 PM UTC 24 |
| Peak memory | 451500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687648608 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3687648608 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.2347675521 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 25352987 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 12:00:35 PM UTC 24 |
| Finished | Sep 11 12:00:37 PM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347675521 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2347675521 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_app.2657013913 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 23214011352 ps |
| CPU time | 439.08 seconds |
| Started | Sep 11 11:58:54 AM UTC 24 |
| Finished | Sep 11 12:06:19 PM UTC 24 |
| Peak memory | 465560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657013913 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2657013913 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.615959121 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 13320012160 ps |
| CPU time | 423.93 seconds |
| Started | Sep 11 11:58:26 AM UTC 24 |
| Finished | Sep 11 12:05:36 PM UTC 24 |
| Peak memory | 248356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615959121 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.615959121 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.3495238967 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 14111450944 ps |
| CPU time | 385.01 seconds |
| Started | Sep 11 11:59:18 AM UTC 24 |
| Finished | Sep 11 12:05:48 PM UTC 24 |
| Peak memory | 481884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495238967 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3495238967 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_error.3019306494 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 6291482144 ps |
| CPU time | 227.95 seconds |
| Started | Sep 11 11:59:21 AM UTC 24 |
| Finished | Sep 11 12:03:13 PM UTC 24 |
| Peak memory | 324212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019306494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3019306494 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.3505004466 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 774744489 ps |
| CPU time | 4.01 seconds |
| Started | Sep 11 12:00:12 PM UTC 24 |
| Finished | Sep 11 12:00:17 PM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505004466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3505004466 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.3437551969 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 52519883 ps |
| CPU time | 2.27 seconds |
| Started | Sep 11 12:00:18 PM UTC 24 |
| Finished | Sep 11 12:00:21 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437551969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3437551969 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.1376310233 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 19604665181 ps |
| CPU time | 2306.56 seconds |
| Started | Sep 11 11:58:00 AM UTC 24 |
| Finished | Sep 11 12:36:54 PM UTC 24 |
| Peak memory | 1370656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376310233 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.1376310233 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.3233543830 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 16230711642 ps |
| CPU time | 424.32 seconds |
| Started | Sep 11 11:58:07 AM UTC 24 |
| Finished | Sep 11 12:05:17 PM UTC 24 |
| Peak memory | 582232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233543830 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3233543830 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.3065246515 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1606858460 ps |
| CPU time | 55.15 seconds |
| Started | Sep 11 11:57:56 AM UTC 24 |
| Finished | Sep 11 11:58:53 AM UTC 24 |
| Peak memory | 234072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065246515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3065246515 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.433296354 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 20869023211 ps |
| CPU time | 749.07 seconds |
| Started | Sep 11 12:00:22 PM UTC 24 |
| Finished | Sep 11 12:13:00 PM UTC 24 |
| Peak memory | 897948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433296354 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.433296354 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.335736653 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 67952593 ps |
| CPU time | 1.41 seconds |
| Started | Sep 11 12:05:18 PM UTC 24 |
| Finished | Sep 11 12:05:20 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335736653 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.335736653 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_app.1508982881 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 43057398175 ps |
| CPU time | 354.42 seconds |
| Started | Sep 11 12:03:18 PM UTC 24 |
| Finished | Sep 11 12:09:17 PM UTC 24 |
| Peak memory | 438820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508982881 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1508982881 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.3116139978 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 17651173953 ps |
| CPU time | 949.69 seconds |
| Started | Sep 11 12:03:14 PM UTC 24 |
| Finished | Sep 11 12:19:14 PM UTC 24 |
| Peak memory | 258628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116139978 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3116139978 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.93100666 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 32874715205 ps |
| CPU time | 302.97 seconds |
| Started | Sep 11 12:04:20 PM UTC 24 |
| Finished | Sep 11 12:09:27 PM UTC 24 |
| Peak memory | 332448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93100666 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.93100666 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_error.3646283679 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 23763274823 ps |
| CPU time | 151.53 seconds |
| Started | Sep 11 12:04:26 PM UTC 24 |
| Finished | Sep 11 12:07:01 PM UTC 24 |
| Peak memory | 363100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646283679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3646283679 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.193656030 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1358766792 ps |
| CPU time | 6.95 seconds |
| Started | Sep 11 12:04:58 PM UTC 24 |
| Finished | Sep 11 12:05:06 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193656030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.193656030 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.2178806659 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 173067749 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 12:05:07 PM UTC 24 |
| Finished | Sep 11 12:05:10 PM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178806659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2178806659 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.1519128844 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 236857477878 ps |
| CPU time | 2006.67 seconds |
| Started | Sep 11 12:01:06 PM UTC 24 |
| Finished | Sep 11 12:34:54 PM UTC 24 |
| Peak memory | 2527840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519128844 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.1519128844 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.3221638742 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 12238330994 ps |
| CPU time | 407.1 seconds |
| Started | Sep 11 12:01:54 PM UTC 24 |
| Finished | Sep 11 12:08:47 PM UTC 24 |
| Peak memory | 539156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221638742 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3221638742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.787976865 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 18792428153 ps |
| CPU time | 72.58 seconds |
| Started | Sep 11 12:00:38 PM UTC 24 |
| Finished | Sep 11 12:01:53 PM UTC 24 |
| Peak memory | 236192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787976865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.787976865 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.1606161030 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 5737707593 ps |
| CPU time | 149.59 seconds |
| Started | Sep 11 12:05:11 PM UTC 24 |
| Finished | Sep 11 12:07:43 PM UTC 24 |
| Peak memory | 314280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606161030 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1606161030 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.1489053830 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 62393213 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 12:06:25 PM UTC 24 |
| Finished | Sep 11 12:06:27 PM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489053830 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1489053830 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_app.1469411833 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 16503808762 ps |
| CPU time | 424.28 seconds |
| Started | Sep 11 12:05:50 PM UTC 24 |
| Finished | Sep 11 12:13:00 PM UTC 24 |
| Peak memory | 541248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469411833 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1469411833 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.2494075227 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 53765368344 ps |
| CPU time | 1223.3 seconds |
| Started | Sep 11 12:05:36 PM UTC 24 |
| Finished | Sep 11 12:26:14 PM UTC 24 |
| Peak memory | 256608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494075227 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2494075227 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.2438786734 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 14053233100 ps |
| CPU time | 350.92 seconds |
| Started | Sep 11 12:06:02 PM UTC 24 |
| Finished | Sep 11 12:11:58 PM UTC 24 |
| Peak memory | 459352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438786734 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2438786734 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_error.2833147873 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 7925205119 ps |
| CPU time | 354.82 seconds |
| Started | Sep 11 12:06:09 PM UTC 24 |
| Finished | Sep 11 12:12:09 PM UTC 24 |
| Peak memory | 350880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833147873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2833147873 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.3150858579 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 36794659639 ps |
| CPU time | 1626.64 seconds |
| Started | Sep 11 12:05:21 PM UTC 24 |
| Finished | Sep 11 12:32:47 PM UTC 24 |
| Peak memory | 1970784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150858579 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.3150858579 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.95786139 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3574926080 ps |
| CPU time | 192.05 seconds |
| Started | Sep 11 12:05:28 PM UTC 24 |
| Finished | Sep 11 12:08:43 PM UTC 24 |
| Peak memory | 297640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95786139 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.95786139 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.4236186766 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1912001147 ps |
| CPU time | 40.42 seconds |
| Started | Sep 11 12:05:19 PM UTC 24 |
| Finished | Sep 11 12:06:01 PM UTC 24 |
| Peak memory | 235912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236186766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4236186766 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.215307294 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 16405662068 ps |
| CPU time | 262.22 seconds |
| Started | Sep 11 12:06:21 PM UTC 24 |
| Finished | Sep 11 12:10:47 PM UTC 24 |
| Peak memory | 328284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215307294 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.215307294 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.295524892 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 42184171 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 10:39:47 AM UTC 24 |
| Finished | Sep 11 10:39:49 AM UTC 24 |
| Peak memory | 226288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295524892 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.295524892 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_app.1659398624 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3471251449 ps |
| CPU time | 271.08 seconds |
| Started | Sep 11 10:37:36 AM UTC 24 |
| Finished | Sep 11 10:42:12 AM UTC 24 |
| Peak memory | 307776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659398624 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1659398624 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2265261993 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 5161102327 ps |
| CPU time | 305.99 seconds |
| Started | Sep 11 10:37:37 AM UTC 24 |
| Finished | Sep 11 10:42:48 AM UTC 24 |
| Peak memory | 336412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265261993 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2265261993 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.2217350670 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 23494781905 ps |
| CPU time | 278.58 seconds |
| Started | Sep 11 10:36:54 AM UTC 24 |
| Finished | Sep 11 10:41:37 AM UTC 24 |
| Peak memory | 250384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217350670 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2217350670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3158756173 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 33241213 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 10:38:03 AM UTC 24 |
| Finished | Sep 11 10:38:06 AM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158756173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3158756173 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.196939149 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 55596419 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 10:38:07 AM UTC 24 |
| Finished | Sep 11 10:38:09 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196939149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.196939149 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.13971248 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 11375721133 ps |
| CPU time | 94.26 seconds |
| Started | Sep 11 10:38:10 AM UTC 24 |
| Finished | Sep 11 10:39:46 AM UTC 24 |
| Peak memory | 234420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13971248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_mask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.13971248 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3872471678 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 11157961723 ps |
| CPU time | 167.72 seconds |
| Started | Sep 11 10:37:52 AM UTC 24 |
| Finished | Sep 11 10:40:43 AM UTC 24 |
| Peak memory | 342592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872471678 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3872471678 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_error.2293543267 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8445877258 ps |
| CPU time | 265 seconds |
| Started | Sep 11 10:37:56 AM UTC 24 |
| Finished | Sep 11 10:42:24 AM UTC 24 |
| Peak memory | 453152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293543267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2293543267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.1026200310 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 511993793 ps |
| CPU time | 3.53 seconds |
| Started | Sep 11 10:37:58 AM UTC 24 |
| Finished | Sep 11 10:38:02 AM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026200310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1026200310 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.2912243450 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13220779808 ps |
| CPU time | 57.42 seconds |
| Started | Sep 11 10:38:18 AM UTC 24 |
| Finished | Sep 11 10:39:17 AM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912243450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2912243450 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.4228304535 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 78532535633 ps |
| CPU time | 584.72 seconds |
| Started | Sep 11 10:36:51 AM UTC 24 |
| Finished | Sep 11 10:46:43 AM UTC 24 |
| Peak memory | 928340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228304535 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.4228304535 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.1286402132 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 23669511193 ps |
| CPU time | 161.17 seconds |
| Started | Sep 11 10:37:56 AM UTC 24 |
| Finished | Sep 11 10:40:40 AM UTC 24 |
| Peak memory | 357196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286402132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1286402132 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.3780602088 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 9278266531 ps |
| CPU time | 35.34 seconds |
| Started | Sep 11 10:39:19 AM UTC 24 |
| Finished | Sep 11 10:39:55 AM UTC 24 |
| Peak memory | 278376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780602088 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3780602088 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.2411120166 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3701695386 ps |
| CPU time | 269.52 seconds |
| Started | Sep 11 10:36:53 AM UTC 24 |
| Finished | Sep 11 10:41:27 AM UTC 24 |
| Peak memory | 332380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411120166 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2411120166 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.2500698302 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2153393422 ps |
| CPU time | 27.63 seconds |
| Started | Sep 11 10:36:23 AM UTC 24 |
| Finished | Sep 11 10:36:52 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500698302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2500698302 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.727226371 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 47148987818 ps |
| CPU time | 2006.72 seconds |
| Started | Sep 11 10:38:22 AM UTC 24 |
| Finished | Sep 11 11:12:12 AM UTC 24 |
| Peak memory | 869264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727226371 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.727226371 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.2040836728 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 751245323 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 10:37:31 AM UTC 24 |
| Finished | Sep 11 10:37:36 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040836728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.2040836728 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1812076624 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 108360352 ps |
| CPU time | 3.73 seconds |
| Started | Sep 11 10:37:31 AM UTC 24 |
| Finished | Sep 11 10:37:36 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812076624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1812076624 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.2858272502 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1220933266 ps |
| CPU time | 52.49 seconds |
| Started | Sep 11 10:37:03 AM UTC 24 |
| Finished | Sep 11 10:37:57 AM UTC 24 |
| Peak memory | 234872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858272502 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2858272502 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.1187505747 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1996595395 ps |
| CPU time | 44.99 seconds |
| Started | Sep 11 10:37:09 AM UTC 24 |
| Finished | Sep 11 10:37:55 AM UTC 24 |
| Peak memory | 256408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187505747 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1187505747 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.2826155343 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1831776552 ps |
| CPU time | 37.35 seconds |
| Started | Sep 11 10:37:13 AM UTC 24 |
| Finished | Sep 11 10:37:52 AM UTC 24 |
| Peak memory | 242012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826155343 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2826155343 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.2760948540 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3542156177 ps |
| CPU time | 16.74 seconds |
| Started | Sep 11 10:37:13 AM UTC 24 |
| Finished | Sep 11 10:37:31 AM UTC 24 |
| Peak memory | 234160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760948540 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2760948540 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.2646632219 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 283732588421 ps |
| CPU time | 2826.56 seconds |
| Started | Sep 11 10:37:23 AM UTC 24 |
| Finished | Sep 11 11:24:59 AM UTC 24 |
| Peak memory | 3621388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646632219 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2646632219 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.4286200664 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 46711863051 ps |
| CPU time | 554.85 seconds |
| Started | Sep 11 10:37:24 AM UTC 24 |
| Finished | Sep 11 10:46:46 AM UTC 24 |
| Peak memory | 369096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286200664 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.4286200664 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.2774052774 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 87426827 ps |
| CPU time | 1.06 seconds |
| Started | Sep 11 12:09:11 PM UTC 24 |
| Finished | Sep 11 12:09:13 PM UTC 24 |
| Peak memory | 225092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774052774 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2774052774 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_app.3299390733 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 9620140119 ps |
| CPU time | 300.08 seconds |
| Started | Sep 11 12:07:01 PM UTC 24 |
| Finished | Sep 11 12:12:06 PM UTC 24 |
| Peak memory | 334424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299390733 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3299390733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.1475476588 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3404232867 ps |
| CPU time | 224.14 seconds |
| Started | Sep 11 12:06:59 PM UTC 24 |
| Finished | Sep 11 12:10:47 PM UTC 24 |
| Peak memory | 238116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475476588 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1475476588 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.454926429 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 34793865456 ps |
| CPU time | 384.91 seconds |
| Started | Sep 11 12:07:44 PM UTC 24 |
| Finished | Sep 11 12:14:15 PM UTC 24 |
| Peak memory | 529116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454926429 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.454926429 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_error.1857748870 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 4291758311 ps |
| CPU time | 176.39 seconds |
| Started | Sep 11 12:07:55 PM UTC 24 |
| Finished | Sep 11 12:10:54 PM UTC 24 |
| Peak memory | 334424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857748870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1857748870 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2719265287 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1843971033 ps |
| CPU time | 22.09 seconds |
| Started | Sep 11 12:08:45 PM UTC 24 |
| Finished | Sep 11 12:09:08 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719265287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2719265287 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.2378431945 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 599187335 ps |
| CPU time | 21.25 seconds |
| Started | Sep 11 12:08:48 PM UTC 24 |
| Finished | Sep 11 12:09:11 PM UTC 24 |
| Peak memory | 246316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378431945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2378431945 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.2352675329 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 209094671349 ps |
| CPU time | 2213.4 seconds |
| Started | Sep 11 12:06:32 PM UTC 24 |
| Finished | Sep 11 12:43:50 PM UTC 24 |
| Peak memory | 2286244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352675329 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.2352675329 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.1585431258 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 16447893756 ps |
| CPU time | 395.96 seconds |
| Started | Sep 11 12:06:55 PM UTC 24 |
| Finished | Sep 11 12:13:36 PM UTC 24 |
| Peak memory | 561756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585431258 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1585431258 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.1136449390 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 12826746757 ps |
| CPU time | 84.58 seconds |
| Started | Sep 11 12:06:28 PM UTC 24 |
| Finished | Sep 11 12:07:54 PM UTC 24 |
| Peak memory | 236044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136449390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1136449390 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.1606228698 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 12788373293 ps |
| CPU time | 239.87 seconds |
| Started | Sep 11 12:09:09 PM UTC 24 |
| Finished | Sep 11 12:13:13 PM UTC 24 |
| Peak memory | 297568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606228698 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1606228698 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.3587318691 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 115108025 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 12:11:24 PM UTC 24 |
| Finished | Sep 11 12:11:27 PM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587318691 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3587318691 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_app.294779661 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 570113952 ps |
| CPU time | 33.47 seconds |
| Started | Sep 11 12:10:43 PM UTC 24 |
| Finished | Sep 11 12:11:18 PM UTC 24 |
| Peak memory | 242088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294779661 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.294779661 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.1652902041 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 29186055171 ps |
| CPU time | 852.97 seconds |
| Started | Sep 11 12:10:02 PM UTC 24 |
| Finished | Sep 11 12:24:26 PM UTC 24 |
| Peak memory | 256544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652902041 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.1652902041 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.2277543215 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 7044696877 ps |
| CPU time | 239.11 seconds |
| Started | Sep 11 12:10:48 PM UTC 24 |
| Finished | Sep 11 12:14:51 PM UTC 24 |
| Peak memory | 307872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277543215 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2277543215 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_error.1670604638 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 19003922440 ps |
| CPU time | 455.49 seconds |
| Started | Sep 11 12:10:48 PM UTC 24 |
| Finished | Sep 11 12:18:30 PM UTC 24 |
| Peak memory | 614940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670604638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1670604638 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.1721136451 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 7303507041 ps |
| CPU time | 27.2 seconds |
| Started | Sep 11 12:10:55 PM UTC 24 |
| Finished | Sep 11 12:11:23 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721136451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1721136451 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.2407789986 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 57398135 ps |
| CPU time | 2 seconds |
| Started | Sep 11 12:11:19 PM UTC 24 |
| Finished | Sep 11 12:11:22 PM UTC 24 |
| Peak memory | 231580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407789986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2407789986 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.382083092 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 20753687170 ps |
| CPU time | 491.9 seconds |
| Started | Sep 11 12:09:19 PM UTC 24 |
| Finished | Sep 11 12:17:37 PM UTC 24 |
| Peak memory | 492120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382083092 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.382083092 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.110413007 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 692654209 ps |
| CPU time | 71.33 seconds |
| Started | Sep 11 12:09:29 PM UTC 24 |
| Finished | Sep 11 12:10:42 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110413007 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.110413007 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.2606204502 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1388465617 ps |
| CPU time | 44.42 seconds |
| Started | Sep 11 12:09:15 PM UTC 24 |
| Finished | Sep 11 12:10:01 PM UTC 24 |
| Peak memory | 235996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606204502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2606204502 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.3686496264 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 92532632142 ps |
| CPU time | 1324.19 seconds |
| Started | Sep 11 12:11:23 PM UTC 24 |
| Finished | Sep 11 12:33:43 PM UTC 24 |
| Peak memory | 545620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686496264 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3686496264 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.3565917831 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 41894506 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 12:13:17 PM UTC 24 |
| Finished | Sep 11 12:13:19 PM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565917831 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3565917831 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_app.1296541147 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 4841751564 ps |
| CPU time | 136.47 seconds |
| Started | Sep 11 12:12:10 PM UTC 24 |
| Finished | Sep 11 12:14:29 PM UTC 24 |
| Peak memory | 307816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296541147 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1296541147 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.3999435796 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 9939997770 ps |
| CPU time | 473 seconds |
| Started | Sep 11 12:12:07 PM UTC 24 |
| Finished | Sep 11 12:20:06 PM UTC 24 |
| Peak memory | 246372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999435796 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3999435796 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1022901188 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1094229931 ps |
| CPU time | 54.22 seconds |
| Started | Sep 11 12:12:20 PM UTC 24 |
| Finished | Sep 11 12:13:16 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022901188 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1022901188 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_error.3884123867 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2231780370 ps |
| CPU time | 46.3 seconds |
| Started | Sep 11 12:12:45 PM UTC 24 |
| Finished | Sep 11 12:13:33 PM UTC 24 |
| Peak memory | 279068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884123867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3884123867 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.1824858365 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 14488626762 ps |
| CPU time | 21.04 seconds |
| Started | Sep 11 12:13:01 PM UTC 24 |
| Finished | Sep 11 12:13:24 PM UTC 24 |
| Peak memory | 227936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824858365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1824858365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.660601947 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 853152977 ps |
| CPU time | 39.67 seconds |
| Started | Sep 11 12:13:02 PM UTC 24 |
| Finished | Sep 11 12:13:43 PM UTC 24 |
| Peak memory | 252400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660601947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.660601947 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.3421466334 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 29208704478 ps |
| CPU time | 1710.92 seconds |
| Started | Sep 11 12:11:58 PM UTC 24 |
| Finished | Sep 11 12:40:49 PM UTC 24 |
| Peak memory | 1077980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421466334 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.3421466334 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.1223398816 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 99956675945 ps |
| CPU time | 387.8 seconds |
| Started | Sep 11 12:12:00 PM UTC 24 |
| Finished | Sep 11 12:18:33 PM UTC 24 |
| Peak memory | 451168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223398816 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1223398816 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.635662267 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 4288649446 ps |
| CPU time | 75.09 seconds |
| Started | Sep 11 12:11:27 PM UTC 24 |
| Finished | Sep 11 12:12:45 PM UTC 24 |
| Peak memory | 236132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635662267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.635662267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.2441197652 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 110909658521 ps |
| CPU time | 2020.69 seconds |
| Started | Sep 11 12:13:14 PM UTC 24 |
| Finished | Sep 11 12:47:19 PM UTC 24 |
| Peak memory | 631332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441197652 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2441197652 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.242840415 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 12900387 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 12:14:49 PM UTC 24 |
| Finished | Sep 11 12:14:52 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242840415 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.242840415 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_app.3006060087 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 34353358822 ps |
| CPU time | 46.36 seconds |
| Started | Sep 11 12:13:43 PM UTC 24 |
| Finished | Sep 11 12:14:31 PM UTC 24 |
| Peak memory | 266776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006060087 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3006060087 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.3170072365 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 14937895753 ps |
| CPU time | 637.63 seconds |
| Started | Sep 11 12:13:37 PM UTC 24 |
| Finished | Sep 11 12:24:23 PM UTC 24 |
| Peak memory | 254488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170072365 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3170072365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2250314792 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 25139630649 ps |
| CPU time | 304.6 seconds |
| Started | Sep 11 12:14:16 PM UTC 24 |
| Finished | Sep 11 12:19:25 PM UTC 24 |
| Peak memory | 440860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250314792 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2250314792 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_error.1902951153 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 91957452229 ps |
| CPU time | 522.71 seconds |
| Started | Sep 11 12:14:30 PM UTC 24 |
| Finished | Sep 11 12:23:19 PM UTC 24 |
| Peak memory | 582240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902951153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1902951153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.3687941051 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 5904755563 ps |
| CPU time | 16.08 seconds |
| Started | Sep 11 12:14:32 PM UTC 24 |
| Finished | Sep 11 12:14:49 PM UTC 24 |
| Peak memory | 228000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687941051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3687941051 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.4053713807 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 49259973 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 12:14:36 PM UTC 24 |
| Finished | Sep 11 12:14:39 PM UTC 24 |
| Peak memory | 233652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053713807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.4053713807 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.2189621181 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 22603286034 ps |
| CPU time | 1180.15 seconds |
| Started | Sep 11 12:13:25 PM UTC 24 |
| Finished | Sep 11 12:33:20 PM UTC 24 |
| Peak memory | 1241760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189621181 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.2189621181 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.1651618418 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1985626557 ps |
| CPU time | 58.97 seconds |
| Started | Sep 11 12:13:34 PM UTC 24 |
| Finished | Sep 11 12:14:35 PM UTC 24 |
| Peak memory | 283076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651618418 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1651618418 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.1826137396 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 21024148319 ps |
| CPU time | 89.62 seconds |
| Started | Sep 11 12:13:20 PM UTC 24 |
| Finished | Sep 11 12:14:52 PM UTC 24 |
| Peak memory | 235812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826137396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1826137396 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.985281641 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2525319599 ps |
| CPU time | 94.04 seconds |
| Started | Sep 11 12:14:39 PM UTC 24 |
| Finished | Sep 11 12:16:15 PM UTC 24 |
| Peak memory | 260644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985281641 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.985281641 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.3407751995 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 19297605 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 12:16:54 PM UTC 24 |
| Finished | Sep 11 12:16:57 PM UTC 24 |
| Peak memory | 227000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407751995 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3407751995 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_app.1672995790 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 11169727593 ps |
| CPU time | 109.52 seconds |
| Started | Sep 11 12:15:01 PM UTC 24 |
| Finished | Sep 11 12:16:53 PM UTC 24 |
| Peak memory | 293532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672995790 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1672995790 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.100310968 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3714815249 ps |
| CPU time | 219.88 seconds |
| Started | Sep 11 12:14:53 PM UTC 24 |
| Finished | Sep 11 12:18:36 PM UTC 24 |
| Peak memory | 250672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100310968 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.100310968 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.650331883 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 58050262796 ps |
| CPU time | 236.24 seconds |
| Started | Sep 11 12:15:14 PM UTC 24 |
| Finished | Sep 11 12:19:14 PM UTC 24 |
| Peak memory | 432644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650331883 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.650331883 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_error.269908762 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 13166719543 ps |
| CPU time | 240.93 seconds |
| Started | Sep 11 12:16:17 PM UTC 24 |
| Finished | Sep 11 12:20:22 PM UTC 24 |
| Peak memory | 326240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269908762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.269908762 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.520421365 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 135957029 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 12:16:31 PM UTC 24 |
| Finished | Sep 11 12:16:35 PM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520421365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.520421365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.4069662359 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 36891379 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 12:16:36 PM UTC 24 |
| Finished | Sep 11 12:16:39 PM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069662359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4069662359 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.3806813059 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 80210840860 ps |
| CPU time | 3246.12 seconds |
| Started | Sep 11 12:14:52 PM UTC 24 |
| Finished | Sep 11 01:09:35 PM UTC 24 |
| Peak memory | 1845900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806813059 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.3806813059 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.3515688661 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1966344169 ps |
| CPU time | 94.9 seconds |
| Started | Sep 11 12:14:53 PM UTC 24 |
| Finished | Sep 11 12:16:30 PM UTC 24 |
| Peak memory | 258460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515688661 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3515688661 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.2515465906 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 918432878 ps |
| CPU time | 21.75 seconds |
| Started | Sep 11 12:14:50 PM UTC 24 |
| Finished | Sep 11 12:15:13 PM UTC 24 |
| Peak memory | 232048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515465906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2515465906 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.930622227 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 11809537881 ps |
| CPU time | 1165.29 seconds |
| Started | Sep 11 12:16:40 PM UTC 24 |
| Finished | Sep 11 12:36:20 PM UTC 24 |
| Peak memory | 328288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930622227 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.930622227 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.412456387 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 32609048 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 12:19:15 PM UTC 24 |
| Finished | Sep 11 12:19:17 PM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412456387 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.412456387 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_app.2910059992 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 7116553210 ps |
| CPU time | 211.78 seconds |
| Started | Sep 11 12:17:57 PM UTC 24 |
| Finished | Sep 11 12:21:32 PM UTC 24 |
| Peak memory | 387620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910059992 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2910059992 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.563953305 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 9396165192 ps |
| CPU time | 293.52 seconds |
| Started | Sep 11 12:17:38 PM UTC 24 |
| Finished | Sep 11 12:22:36 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563953305 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.563953305 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.1810187437 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 19302681496 ps |
| CPU time | 319.69 seconds |
| Started | Sep 11 12:18:30 PM UTC 24 |
| Finished | Sep 11 12:23:55 PM UTC 24 |
| Peak memory | 467620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810187437 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1810187437 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_error.237606725 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 18346766449 ps |
| CPU time | 372.8 seconds |
| Started | Sep 11 12:18:34 PM UTC 24 |
| Finished | Sep 11 12:24:52 PM UTC 24 |
| Peak memory | 377504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237606725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.237606725 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.1598601263 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2008147974 ps |
| CPU time | 19.7 seconds |
| Started | Sep 11 12:18:37 PM UTC 24 |
| Finished | Sep 11 12:18:58 PM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598601263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1598601263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.795398409 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1272013253 ps |
| CPU time | 18.36 seconds |
| Started | Sep 11 12:18:59 PM UTC 24 |
| Finished | Sep 11 12:19:18 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795398409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.795398409 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.223942583 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4511528607 ps |
| CPU time | 172.72 seconds |
| Started | Sep 11 12:17:10 PM UTC 24 |
| Finished | Sep 11 12:20:06 PM UTC 24 |
| Peak memory | 438876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223942583 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.223942583 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.566139636 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 37351832423 ps |
| CPU time | 264.69 seconds |
| Started | Sep 11 12:17:33 PM UTC 24 |
| Finished | Sep 11 12:22:01 PM UTC 24 |
| Peak memory | 385576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566139636 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.566139636 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.2340507094 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 770999908 ps |
| CPU time | 11.3 seconds |
| Started | Sep 11 12:16:57 PM UTC 24 |
| Finished | Sep 11 12:17:10 PM UTC 24 |
| Peak memory | 235940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340507094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2340507094 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.2783594210 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 44115640464 ps |
| CPU time | 1264.49 seconds |
| Started | Sep 11 12:19:15 PM UTC 24 |
| Finished | Sep 11 12:40:33 PM UTC 24 |
| Peak memory | 1680308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783594210 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2783594210 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.3689617214 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 15425341 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 12:20:55 PM UTC 24 |
| Finished | Sep 11 12:20:57 PM UTC 24 |
| Peak memory | 227000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689617214 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3689617214 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_app.2311528678 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 25604349211 ps |
| CPU time | 338.7 seconds |
| Started | Sep 11 12:20:07 PM UTC 24 |
| Finished | Sep 11 12:25:51 PM UTC 24 |
| Peak memory | 465424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311528678 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2311528678 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.3104212436 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 38056501463 ps |
| CPU time | 408.66 seconds |
| Started | Sep 11 12:19:49 PM UTC 24 |
| Finished | Sep 11 12:26:43 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104212436 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.3104212436 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.895457177 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2976058675 ps |
| CPU time | 25.81 seconds |
| Started | Sep 11 12:20:07 PM UTC 24 |
| Finished | Sep 11 12:20:35 PM UTC 24 |
| Peak memory | 238108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895457177 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.895457177 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_error.3489894788 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 24242530914 ps |
| CPU time | 628.29 seconds |
| Started | Sep 11 12:20:22 PM UTC 24 |
| Finished | Sep 11 12:30:59 PM UTC 24 |
| Peak memory | 688740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489894788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3489894788 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.1888819541 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4801742232 ps |
| CPU time | 13.48 seconds |
| Started | Sep 11 12:20:36 PM UTC 24 |
| Finished | Sep 11 12:20:50 PM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888819541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1888819541 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.2171002553 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 186457131 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 12:20:51 PM UTC 24 |
| Finished | Sep 11 12:20:54 PM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171002553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2171002553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2542555749 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 14163490031 ps |
| CPU time | 1441.4 seconds |
| Started | Sep 11 12:19:20 PM UTC 24 |
| Finished | Sep 11 12:43:38 PM UTC 24 |
| Peak memory | 1043044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542555749 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2542555749 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.259454067 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 58881845698 ps |
| CPU time | 570.37 seconds |
| Started | Sep 11 12:19:26 PM UTC 24 |
| Finished | Sep 11 12:29:04 PM UTC 24 |
| Peak memory | 668324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259454067 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.259454067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.1111713584 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 962942946 ps |
| CPU time | 28.26 seconds |
| Started | Sep 11 12:19:18 PM UTC 24 |
| Finished | Sep 11 12:19:48 PM UTC 24 |
| Peak memory | 234160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111713584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1111713584 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.1411500200 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 12880326539 ps |
| CPU time | 1027.13 seconds |
| Started | Sep 11 12:20:55 PM UTC 24 |
| Finished | Sep 11 12:38:14 PM UTC 24 |
| Peak memory | 439232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411500200 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1411500200 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.1967107664 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 51864618 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 12:24:09 PM UTC 24 |
| Finished | Sep 11 12:24:12 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967107664 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1967107664 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_app.2746029980 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 32293056532 ps |
| CPU time | 176.21 seconds |
| Started | Sep 11 12:22:42 PM UTC 24 |
| Finished | Sep 11 12:25:41 PM UTC 24 |
| Peak memory | 375384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746029980 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2746029980 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.3951231717 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 12032499342 ps |
| CPU time | 1221.64 seconds |
| Started | Sep 11 12:22:36 PM UTC 24 |
| Finished | Sep 11 12:43:13 PM UTC 24 |
| Peak memory | 254564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951231717 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3951231717 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1760437095 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2228191700 ps |
| CPU time | 91.77 seconds |
| Started | Sep 11 12:22:49 PM UTC 24 |
| Finished | Sep 11 12:24:23 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760437095 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1760437095 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_error.1205939476 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 60098149820 ps |
| CPU time | 414.94 seconds |
| Started | Sep 11 12:23:21 PM UTC 24 |
| Finished | Sep 11 12:30:21 PM UTC 24 |
| Peak memory | 572068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205939476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1205939476 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.2524074850 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1489400862 ps |
| CPU time | 10.98 seconds |
| Started | Sep 11 12:23:56 PM UTC 24 |
| Finished | Sep 11 12:24:08 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524074850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2524074850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.1855263309 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 48826084 ps |
| CPU time | 1.43 seconds |
| Started | Sep 11 12:24:00 PM UTC 24 |
| Finished | Sep 11 12:24:02 PM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855263309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1855263309 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.2307756199 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 57717492657 ps |
| CPU time | 2615.96 seconds |
| Started | Sep 11 12:21:34 PM UTC 24 |
| Finished | Sep 11 01:05:40 PM UTC 24 |
| Peak memory | 2806300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307756199 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.2307756199 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.2923737361 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 12355027509 ps |
| CPU time | 425.41 seconds |
| Started | Sep 11 12:22:03 PM UTC 24 |
| Finished | Sep 11 12:29:14 PM UTC 24 |
| Peak memory | 567896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923737361 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2923737361 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.3283533187 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 29636694128 ps |
| CPU time | 107.64 seconds |
| Started | Sep 11 12:20:58 PM UTC 24 |
| Finished | Sep 11 12:22:48 PM UTC 24 |
| Peak memory | 236056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283533187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3283533187 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.3986466399 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 757488817299 ps |
| CPU time | 1716.57 seconds |
| Started | Sep 11 12:24:03 PM UTC 24 |
| Finished | Sep 11 12:52:59 PM UTC 24 |
| Peak memory | 1336176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986466399 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3986466399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.763698874 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 21171838 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 12:25:44 PM UTC 24 |
| Finished | Sep 11 12:25:46 PM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763698874 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.763698874 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_app.3388302663 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 5186529569 ps |
| CPU time | 182.67 seconds |
| Started | Sep 11 12:24:31 PM UTC 24 |
| Finished | Sep 11 12:27:37 PM UTC 24 |
| Peak memory | 281176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388302663 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3388302663 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.4192213546 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 7090191239 ps |
| CPU time | 672 seconds |
| Started | Sep 11 12:24:27 PM UTC 24 |
| Finished | Sep 11 12:35:48 PM UTC 24 |
| Peak memory | 246360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192213546 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.4192213546 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3685635867 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 8942860271 ps |
| CPU time | 301.27 seconds |
| Started | Sep 11 12:24:35 PM UTC 24 |
| Finished | Sep 11 12:29:42 PM UTC 24 |
| Peak memory | 406116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685635867 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3685635867 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_error.776483841 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 114905452609 ps |
| CPU time | 545.04 seconds |
| Started | Sep 11 12:24:53 PM UTC 24 |
| Finished | Sep 11 12:34:05 PM UTC 24 |
| Peak memory | 649820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776483841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.776483841 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.3586763929 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4751601860 ps |
| CPU time | 17.32 seconds |
| Started | Sep 11 12:25:37 PM UTC 24 |
| Finished | Sep 11 12:25:56 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586763929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3586763929 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.481053959 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 41860968 ps |
| CPU time | 1.85 seconds |
| Started | Sep 11 12:25:40 PM UTC 24 |
| Finished | Sep 11 12:25:43 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481053959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.481053959 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3855918638 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 94276347796 ps |
| CPU time | 3944.71 seconds |
| Started | Sep 11 12:24:24 PM UTC 24 |
| Finished | Sep 11 01:30:51 PM UTC 24 |
| Peak memory | 4559548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855918638 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3855918638 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.3843991457 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 76793257301 ps |
| CPU time | 335.7 seconds |
| Started | Sep 11 12:24:25 PM UTC 24 |
| Finished | Sep 11 12:30:06 PM UTC 24 |
| Peak memory | 481828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843991457 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3843991457 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.1821935154 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 25549325866 ps |
| CPU time | 81.15 seconds |
| Started | Sep 11 12:24:13 PM UTC 24 |
| Finished | Sep 11 12:25:36 PM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821935154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1821935154 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.1418182514 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 68616220 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 12:25:42 PM UTC 24 |
| Finished | Sep 11 12:25:47 PM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418182514 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1418182514 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.3204868653 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 53986555 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 12:27:42 PM UTC 24 |
| Finished | Sep 11 12:27:44 PM UTC 24 |
| Peak memory | 227000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204868653 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3204868653 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_app.650372914 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 17376247340 ps |
| CPU time | 295.44 seconds |
| Started | Sep 11 12:26:14 PM UTC 24 |
| Finished | Sep 11 12:31:14 PM UTC 24 |
| Peak memory | 318116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650372914 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.650372914 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.3644117857 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4631099763 ps |
| CPU time | 269.15 seconds |
| Started | Sep 11 12:25:56 PM UTC 24 |
| Finished | Sep 11 12:30:30 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644117857 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3644117857 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.1052272952 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 17900879575 ps |
| CPU time | 252.96 seconds |
| Started | Sep 11 12:26:17 PM UTC 24 |
| Finished | Sep 11 12:30:33 PM UTC 24 |
| Peak memory | 307752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052272952 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1052272952 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_error.988344498 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 10847009326 ps |
| CPU time | 208.55 seconds |
| Started | Sep 11 12:26:44 PM UTC 24 |
| Finished | Sep 11 12:30:16 PM UTC 24 |
| Peak memory | 318120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988344498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.988344498 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.2188077883 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 609653862 ps |
| CPU time | 8.27 seconds |
| Started | Sep 11 12:27:31 PM UTC 24 |
| Finished | Sep 11 12:27:41 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188077883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2188077883 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.1178611883 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 123535464 ps |
| CPU time | 2.1 seconds |
| Started | Sep 11 12:27:38 PM UTC 24 |
| Finished | Sep 11 12:27:42 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178611883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1178611883 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.594150339 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 19017291614 ps |
| CPU time | 614.96 seconds |
| Started | Sep 11 12:25:48 PM UTC 24 |
| Finished | Sep 11 12:36:11 PM UTC 24 |
| Peak memory | 911900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594150339 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.594150339 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.2832780206 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1785045751 ps |
| CPU time | 150.37 seconds |
| Started | Sep 11 12:25:52 PM UTC 24 |
| Finished | Sep 11 12:28:25 PM UTC 24 |
| Peak memory | 268700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832780206 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2832780206 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.1144220835 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3594248139 ps |
| CPU time | 101.49 seconds |
| Started | Sep 11 12:25:47 PM UTC 24 |
| Finished | Sep 11 12:27:30 PM UTC 24 |
| Peak memory | 236116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144220835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1144220835 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.3541603713 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 41020913176 ps |
| CPU time | 1503.68 seconds |
| Started | Sep 11 12:27:39 PM UTC 24 |
| Finished | Sep 11 12:53:01 PM UTC 24 |
| Peak memory | 433016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541603713 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3541603713 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.3780145672 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 20603124 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 10:41:46 AM UTC 24 |
| Finished | Sep 11 10:41:49 AM UTC 24 |
| Peak memory | 225036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780145672 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3780145672 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_app.1540045991 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 38493663311 ps |
| CPU time | 154.52 seconds |
| Started | Sep 11 10:40:21 AM UTC 24 |
| Finished | Sep 11 10:42:58 AM UTC 24 |
| Peak memory | 311900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540045991 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1540045991 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.4012703099 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 24429370723 ps |
| CPU time | 395.54 seconds |
| Started | Sep 11 10:40:40 AM UTC 24 |
| Finished | Sep 11 10:47:21 AM UTC 24 |
| Peak memory | 385644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012703099 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.4012703099 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.165492104 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 23683155839 ps |
| CPU time | 251.92 seconds |
| Started | Sep 11 10:40:17 AM UTC 24 |
| Finished | Sep 11 10:44:33 AM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165492104 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.165492104 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.2588806054 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 37584008 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 10:41:29 AM UTC 24 |
| Finished | Sep 11 10:41:31 AM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588806054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2588806054 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3445372927 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 62857071 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 10:41:32 AM UTC 24 |
| Finished | Sep 11 10:41:34 AM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445372927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3445372927 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.177330901 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1161799940 ps |
| CPU time | 9.17 seconds |
| Started | Sep 11 10:41:35 AM UTC 24 |
| Finished | Sep 11 10:41:45 AM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177330901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.177330901 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.1828248788 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3065386067 ps |
| CPU time | 159.75 seconds |
| Started | Sep 11 10:40:44 AM UTC 24 |
| Finished | Sep 11 10:43:27 AM UTC 24 |
| Peak memory | 272968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828248788 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1828248788 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_error.2401565639 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 45321243814 ps |
| CPU time | 317.3 seconds |
| Started | Sep 11 10:41:24 AM UTC 24 |
| Finished | Sep 11 10:46:45 AM UTC 24 |
| Peak memory | 508576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401565639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2401565639 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.1619624388 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 6103531775 ps |
| CPU time | 20.6 seconds |
| Started | Sep 11 10:41:28 AM UTC 24 |
| Finished | Sep 11 10:41:50 AM UTC 24 |
| Peak memory | 228004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619624388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1619624388 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.3633658209 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 30606761 ps |
| CPU time | 2.08 seconds |
| Started | Sep 11 10:41:38 AM UTC 24 |
| Finished | Sep 11 10:41:41 AM UTC 24 |
| Peak memory | 234164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633658209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3633658209 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.3350213747 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 26704117793 ps |
| CPU time | 1538.85 seconds |
| Started | Sep 11 10:39:51 AM UTC 24 |
| Finished | Sep 11 11:05:48 AM UTC 24 |
| Peak memory | 989772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350213747 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.3350213747 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.1966372399 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 41974616711 ps |
| CPU time | 238.28 seconds |
| Started | Sep 11 10:40:55 AM UTC 24 |
| Finished | Sep 11 10:44:57 AM UTC 24 |
| Peak memory | 430952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966372399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.1966372399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.380213697 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 16590159323 ps |
| CPU time | 90.38 seconds |
| Started | Sep 11 10:39:56 AM UTC 24 |
| Finished | Sep 11 10:41:28 AM UTC 24 |
| Peak memory | 279040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380213697 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.380213697 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.3195345952 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 11521270288 ps |
| CPU time | 63.06 seconds |
| Started | Sep 11 10:39:50 AM UTC 24 |
| Finished | Sep 11 10:40:55 AM UTC 24 |
| Peak memory | 236120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195345952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3195345952 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.945831796 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 108359449617 ps |
| CPU time | 1355.16 seconds |
| Started | Sep 11 10:41:41 AM UTC 24 |
| Finished | Sep 11 11:04:32 AM UTC 24 |
| Peak memory | 1137588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945831796 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.945831796 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.2310620076 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 19298591 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 10:44:51 AM UTC 24 |
| Finished | Sep 11 10:44:53 AM UTC 24 |
| Peak memory | 226356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310620076 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2310620076 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_app.3816880909 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3553557331 ps |
| CPU time | 238.71 seconds |
| Started | Sep 11 10:42:26 AM UTC 24 |
| Finished | Sep 11 10:46:28 AM UTC 24 |
| Peak memory | 313892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816880909 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3816880909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.353691532 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 19184438529 ps |
| CPU time | 190.69 seconds |
| Started | Sep 11 10:42:49 AM UTC 24 |
| Finished | Sep 11 10:46:03 AM UTC 24 |
| Peak memory | 283228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353691532 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.353691532 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.21801943 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 14859893273 ps |
| CPU time | 1786.2 seconds |
| Started | Sep 11 10:42:13 AM UTC 24 |
| Finished | Sep 11 11:12:21 AM UTC 24 |
| Peak memory | 256604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21801943 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.21801943 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.767578449 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2361359775 ps |
| CPU time | 22.67 seconds |
| Started | Sep 11 10:43:54 AM UTC 24 |
| Finished | Sep 11 10:44:17 AM UTC 24 |
| Peak memory | 235992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767578449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.767578449 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.872092669 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2152631889 ps |
| CPU time | 18.29 seconds |
| Started | Sep 11 10:44:19 AM UTC 24 |
| Finished | Sep 11 10:44:38 AM UTC 24 |
| Peak memory | 234480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872092669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.872092669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.896533726 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 10477578071 ps |
| CPU time | 27.25 seconds |
| Started | Sep 11 10:44:32 AM UTC 24 |
| Finished | Sep 11 10:45:00 AM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896533726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.896533726 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3312832852 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2471271737 ps |
| CPU time | 96.98 seconds |
| Started | Sep 11 10:42:52 AM UTC 24 |
| Finished | Sep 11 10:44:31 AM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312832852 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3312832852 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_error.4079101067 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 16263461409 ps |
| CPU time | 271.98 seconds |
| Started | Sep 11 10:43:28 AM UTC 24 |
| Finished | Sep 11 10:48:04 AM UTC 24 |
| Peak memory | 315940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079101067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.4079101067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.336509405 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2981292542 ps |
| CPU time | 10.92 seconds |
| Started | Sep 11 10:43:40 AM UTC 24 |
| Finished | Sep 11 10:43:52 AM UTC 24 |
| Peak memory | 228000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336509405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.336509405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.2916485923 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 49733847 ps |
| CPU time | 2.19 seconds |
| Started | Sep 11 10:44:34 AM UTC 24 |
| Finished | Sep 11 10:44:37 AM UTC 24 |
| Peak memory | 234080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916485923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2916485923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.2015614777 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 22310719799 ps |
| CPU time | 540 seconds |
| Started | Sep 11 10:41:50 AM UTC 24 |
| Finished | Sep 11 10:50:57 AM UTC 24 |
| Peak memory | 553552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015614777 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2015614777 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.3477637103 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 7172360038 ps |
| CPU time | 317.65 seconds |
| Started | Sep 11 10:42:59 AM UTC 24 |
| Finished | Sep 11 10:48:21 AM UTC 24 |
| Peak memory | 383828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477637103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3477637103 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.3541570853 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2140477925 ps |
| CPU time | 183.31 seconds |
| Started | Sep 11 10:42:10 AM UTC 24 |
| Finished | Sep 11 10:45:16 AM UTC 24 |
| Peak memory | 299484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541570853 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3541570853 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.1994418810 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3731886485 ps |
| CPU time | 107.7 seconds |
| Started | Sep 11 10:41:49 AM UTC 24 |
| Finished | Sep 11 10:43:39 AM UTC 24 |
| Peak memory | 236168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994418810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1994418810 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.3418980868 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1972993980 ps |
| CPU time | 61.13 seconds |
| Started | Sep 11 10:44:38 AM UTC 24 |
| Finished | Sep 11 10:45:41 AM UTC 24 |
| Peak memory | 250272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418980868 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3418980868 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.2336581886 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 12070406 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 10:47:26 AM UTC 24 |
| Finished | Sep 11 10:47:28 AM UTC 24 |
| Peak memory | 226596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336581886 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2336581886 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_app.1422421026 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5796171976 ps |
| CPU time | 247.38 seconds |
| Started | Sep 11 10:45:42 AM UTC 24 |
| Finished | Sep 11 10:49:53 AM UTC 24 |
| Peak memory | 315992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422421026 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1422421026 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.1413256585 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 10697611412 ps |
| CPU time | 239.39 seconds |
| Started | Sep 11 10:46:04 AM UTC 24 |
| Finished | Sep 11 10:50:07 AM UTC 24 |
| Peak memory | 420436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413256585 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1413256585 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.3700449648 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 49743819149 ps |
| CPU time | 1435.51 seconds |
| Started | Sep 11 10:45:16 AM UTC 24 |
| Finished | Sep 11 11:09:29 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700449648 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3700449648 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.1286575600 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 322309550 ps |
| CPU time | 19.99 seconds |
| Started | Sep 11 10:46:47 AM UTC 24 |
| Finished | Sep 11 10:47:08 AM UTC 24 |
| Peak memory | 244412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286575600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1286575600 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.882819214 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 468402008 ps |
| CPU time | 2.05 seconds |
| Started | Sep 11 10:46:50 AM UTC 24 |
| Finished | Sep 11 10:46:53 AM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882819214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.882819214 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.377858311 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 15437531620 ps |
| CPU time | 76.98 seconds |
| Started | Sep 11 10:46:54 AM UTC 24 |
| Finished | Sep 11 10:48:13 AM UTC 24 |
| Peak memory | 236068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377858311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.377858311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.810820055 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 8617574397 ps |
| CPU time | 156.5 seconds |
| Started | Sep 11 10:46:29 AM UTC 24 |
| Finished | Sep 11 10:49:08 AM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810820055 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.810820055 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_error.289443818 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7614160445 ps |
| CPU time | 318.18 seconds |
| Started | Sep 11 10:46:44 AM UTC 24 |
| Finished | Sep 11 10:52:07 AM UTC 24 |
| Peak memory | 344660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289443818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.289443818 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.1305443524 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2060199488 ps |
| CPU time | 2.77 seconds |
| Started | Sep 11 10:46:46 AM UTC 24 |
| Finished | Sep 11 10:46:50 AM UTC 24 |
| Peak memory | 227724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305443524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1305443524 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.1890324848 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 973082278 ps |
| CPU time | 45.83 seconds |
| Started | Sep 11 10:47:01 AM UTC 24 |
| Finished | Sep 11 10:47:48 AM UTC 24 |
| Peak memory | 258672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890324848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1890324848 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.706893560 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 145350995065 ps |
| CPU time | 5497.62 seconds |
| Started | Sep 11 10:44:58 AM UTC 24 |
| Finished | Sep 11 12:17:31 PM UTC 24 |
| Peak memory | 5321336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706893560 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.706893560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.2428104904 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1122297065 ps |
| CPU time | 25.12 seconds |
| Started | Sep 11 10:46:33 AM UTC 24 |
| Finished | Sep 11 10:47:00 AM UTC 24 |
| Peak memory | 244648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428104904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2428104904 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.4265948920 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 14235698885 ps |
| CPU time | 183.46 seconds |
| Started | Sep 11 10:45:01 AM UTC 24 |
| Finished | Sep 11 10:48:08 AM UTC 24 |
| Peak memory | 373280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265948920 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.4265948920 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.879497495 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1888406193 ps |
| CPU time | 96.16 seconds |
| Started | Sep 11 10:44:54 AM UTC 24 |
| Finished | Sep 11 10:46:32 AM UTC 24 |
| Peak memory | 234072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879497495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.879497495 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.2877315978 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 24789924747 ps |
| CPU time | 415.77 seconds |
| Started | Sep 11 10:47:10 AM UTC 24 |
| Finished | Sep 11 10:54:11 AM UTC 24 |
| Peak memory | 317956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877315978 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2877315978 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.1555313361 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 7746028214 ps |
| CPU time | 106.52 seconds |
| Started | Sep 11 10:47:22 AM UTC 24 |
| Finished | Sep 11 10:49:10 AM UTC 24 |
| Peak memory | 279496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1555313361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_r and_reset.1555313361 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.2597748339 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 20357433 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 10:49:19 AM UTC 24 |
| Finished | Sep 11 10:49:21 AM UTC 24 |
| Peak memory | 224676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597748339 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2597748339 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_app.1536763890 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 76687955800 ps |
| CPU time | 519.03 seconds |
| Started | Sep 11 10:48:05 AM UTC 24 |
| Finished | Sep 11 10:56:51 AM UTC 24 |
| Peak memory | 596568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536763890 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1536763890 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2348105840 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2559523731 ps |
| CPU time | 29.56 seconds |
| Started | Sep 11 10:48:08 AM UTC 24 |
| Finished | Sep 11 10:48:40 AM UTC 24 |
| Peak memory | 240244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348105840 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2348105840 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.1690422703 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 86966367971 ps |
| CPU time | 932.97 seconds |
| Started | Sep 11 10:47:48 AM UTC 24 |
| Finished | Sep 11 11:03:33 AM UTC 24 |
| Peak memory | 256540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690422703 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1690422703 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.2044244126 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 806743687 ps |
| CPU time | 9.81 seconds |
| Started | Sep 11 10:49:07 AM UTC 24 |
| Finished | Sep 11 10:49:18 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044244126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2044244126 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.620984465 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 18832670 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 10:49:09 AM UTC 24 |
| Finished | Sep 11 10:49:12 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620984465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.620984465 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.2938618191 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4578744521 ps |
| CPU time | 24.77 seconds |
| Started | Sep 11 10:49:11 AM UTC 24 |
| Finished | Sep 11 10:49:37 AM UTC 24 |
| Peak memory | 236168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938618191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2938618191 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.176022956 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 15650562345 ps |
| CPU time | 372.57 seconds |
| Started | Sep 11 10:48:15 AM UTC 24 |
| Finished | Sep 11 10:54:33 AM UTC 24 |
| Peak memory | 346736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176022956 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.176022956 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_error.1983056562 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 158486942400 ps |
| CPU time | 380.87 seconds |
| Started | Sep 11 10:48:41 AM UTC 24 |
| Finished | Sep 11 10:55:07 AM UTC 24 |
| Peak memory | 414244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983056562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1983056562 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.3788953855 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1810759495 ps |
| CPU time | 20.04 seconds |
| Started | Sep 11 10:48:45 AM UTC 24 |
| Finished | Sep 11 10:49:06 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788953855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3788953855 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.667855052 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 125047376 ps |
| CPU time | 1.8 seconds |
| Started | Sep 11 10:49:12 AM UTC 24 |
| Finished | Sep 11 10:49:15 AM UTC 24 |
| Peak memory | 234436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667855052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.667855052 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2198625748 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 329677229099 ps |
| CPU time | 2937.48 seconds |
| Started | Sep 11 10:47:34 AM UTC 24 |
| Finished | Sep 11 11:37:03 AM UTC 24 |
| Peak memory | 3271232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198625748 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2198625748 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.2138613777 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1716865443 ps |
| CPU time | 48.35 seconds |
| Started | Sep 11 10:48:23 AM UTC 24 |
| Finished | Sep 11 10:49:13 AM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138613777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2138613777 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.3110097353 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 32666151830 ps |
| CPU time | 423.56 seconds |
| Started | Sep 11 10:47:35 AM UTC 24 |
| Finished | Sep 11 10:54:44 AM UTC 24 |
| Peak memory | 352852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110097353 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3110097353 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.2308822628 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 11558823072 ps |
| CPU time | 73.12 seconds |
| Started | Sep 11 10:47:29 AM UTC 24 |
| Finished | Sep 11 10:48:44 AM UTC 24 |
| Peak memory | 236120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308822628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2308822628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.3225850555 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 7882644392 ps |
| CPU time | 124.19 seconds |
| Started | Sep 11 10:49:13 AM UTC 24 |
| Finished | Sep 11 10:51:20 AM UTC 24 |
| Peak memory | 279136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225850555 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3225850555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.1043973201 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 14049691 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 10:51:54 AM UTC 24 |
| Finished | Sep 11 10:51:56 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043973201 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1043973201 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_app.3869428531 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1338818306 ps |
| CPU time | 68.18 seconds |
| Started | Sep 11 10:49:54 AM UTC 24 |
| Finished | Sep 11 10:51:04 AM UTC 24 |
| Peak memory | 250384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869428531 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3869428531 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.1898480656 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 60398698993 ps |
| CPU time | 187.6 seconds |
| Started | Sep 11 10:50:07 AM UTC 24 |
| Finished | Sep 11 10:53:18 AM UTC 24 |
| Peak memory | 342616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898480656 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1898480656 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.4135973679 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 30280443152 ps |
| CPU time | 803.56 seconds |
| Started | Sep 11 10:49:54 AM UTC 24 |
| Finished | Sep 11 11:03:29 AM UTC 24 |
| Peak memory | 258652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135973679 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.4135973679 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.2437544081 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 954853809 ps |
| CPU time | 3.7 seconds |
| Started | Sep 11 10:51:05 AM UTC 24 |
| Finished | Sep 11 10:51:10 AM UTC 24 |
| Peak memory | 231920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437544081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2437544081 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.2180048836 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2931319616 ps |
| CPU time | 40.45 seconds |
| Started | Sep 11 10:51:11 AM UTC 24 |
| Finished | Sep 11 10:51:53 AM UTC 24 |
| Peak memory | 252404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180048836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2180048836 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.953380802 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2311359701 ps |
| CPU time | 38.13 seconds |
| Started | Sep 11 10:51:16 AM UTC 24 |
| Finished | Sep 11 10:51:56 AM UTC 24 |
| Peak memory | 236048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953380802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.953380802 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.3331619983 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3950790451 ps |
| CPU time | 122.42 seconds |
| Started | Sep 11 10:50:56 AM UTC 24 |
| Finished | Sep 11 10:53:01 AM UTC 24 |
| Peak memory | 309836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331619983 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3331619983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_error.3441214320 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 55586706112 ps |
| CPU time | 236.09 seconds |
| Started | Sep 11 10:50:59 AM UTC 24 |
| Finished | Sep 11 10:54:58 AM UTC 24 |
| Peak memory | 449116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441214320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3441214320 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.501280042 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 960420652 ps |
| CPU time | 12.39 seconds |
| Started | Sep 11 10:51:02 AM UTC 24 |
| Finished | Sep 11 10:51:16 AM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501280042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.501280042 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.98947875 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 48288062 ps |
| CPU time | 2.25 seconds |
| Started | Sep 11 10:51:21 AM UTC 24 |
| Finished | Sep 11 10:51:24 AM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98947875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.98947875 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.2728302664 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 365418670411 ps |
| CPU time | 2435.63 seconds |
| Started | Sep 11 10:49:22 AM UTC 24 |
| Finished | Sep 11 11:30:23 AM UTC 24 |
| Peak memory | 2970200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728302664 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.2728302664 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.2250544066 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6156001306 ps |
| CPU time | 523 seconds |
| Started | Sep 11 10:50:58 AM UTC 24 |
| Finished | Sep 11 10:59:48 AM UTC 24 |
| Peak memory | 369584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250544066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2250544066 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.3736317497 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3157912259 ps |
| CPU time | 211.01 seconds |
| Started | Sep 11 10:49:38 AM UTC 24 |
| Finished | Sep 11 10:53:12 AM UTC 24 |
| Peak memory | 309852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736317497 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3736317497 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.2653324154 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2179435556 ps |
| CPU time | 31.07 seconds |
| Started | Sep 11 10:49:21 AM UTC 24 |
| Finished | Sep 11 10:49:53 AM UTC 24 |
| Peak memory | 232112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653324154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2653324154 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.37501957 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 21494027905 ps |
| CPU time | 1772.08 seconds |
| Started | Sep 11 10:51:22 AM UTC 24 |
| Finished | Sep 11 11:21:14 AM UTC 24 |
| Peak memory | 816004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37501957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.37501957 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all_with_rand_reset.1969791630 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 21885556429 ps |
| CPU time | 179.68 seconds |
| Started | Sep 11 10:51:25 AM UTC 24 |
| Finished | Sep 11 10:54:27 AM UTC 24 |
| Peak memory | 303696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1969791630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_r and_reset.1969791630 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |