Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16009085	1			T3	4		T10	140		T9	7480
all_values[1]	16009085	1			T3	4		T10	140		T9	7480
all_values[2]	16009085	1			T3	4		T10	140		T9	7480

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

529750

1

T3

4

T10

6

T9

130

auto[1]

47497505

1

T3

8

T10

414

T9

22310

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47802273

1

T3

12

T10

408

T9

22230

auto[1]

224982

1

T10

12

T9

210

T16

18

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	146415	1			T16	111		T4	2		T46	61
all_values[0]	auto[0]	auto[1]	1267	1			T16	6		T46	4		T41	2
all_values[0]	auto[1]	auto[0]	15787676	1			T3	4		T10	136		T9	7410
all_values[0]	auto[1]	auto[1]	73727	1			T10	4		T9	70		T45	5
all_values[1]	auto[0]	auto[0]	183068	1			T3	4		T9	129		T29	12
all_values[1]	auto[0]	auto[1]	916	1			T9	1		T29	1		T48	2
all_values[1]	auto[1]	auto[0]	15751023	1			T10	136		T9	7281		T16	111
all_values[1]	auto[1]	auto[1]	74078	1			T10	4		T9	69		T16	6
all_values[2]	auto[0]	auto[0]	197067	1			T10	5		T16	111		T46	8
all_values[2]	auto[0]	auto[1]	1017	1			T10	1		T16	6		T46	2
all_values[2]	auto[1]	auto[0]	15737024	1			T3	4		T10	131		T9	7410
all_values[2]	auto[1]	auto[1]	73977	1			T10	3		T9	70		T45	5