Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56296 |
1 |
|
|
T3 |
2 |
|
T10 |
6 |
|
T9 |
162 |
auto[1] |
57178 |
1 |
|
|
T65 |
4 |
|
T41 |
144 |
|
T30 |
4 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28344 |
1 |
|
|
T3 |
1 |
|
T10 |
4 |
|
T9 |
40 |
lower_val |
28219 |
1 |
|
|
T10 |
1 |
|
T9 |
43 |
|
T16 |
1 |
zero_val |
888 |
1 |
|
|
T3 |
1 |
|
T10 |
1 |
|
T9 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
42886 |
1 |
|
|
T3 |
2 |
|
T10 |
4 |
|
T9 |
86 |
lower_val |
41728 |
1 |
|
|
T10 |
2 |
|
T9 |
76 |
|
T16 |
2 |
zero_val |
28860 |
1 |
|
|
T65 |
4 |
|
T41 |
72 |
|
T18 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7033 |
1 |
|
|
T3 |
1 |
|
T10 |
3 |
|
T9 |
23 |
higher_val |
higher_val |
auto[1] |
3666 |
1 |
|
|
T41 |
11 |
|
T12 |
2 |
|
T52 |
20 |
higher_val |
lower_val |
auto[0] |
7055 |
1 |
|
|
T10 |
1 |
|
T9 |
17 |
|
T45 |
2 |
higher_val |
lower_val |
auto[1] |
3477 |
1 |
|
|
T65 |
1 |
|
T41 |
13 |
|
T30 |
2 |
higher_val |
zero_val |
auto[0] |
60 |
1 |
|
|
T65 |
1 |
|
T30 |
1 |
|
T23 |
1 |
higher_val |
zero_val |
auto[1] |
7053 |
1 |
|
|
T65 |
1 |
|
T41 |
25 |
|
T30 |
1 |
lower_val |
higher_val |
auto[0] |
7094 |
1 |
|
|
T9 |
21 |
|
T16 |
1 |
|
T46 |
2 |
lower_val |
higher_val |
auto[1] |
3611 |
1 |
|
|
T41 |
6 |
|
T12 |
9 |
|
T52 |
24 |
lower_val |
lower_val |
auto[0] |
6815 |
1 |
|
|
T10 |
1 |
|
T9 |
22 |
|
T4 |
2 |
lower_val |
lower_val |
auto[1] |
3535 |
1 |
|
|
T41 |
5 |
|
T12 |
2 |
|
T52 |
18 |
lower_val |
zero_val |
auto[0] |
48 |
1 |
|
|
T5 |
1 |
|
T144 |
1 |
|
T50 |
1 |
lower_val |
zero_val |
auto[1] |
7116 |
1 |
|
|
T41 |
10 |
|
T12 |
3 |
|
T52 |
49 |
zero_val |
higher_val |
auto[0] |
268 |
1 |
|
|
T3 |
1 |
|
T10 |
1 |
|
T9 |
1 |
zero_val |
higher_val |
auto[1] |
60 |
1 |
|
|
T85 |
1 |
|
T190 |
2 |
|
T70 |
2 |
zero_val |
lower_val |
auto[0] |
286 |
1 |
|
|
T45 |
1 |
|
T4 |
1 |
|
T29 |
1 |
zero_val |
lower_val |
auto[1] |
63 |
1 |
|
|
T190 |
1 |
|
T70 |
1 |
|
T163 |
2 |
zero_val |
zero_val |
auto[0] |
151 |
1 |
|
|
T65 |
1 |
|
T18 |
1 |
|
T30 |
1 |
zero_val |
zero_val |
auto[1] |
60 |
1 |
|
|
T32 |
1 |
|
T85 |
1 |
|
T151 |
1 |