Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16009085	1			T3	4		T10	140		T9	7480
all_pins[1]	16009085	1			T3	4		T10	140		T9	7480
all_pins[2]	16009085	1			T3	4		T10	140		T9	7480

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47656880	1			T3	12		T10	416		T9	22370
values[0x1]	370375	1			T10	4		T9	70		T45	5
transitions[0x0=>0x1]	368379	1			T10	4		T9	70		T45	5
transitions[0x1=>0x0]	368397	1			T10	4		T9	70		T45	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15935358	1			T3	4		T10	136		T9	7410
all_pins[0]	values[0x1]	73727	1			T10	4		T9	70		T45	5
all_pins[0]	transitions[0x0=>0x1]	73715	1			T10	4		T9	70		T45	5
all_pins[0]	transitions[0x1=>0x0]	5600	1			T12	3		T111	18		T25	40
all_pins[1]	values[0x0]	16003473	1			T3	4		T10	140		T9	7480
all_pins[1]	values[0x1]	5612	1			T12	3		T111	18		T25	40
all_pins[1]	transitions[0x0=>0x1]	5332	1			T12	3		T111	18		T25	40
all_pins[1]	transitions[0x1=>0x0]	290756	1			T13	2487		T31	4444		T22	624
all_pins[2]	values[0x0]	15718049	1			T3	4		T10	140		T9	7480
all_pins[2]	values[0x1]	291036	1			T13	2487		T31	4444		T22	624
all_pins[2]	transitions[0x0=>0x1]	289332	1			T13	2467		T31	4409		T22	624
all_pins[2]	transitions[0x1=>0x0]	72041	1			T10	4		T9	70		T45	5