Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17561636	1			T1	68		T3	151		T9	5
all_values[1]	17561636	1			T1	68		T3	151		T9	5
all_values[2]	17561636	1			T1	68		T3	151		T9	5

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

523160

1

T1

6

T3

305

T9

5

auto[1]

52161748

1

T1

198

T3

148

T9

10

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52470105

1

T1

189

T3

438

T9

15

auto[1]

214803

1

T1

15

T3

15

T16

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	169382	1			T1	4		T3	73		T4	2
all_values[0]	auto[0]	auto[1]	1298	1			T1	2		T3	4		T30	2
all_values[0]	auto[1]	auto[0]	17320653	1			T1	59		T3	73		T9	5
all_values[0]	auto[1]	auto[1]	70303	1			T1	3		T3	1		T16	4
all_values[1]	auto[0]	auto[0]	172004	1			T3	73		T9	5		T44	85
all_values[1]	auto[0]	auto[1]	1015	1			T3	4		T44	3		T47	1
all_values[1]	auto[1]	auto[0]	17318031	1			T1	63		T3	73		T16	127
all_values[1]	auto[1]	auto[1]	70586	1			T1	5		T3	1		T16	4
all_values[2]	auto[0]	auto[0]	178474	1			T3	146		T4	2		T47	2
all_values[2]	auto[0]	auto[1]	987	1			T3	5		T47	1		T11	7
all_values[2]	auto[1]	auto[0]	17311561	1			T1	63		T9	5		T16	127
all_values[2]	auto[1]	auto[1]	70614	1			T1	5		T16	4		T44	3