Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53022 |
1 |
|
|
T1 |
2 |
|
T3 |
6 |
|
T9 |
2 |
auto[1] |
56918 |
1 |
|
|
T1 |
4 |
|
T42 |
208 |
|
T47 |
288 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27396 |
1 |
|
|
T1 |
3 |
|
T3 |
2 |
|
T4 |
32 |
lower_val |
27306 |
1 |
|
|
T3 |
3 |
|
T16 |
3 |
|
T44 |
1 |
zero_val |
886 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
40558 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T16 |
2 |
lower_val |
40818 |
1 |
|
|
T1 |
2 |
|
T3 |
4 |
|
T16 |
4 |
zero_val |
28564 |
1 |
|
|
T1 |
2 |
|
T9 |
2 |
|
T42 |
102 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6488 |
1 |
|
|
T3 |
1 |
|
T4 |
16 |
|
T30 |
33 |
higher_val |
higher_val |
auto[1] |
3585 |
1 |
|
|
T1 |
1 |
|
T42 |
23 |
|
T47 |
14 |
higher_val |
lower_val |
auto[0] |
6582 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
16 |
higher_val |
lower_val |
auto[1] |
3606 |
1 |
|
|
T42 |
9 |
|
T47 |
17 |
|
T50 |
13 |
higher_val |
zero_val |
auto[0] |
54 |
1 |
|
|
T35 |
1 |
|
T163 |
1 |
|
T177 |
1 |
higher_val |
zero_val |
auto[1] |
7081 |
1 |
|
|
T1 |
1 |
|
T42 |
22 |
|
T47 |
37 |
lower_val |
higher_val |
auto[0] |
6489 |
1 |
|
|
T3 |
1 |
|
T16 |
1 |
|
T44 |
1 |
lower_val |
higher_val |
auto[1] |
3525 |
1 |
|
|
T42 |
15 |
|
T47 |
21 |
|
T50 |
19 |
lower_val |
lower_val |
auto[0] |
6526 |
1 |
|
|
T3 |
2 |
|
T16 |
2 |
|
T4 |
18 |
lower_val |
lower_val |
auto[1] |
3630 |
1 |
|
|
T42 |
15 |
|
T47 |
19 |
|
T50 |
10 |
lower_val |
zero_val |
auto[0] |
57 |
1 |
|
|
T42 |
1 |
|
T48 |
1 |
|
T66 |
1 |
lower_val |
zero_val |
auto[1] |
7079 |
1 |
|
|
T42 |
25 |
|
T47 |
41 |
|
T50 |
39 |
zero_val |
higher_val |
auto[0] |
281 |
1 |
|
|
T16 |
1 |
|
T30 |
1 |
|
T47 |
1 |
zero_val |
higher_val |
auto[1] |
60 |
1 |
|
|
T22 |
1 |
|
T48 |
1 |
|
T72 |
1 |
zero_val |
lower_val |
auto[0] |
268 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T44 |
1 |
zero_val |
lower_val |
auto[1] |
58 |
1 |
|
|
T50 |
1 |
|
T22 |
1 |
|
T163 |
1 |
zero_val |
zero_val |
auto[0] |
162 |
1 |
|
|
T9 |
1 |
|
T42 |
1 |
|
T10 |
1 |
zero_val |
zero_val |
auto[1] |
57 |
1 |
|
|
T50 |
1 |
|
T48 |
1 |
|
T72 |
1 |