Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17561636	1			T1	68		T3	151		T9	5
all_pins[1]	17561636	1			T1	68		T3	151		T9	5
all_pins[2]	17561636	1			T1	68		T3	151		T9	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	52274489	1			T1	201		T3	452		T9	15
values[0x1]	410419	1			T1	3		T3	1		T16	4
transitions[0x0=>0x1]	407962	1			T1	3		T3	1		T16	4
transitions[0x1=>0x0]	407987	1			T1	3		T3	1		T16	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17491333	1			T1	65		T3	150		T9	5
all_pins[0]	values[0x1]	70303	1			T1	3		T3	1		T16	4
all_pins[0]	transitions[0x0=>0x1]	70293	1			T1	3		T3	1		T16	4
all_pins[0]	transitions[0x1=>0x0]	5434	1			T11	8		T48	2		T15	14
all_pins[1]	values[0x0]	17556192	1			T1	68		T3	151		T9	5
all_pins[1]	values[0x1]	5444	1			T11	8		T48	2		T15	14
all_pins[1]	transitions[0x0=>0x1]	5023	1			T11	8		T48	2		T15	14
all_pins[1]	transitions[0x1=>0x0]	334251	1			T11	2		T14	7639		T31	2486
all_pins[2]	values[0x0]	17226964	1			T1	68		T3	151		T9	5
all_pins[2]	values[0x1]	334672	1			T11	2		T14	7639		T31	2490
all_pins[2]	transitions[0x0=>0x1]	332646	1			T11	2		T14	7581		T31	2473
all_pins[2]	transitions[0x1=>0x0]	68302	1			T1	3		T3	1		T16	4