| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.40 | 97.88 | 92.58 | 99.89 | 78.17 | 95.51 | 98.91 | 97.88 |
| T760 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3238496385 | Sep 24 08:53:41 AM UTC 24 | Sep 24 08:53:45 AM UTC 24 | 96251145 ps | ||
| T761 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3124991838 | Sep 24 08:53:42 AM UTC 24 | Sep 24 08:53:45 AM UTC 24 | 103079755 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3048577551 | Sep 24 08:53:39 AM UTC 24 | Sep 24 08:53:46 AM UTC 24 | 189546401 ps | ||
| T762 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.478075606 | Sep 24 08:53:43 AM UTC 24 | Sep 24 08:53:46 AM UTC 24 | 233501009 ps | ||
| T763 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2090936276 | Sep 24 08:53:43 AM UTC 24 | Sep 24 08:53:46 AM UTC 24 | 86025995 ps | ||
| T764 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4148169222 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:46 AM UTC 24 | 64716966 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2848328533 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:47 AM UTC 24 | 168885405 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4002974413 | Sep 24 08:53:43 AM UTC 24 | Sep 24 08:53:47 AM UTC 24 | 216835730 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1002052301 | Sep 24 08:53:41 AM UTC 24 | Sep 24 08:53:47 AM UTC 24 | 1008922014 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1091492484 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:47 AM UTC 24 | 57891935 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3716941864 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:47 AM UTC 24 | 98822727 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.226522344 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:47 AM UTC 24 | 56458088 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2281360662 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:47 AM UTC 24 | 42351024 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.411640727 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:48 AM UTC 24 | 296407965 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1918138622 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:48 AM UTC 24 | 31072247 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.820412702 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:48 AM UTC 24 | 35600229 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.4174152121 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:48 AM UTC 24 | 21421830 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3979921410 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:48 AM UTC 24 | 176792674 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3257364530 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:48 AM UTC 24 | 104540657 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2913949242 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:48 AM UTC 24 | 87176327 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1446262355 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 78828749 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2634750784 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 20107572 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3085353424 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 239750443 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3770883493 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 31522969 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3338798012 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 29768447 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1718453209 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 57837195 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.861175344 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 22901084 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3610049263 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:49 AM UTC 24 | 44254514 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2290302043 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:50 AM UTC 24 | 25716151 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1446109078 | Sep 24 08:53:48 AM UTC 24 | Sep 24 08:53:50 AM UTC 24 | 36838539 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.854295788 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:50 AM UTC 24 | 47384463 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1857722763 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:50 AM UTC 24 | 98817038 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1839994919 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:51 AM UTC 24 | 125890359 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3271025527 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:51 AM UTC 24 | 55324373 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3448817739 | Sep 24 08:53:48 AM UTC 24 | Sep 24 08:53:51 AM UTC 24 | 179347002 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.338147050 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:51 AM UTC 24 | 750979784 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2853000580 | Sep 24 08:53:44 AM UTC 24 | Sep 24 08:53:51 AM UTC 24 | 1022304598 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2312778874 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:51 AM UTC 24 | 184165372 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1349143858 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:52 AM UTC 24 | 451794301 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3481821490 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:52 AM UTC 24 | 17508772 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.2353188283 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:52 AM UTC 24 | 13898874 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2836972417 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:52 AM UTC 24 | 35067443 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.401779159 | Sep 24 08:53:46 AM UTC 24 | Sep 24 08:53:52 AM UTC 24 | 773448635 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3222710337 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 267474771 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.22944774 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 213346294 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2796288965 | Sep 24 08:53:47 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 562502281 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.940229468 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 31505237 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3784811477 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 112097388 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3375750586 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 72550822 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3389289532 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 36740079 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.928031623 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:53 AM UTC 24 | 47986117 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.577760458 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 327350946 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2453446797 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 201767895 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.447168246 | Sep 24 08:53:52 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 74525113 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.4008354860 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 391303500 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.4134624095 | Sep 24 08:53:52 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 21126679 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1455364027 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 384438563 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3625160248 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 336220264 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1353110139 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 114470025 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1702187077 | Sep 24 08:53:52 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 53545926 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.357070381 | Sep 24 08:53:49 AM UTC 24 | Sep 24 08:53:54 AM UTC 24 | 255054914 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4164162540 | Sep 24 08:53:52 AM UTC 24 | Sep 24 08:53:55 AM UTC 24 | 214400805 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.837159231 | Sep 24 08:53:50 AM UTC 24 | Sep 24 08:53:55 AM UTC 24 | 92820650 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2006249483 | Sep 24 08:53:52 AM UTC 24 | Sep 24 08:53:55 AM UTC 24 | 63470857 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2163407647 | Sep 24 08:53:53 AM UTC 24 | Sep 24 08:53:55 AM UTC 24 | 30408276 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2460492634 | Sep 24 08:53:53 AM UTC 24 | Sep 24 08:53:56 AM UTC 24 | 33638629 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3752112799 | Sep 24 08:53:53 AM UTC 24 | Sep 24 08:53:56 AM UTC 24 | 34404862 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2696647430 | Sep 24 08:53:54 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 98421945 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.488165601 | Sep 24 08:53:54 AM UTC 24 | Sep 24 08:53:57 AM UTC 24 | 51284479 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2410426969 | Sep 24 08:53:54 AM UTC 24 | Sep 24 08:53:57 AM UTC 24 | 20629165 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3904074085 | Sep 24 08:53:53 AM UTC 24 | Sep 24 08:53:57 AM UTC 24 | 45691149 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2050881702 | Sep 24 08:53:57 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 23493531 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1528829051 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 19121919 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.895132404 | Sep 24 08:53:51 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 709484229 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1591572517 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 31597666 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.171720650 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 16694857 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.642738828 | Sep 24 08:53:53 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 214951580 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2051221325 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 13031546 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.837025803 | Sep 24 08:53:54 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 133174258 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.143541019 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 150830942 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1621605195 | Sep 24 08:53:54 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 301019964 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1336163714 | Sep 24 08:53:55 AM UTC 24 | Sep 24 08:53:58 AM UTC 24 | 70474035 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2545122760 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:53:59 AM UTC 24 | 132518787 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.160249526 | Sep 24 08:53:53 AM UTC 24 | Sep 24 08:53:59 AM UTC 24 | 178480975 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2356290652 | Sep 24 08:53:54 AM UTC 24 | Sep 24 08:53:59 AM UTC 24 | 24341451 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.16262636 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:53:59 AM UTC 24 | 25987396 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3742047369 | Sep 24 08:53:53 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 539593865 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.924161225 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 86802787 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.809786909 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 186052896 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1719760341 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 670354037 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1546065989 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 60031545 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.956542657 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 114366769 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2188771877 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:54:00 AM UTC 24 | 447758902 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.880263718 | Sep 24 08:53:57 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 294119291 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2823887925 | Sep 24 08:53:56 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 102907247 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2304429053 | Sep 24 08:53:54 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 442283168 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.211948517 | Sep 24 08:53:58 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 14425778 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1414858261 | Sep 24 08:53:58 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 12427910 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1366514142 | Sep 24 08:53:59 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 50237066 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.679977064 | Sep 24 08:53:58 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 16359697 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2599991386 | Sep 24 08:53:59 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 15806136 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2986695855 | Sep 24 08:53:58 AM UTC 24 | Sep 24 08:54:01 AM UTC 24 | 40942213 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2365997362 | Sep 24 08:53:57 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 118665246 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.928321454 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 70535026 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.498431140 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 14126156 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3474540249 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 25592463 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.550782944 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 53695130 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.4084434790 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 42495461 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1515998834 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 13547175 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2166059067 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 30536442 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.256367295 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:02 AM UTC 24 | 31803758 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.73967596 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:03 AM UTC 24 | 40006809 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2042022066 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:03 AM UTC 24 | 24108519 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2238698170 | Sep 24 08:54:00 AM UTC 24 | Sep 24 08:54:03 AM UTC 24 | 12612698 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2974508782 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:03 AM UTC 24 | 22810050 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.487888644 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:03 AM UTC 24 | 30883164 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3762425719 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:03 AM UTC 24 | 11685101 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.2180400694 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:03 AM UTC 24 | 16406248 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3501128310 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:04 AM UTC 24 | 33593616 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1580533208 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:04 AM UTC 24 | 11915825 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.4147918229 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:04 AM UTC 24 | 27355582 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.117189615 | Sep 24 08:54:02 AM UTC 24 | Sep 24 08:54:04 AM UTC 24 | 27793413 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.781027347 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:04 AM UTC 24 | 29949663 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.4055713907 | Sep 24 08:54:01 AM UTC 24 | Sep 24 08:54:04 AM UTC 24 | 43305295 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.450861305 | Sep 24 08:53:37 AM UTC 24 | Sep 24 08:54:04 AM UTC 24 | 8888204440 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3336694090 | Sep 24 08:54:03 AM UTC 24 | Sep 24 08:54:05 AM UTC 24 | 15266373 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3919992382 | Sep 24 08:54:03 AM UTC 24 | Sep 24 08:54:08 AM UTC 24 | 154418364 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3380730779 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9026202034 ps |
| CPU time | 30.94 seconds |
| Started | Sep 24 12:46:16 PM UTC 24 |
| Finished | Sep 24 12:46:48 PM UTC 24 |
| Peak memory | 236700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380730779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3380730779 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.748681445 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4332823967 ps |
| CPU time | 40.37 seconds |
| Started | Sep 24 12:46:11 PM UTC 24 |
| Finished | Sep 24 12:46:53 PM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748681445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.748681445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.2990502039 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6541267855 ps |
| CPU time | 173.67 seconds |
| Started | Sep 24 12:46:14 PM UTC 24 |
| Finished | Sep 24 12:49:11 PM UTC 24 |
| Peak memory | 353640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990502039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2990502039 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.113383218 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 283299434 ps |
| CPU time | 4.96 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:16 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113383218 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.113383218 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.3285299291 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 125534139 ps |
| CPU time | 2.19 seconds |
| Started | Sep 24 12:46:16 PM UTC 24 |
| Finished | Sep 24 12:46:19 PM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285299291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3285299291 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.992743856 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 991959410 ps |
| CPU time | 103.89 seconds |
| Started | Sep 24 12:47:07 PM UTC 24 |
| Finished | Sep 24 12:48:53 PM UTC 24 |
| Peak memory | 281636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=992743856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_ra nd_reset.992743856 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.1382548765 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3367165544 ps |
| CPU time | 49.81 seconds |
| Started | Sep 24 12:48:19 PM UTC 24 |
| Finished | Sep 24 12:49:10 PM UTC 24 |
| Peak memory | 278648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382548765 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1382548765 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.1653042207 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2175735564 ps |
| CPU time | 5.73 seconds |
| Started | Sep 24 12:46:15 PM UTC 24 |
| Finished | Sep 24 12:46:22 PM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653042207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.1653042207 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_error.1165994271 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 44351294639 ps |
| CPU time | 383.53 seconds |
| Started | Sep 24 12:48:00 PM UTC 24 |
| Finished | Sep 24 12:54:29 PM UTC 24 |
| Peak memory | 521252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165994271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1165994271 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2308113717 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 106017855 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:11 AM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308113717 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.2308 113717 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.222861826 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 151969246951 ps |
| CPU time | 267.24 seconds |
| Started | Sep 24 12:49:50 PM UTC 24 |
| Finished | Sep 24 12:54:21 PM UTC 24 |
| Peak memory | 390152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222861826 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.222861826 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.2719678829 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 35447351 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 12:50:49 PM UTC 24 |
| Finished | Sep 24 12:50:52 PM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719678829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2719678829 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2759334595 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 13123756 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 08:53:11 AM UTC 24 |
| Finished | Sep 24 08:53:16 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759334595 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2759334595 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.4108866071 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 164937094 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 12:46:15 PM UTC 24 |
| Finished | Sep 24 12:46:18 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108866071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.4108866071 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.2732268251 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 41044868 ps |
| CPU time | 2.37 seconds |
| Started | Sep 24 01:32:25 PM UTC 24 |
| Finished | Sep 24 01:32:28 PM UTC 24 |
| Peak memory | 234568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732268251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2732268251 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.828530021 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 120870977 ps |
| CPU time | 2.34 seconds |
| Started | Sep 24 01:36:59 PM UTC 24 |
| Finished | Sep 24 01:37:02 PM UTC 24 |
| Peak memory | 234788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828530021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.828530021 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.4118758580 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 478489965 ps |
| CPU time | 3.92 seconds |
| Started | Sep 24 12:56:56 PM UTC 24 |
| Finished | Sep 24 12:57:01 PM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118758580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.4118758580 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.1368752474 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 94801019 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 12:47:03 PM UTC 24 |
| Finished | Sep 24 12:47:06 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368752474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1368752474 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1292965368 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 110029886 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:53:09 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292965368 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1292965368 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.3622360923 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 917760346 ps |
| CPU time | 5.57 seconds |
| Started | Sep 24 08:53:15 AM UTC 24 |
| Finished | Sep 24 08:53:42 AM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622360923 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.3622360923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.3977827076 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 100905369 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 01:18:45 PM UTC 24 |
| Finished | Sep 24 01:18:48 PM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977827076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3977827076 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.416380495 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 41613574 ps |
| CPU time | 2.69 seconds |
| Started | Sep 24 01:29:52 PM UTC 24 |
| Finished | Sep 24 01:29:56 PM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416380495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.416380495 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.3451775215 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 55204232 ps |
| CPU time | 2.61 seconds |
| Started | Sep 24 01:39:19 PM UTC 24 |
| Finished | Sep 24 01:39:23 PM UTC 24 |
| Peak memory | 234660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451775215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.3451775215 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.2442926730 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15388107 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 12:46:17 PM UTC 24 |
| Finished | Sep 24 12:46:19 PM UTC 24 |
| Peak memory | 226656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442926730 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2442926730 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.3389622752 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2496404142 ps |
| CPU time | 53.6 seconds |
| Started | Sep 24 12:46:19 PM UTC 24 |
| Finished | Sep 24 12:47:15 PM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389622752 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3389622752 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.161785171 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 90548013 ps |
| CPU time | 2.59 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:14 AM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161785171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.16178 5171 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.3653391572 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 206805189272 ps |
| CPU time | 481.5 seconds |
| Started | Sep 24 01:11:36 PM UTC 24 |
| Finished | Sep 24 01:19:44 PM UTC 24 |
| Peak memory | 494828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653391572 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3653391572 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.545818919 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 16808381406 ps |
| CPU time | 97.73 seconds |
| Started | Sep 24 12:46:14 PM UTC 24 |
| Finished | Sep 24 12:47:54 PM UTC 24 |
| Peak memory | 275692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545818919 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.545818919 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3481821490 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 17508772 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:52 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481821490 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3481821490 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2304429053 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 442283168 ps |
| CPU time | 4.81 seconds |
| Started | Sep 24 08:53:54 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304429053 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2304429053 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.701532875 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8914048195 ps |
| CPU time | 401.27 seconds |
| Started | Sep 24 01:11:24 PM UTC 24 |
| Finished | Sep 24 01:18:11 PM UTC 24 |
| Peak memory | 355432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701532875 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.701532875 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.587997670 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 65405981856 ps |
| CPU time | 663.41 seconds |
| Started | Sep 24 12:47:18 PM UTC 24 |
| Finished | Sep 24 12:58:30 PM UTC 24 |
| Peak memory | 252960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587997670 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.587997670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_error.1558987152 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5724841360 ps |
| CPU time | 485.39 seconds |
| Started | Sep 24 12:46:15 PM UTC 24 |
| Finished | Sep 24 12:54:27 PM UTC 24 |
| Peak memory | 392404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558987152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1558987152 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.4008354860 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 391303500 ps |
| CPU time | 3.13 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008354860 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.4008354860 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.58052689 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9285767292 ps |
| CPU time | 347.88 seconds |
| Started | Sep 24 12:47:55 PM UTC 24 |
| Finished | Sep 24 12:53:48 PM UTC 24 |
| Peak memory | 339512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58052689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.58052689 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_app.2281636935 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3256135886 ps |
| CPU time | 199.57 seconds |
| Started | Sep 24 01:34:37 PM UTC 24 |
| Finished | Sep 24 01:38:00 PM UTC 24 |
| Peak memory | 283620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281636935 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2281636935 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1621605195 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 301019964 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 08:53:54 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 226272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621605195 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.162 1605195 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.3744125099 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 57849958276 ps |
| CPU time | 405.48 seconds |
| Started | Sep 24 01:52:56 PM UTC 24 |
| Finished | Sep 24 01:59:48 PM UTC 24 |
| Peak memory | 504808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744125099 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3744125099 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.264045670 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3142444504 ps |
| CPU time | 115.41 seconds |
| Started | Sep 24 12:46:16 PM UTC 24 |
| Finished | Sep 24 12:48:14 PM UTC 24 |
| Peak memory | 279740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=264045670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_ra nd_reset.264045670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.1384981658 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 69650153759 ps |
| CPU time | 443.68 seconds |
| Started | Sep 24 12:46:12 PM UTC 24 |
| Finished | Sep 24 12:53:41 PM UTC 24 |
| Peak memory | 580644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384981658 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1384981658 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.3468861993 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4819097559 ps |
| CPU time | 8.63 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:20 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468861993 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3468861993 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2774776405 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1918166718 ps |
| CPU time | 17.22 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:28 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774776405 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2774776405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2576331887 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 20831129 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576331887 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2576331887 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3191781517 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 77117867 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:13 AM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3191781517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_ rw_with_rand_reset.3191781517 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.598074586 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 22209438 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598074586 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.598074586 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.3350509055 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 29368289 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350509055 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3350509055 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.332481787 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 15427296 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:53:09 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332481787 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.332481787 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.78005396 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 137344103 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:13 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78005396 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.78005396 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3044351524 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 354133144 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044351524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.3044351524 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.4094867533 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 250462239 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 08:53:09 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094867533 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.4094867533 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.4149109487 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2170772136 ps |
| CPU time | 9.21 seconds |
| Started | Sep 24 08:53:11 AM UTC 24 |
| Finished | Sep 24 08:53:25 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149109487 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.4149109487 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2307880917 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1934790822 ps |
| CPU time | 17.77 seconds |
| Started | Sep 24 08:53:11 AM UTC 24 |
| Finished | Sep 24 08:53:33 AM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307880917 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2307880917 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2302609554 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 18783632 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:53:11 AM UTC 24 |
| Finished | Sep 24 08:53:16 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302609554 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2302609554 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.3711488947 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 15359257 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:53:11 AM UTC 24 |
| Finished | Sep 24 08:53:16 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711488947 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3711488947 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.1371725468 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 134817757 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371725468 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.1371725468 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1363726165 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 41207939 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363726165 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1363726165 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.536111423 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 97855983 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 08:53:10 AM UTC 24 |
| Finished | Sep 24 08:53:12 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536111423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.536111423 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.3349005442 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 70806605 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 08:53:11 AM UTC 24 |
| Finished | Sep 24 08:53:14 AM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349005442 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3349005442 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1638902259 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 70862022 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 08:53:11 AM UTC 24 |
| Finished | Sep 24 08:53:18 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638902259 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.1638902259 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2634750784 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 20107572 ps |
| CPU time | 1.93 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 228604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2634750784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem _rw_with_rand_reset.2634750784 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.4174152121 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 21421830 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:48 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174152121 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.4174152121 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.820412702 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 35600229 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:48 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820412702 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.820412702 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1446262355 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 78828749 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446262355 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1446262355 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1091492484 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 57891935 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:47 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091492484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.1091492484 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.411640727 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 296407965 ps |
| CPU time | 2.35 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:48 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411640727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.4116 40727 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3770883493 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 31522969 ps |
| CPU time | 2.39 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 226040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770883493 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3770883493 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.401779159 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 773448635 ps |
| CPU time | 5.69 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:52 AM UTC 24 |
| Peak memory | 226000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401779159 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.401779159 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1857722763 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 98817038 ps |
| CPU time | 2.19 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:50 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1857722763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem _rw_with_rand_reset.1857722763 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.861175344 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 22901084 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861175344 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.861175344 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3338798012 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 29768447 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338798012 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3338798012 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.854295788 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 47384463 ps |
| CPU time | 2.14 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:50 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854295788 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.854295788 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3257364530 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 104540657 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:48 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257364530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.3257364530 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3085353424 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 239750443 ps |
| CPU time | 2.14 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085353424 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.308 5353424 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2312778874 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 184165372 ps |
| CPU time | 4.52 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:51 AM UTC 24 |
| Peak memory | 225988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312778874 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2312778874 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1839994919 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 125890359 ps |
| CPU time | 3.6 seconds |
| Started | Sep 24 08:53:46 AM UTC 24 |
| Finished | Sep 24 08:53:51 AM UTC 24 |
| Peak memory | 226120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839994919 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1839994919 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3448817739 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 179347002 ps |
| CPU time | 2.59 seconds |
| Started | Sep 24 08:53:48 AM UTC 24 |
| Finished | Sep 24 08:53:51 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3448817739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem _rw_with_rand_reset.3448817739 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2290302043 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 25716151 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:50 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290302043 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2290302043 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3610049263 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 44254514 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610049263 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3610049263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3271025527 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 55324373 ps |
| CPU time | 2.11 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:51 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271025527 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.3271025527 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1718453209 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 57837195 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:49 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718453209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.1718453209 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.338147050 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 750979784 ps |
| CPU time | 2.99 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:51 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338147050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.3381 47050 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2796288965 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 562502281 ps |
| CPU time | 4.24 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796288965 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2796288965 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1349143858 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 451794301 ps |
| CPU time | 3.25 seconds |
| Started | Sep 24 08:53:47 AM UTC 24 |
| Finished | Sep 24 08:53:52 AM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349143858 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1349143858 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.577760458 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 327350946 ps |
| CPU time | 2.75 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 232052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=577760458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_ rw_with_rand_reset.577760458 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2836972417 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 35067443 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:52 AM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836972417 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2836972417 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1455364027 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 384438563 ps |
| CPU time | 3.21 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455364027 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.1455364027 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1446109078 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 36838539 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:53:48 AM UTC 24 |
| Finished | Sep 24 08:53:50 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446109078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1446109078 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.22944774 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 213346294 ps |
| CPU time | 1.88 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 228588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22944774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.22944 774 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.357070381 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 255054914 ps |
| CPU time | 3.71 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357070381 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.357070381 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3625160248 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 336220264 ps |
| CPU time | 2.89 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3625160248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem _rw_with_rand_reset.3625160248 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.940229468 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 31505237 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940229468 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.940229468 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.2353188283 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 13898874 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:52 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353188283 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2353188283 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3375750586 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 72550822 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375750586 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.3375750586 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3222710337 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 267474771 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222710337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3222710337 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3784811477 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 112097388 ps |
| CPU time | 2.06 seconds |
| Started | Sep 24 08:53:49 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784811477 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.378 4811477 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.928031623 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 47986117 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928031623 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.928031623 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2453446797 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 201767895 ps |
| CPU time | 2.7 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453446797 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2453446797 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2006249483 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 63470857 ps |
| CPU time | 2.38 seconds |
| Started | Sep 24 08:53:52 AM UTC 24 |
| Finished | Sep 24 08:53:55 AM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2006249483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem _rw_with_rand_reset.2006249483 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.4134624095 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 21126679 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:53:52 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134624095 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.4134624095 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.447168246 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 74525113 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:53:52 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447168246 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.447168246 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1702187077 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 53545926 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:53:52 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702187077 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1702187077 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3389289532 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 36740079 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:53 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389289532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.3389289532 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1353110139 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 114470025 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:54 AM UTC 24 |
| Peak memory | 230696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353110139 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.135 3110139 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.837159231 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 92820650 ps |
| CPU time | 3.4 seconds |
| Started | Sep 24 08:53:50 AM UTC 24 |
| Finished | Sep 24 08:53:55 AM UTC 24 |
| Peak memory | 226128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837159231 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.837159231 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.895132404 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 709484229 ps |
| CPU time | 5.01 seconds |
| Started | Sep 24 08:53:51 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 225872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895132404 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.895132404 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.642738828 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 214951580 ps |
| CPU time | 2.49 seconds |
| Started | Sep 24 08:53:53 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=642738828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_ rw_with_rand_reset.642738828 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2460492634 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 33638629 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:53:53 AM UTC 24 |
| Finished | Sep 24 08:53:56 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460492634 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2460492634 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2163407647 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 30408276 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:53:53 AM UTC 24 |
| Finished | Sep 24 08:53:55 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163407647 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2163407647 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.160249526 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 178480975 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 08:53:53 AM UTC 24 |
| Finished | Sep 24 08:53:59 AM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160249526 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.160249526 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4164162540 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 214400805 ps |
| CPU time | 1.77 seconds |
| Started | Sep 24 08:53:52 AM UTC 24 |
| Finished | Sep 24 08:53:55 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164162540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.4164162540 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3752112799 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 34404862 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 08:53:53 AM UTC 24 |
| Finished | Sep 24 08:53:56 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752112799 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.375 2112799 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3904074085 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 45691149 ps |
| CPU time | 3.07 seconds |
| Started | Sep 24 08:53:53 AM UTC 24 |
| Finished | Sep 24 08:53:57 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904074085 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3904074085 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3742047369 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 539593865 ps |
| CPU time | 5.2 seconds |
| Started | Sep 24 08:53:53 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742047369 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3742047369 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1336163714 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 70474035 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:53:55 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1336163714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem _rw_with_rand_reset.1336163714 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.837025803 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 133174258 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:53:54 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837025803 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.837025803 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2410426969 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 20629165 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:53:54 AM UTC 24 |
| Finished | Sep 24 08:53:57 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410426969 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2410426969 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2356290652 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 24341451 ps |
| CPU time | 2.17 seconds |
| Started | Sep 24 08:53:54 AM UTC 24 |
| Finished | Sep 24 08:53:59 AM UTC 24 |
| Peak memory | 226124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356290652 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2356290652 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.488165601 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 51284479 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:53:54 AM UTC 24 |
| Finished | Sep 24 08:53:57 AM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488165601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.488165601 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2696647430 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 98421945 ps |
| CPU time | 3.26 seconds |
| Started | Sep 24 08:53:54 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696647430 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2696647430 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.16262636 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 25987396 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:53:59 AM UTC 24 |
| Peak memory | 232328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=16262636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_r w_with_rand_reset.16262636 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2051221325 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 13031546 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 224476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051221325 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2051221325 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1528829051 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 19121919 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528829051 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1528829051 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2188771877 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 447758902 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188771877 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.2188771877 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1591572517 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 31597666 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591572517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.1591572517 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.809786909 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 186052896 ps |
| CPU time | 3.15 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809786909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.8097 86909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1546065989 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 60031545 ps |
| CPU time | 3.44 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546065989 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1546065989 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2823887925 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 102907247 ps |
| CPU time | 4.16 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 226200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823887925 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2823887925 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2365997362 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 118665246 ps |
| CPU time | 2.7 seconds |
| Started | Sep 24 08:53:57 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2365997362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem _rw_with_rand_reset.2365997362 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.143541019 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 150830942 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143541019 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.143541019 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.171720650 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 16694857 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:53:58 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171720650 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.171720650 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.880263718 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 294119291 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:53:57 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880263718 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.880263718 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2545122760 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 132518787 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:53:59 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545122760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2545122760 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1719760341 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 670354037 ps |
| CPU time | 2.87 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 230636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719760341 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.171 9760341 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.956542657 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 114366769 ps |
| CPU time | 3.04 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956542657 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.956542657 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.924161225 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 86802787 ps |
| CPU time | 2.6 seconds |
| Started | Sep 24 08:53:56 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924161225 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.924161225 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3915859300 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 75873947 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:42 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915859300 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3915859300 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.4142521331 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 150357415 ps |
| CPU time | 8.53 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:42 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142521331 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.4142521331 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.702260034 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 45592951 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:38 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702260034 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.702260034 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2168461973 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 44398807 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:39 AM UTC 24 |
| Peak memory | 228600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2168461973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_ rw_with_rand_reset.2168461973 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.856677425 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 20956782 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:38 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856677425 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.856677425 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3133642506 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 33270852 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:38 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133642506 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3133642506 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3308224316 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 43944761 ps |
| CPU time | 2.53 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:40 AM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308224316 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3308224316 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.2507678262 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 114427808 ps |
| CPU time | 2.75 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:41 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507678262 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2507678262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.439181149 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 95427645 ps |
| CPU time | 4.36 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:41 AM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439181149 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.439181149 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2050881702 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 23493531 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 08:53:57 AM UTC 24 |
| Finished | Sep 24 08:54:00 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050881702 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2050881702 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2986695855 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 40942213 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 08:53:58 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986695855 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2986695855 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1414858261 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 12427910 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:53:58 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414858261 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1414858261 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.679977064 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 16359697 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:53:58 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679977064 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.679977064 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.211948517 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 14425778 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:53:58 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211948517 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.211948517 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2599991386 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 15806136 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:53:59 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599991386 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2599991386 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1366514142 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 50237066 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:53:59 AM UTC 24 |
| Finished | Sep 24 08:54:01 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366514142 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1366514142 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.498431140 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 14126156 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498431140 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.498431140 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3474540249 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 25592463 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474540249 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3474540249 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.928321454 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 70535026 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928321454 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.928321454 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1053199267 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 546010453 ps |
| CPU time | 9.34 seconds |
| Started | Sep 24 08:53:18 AM UTC 24 |
| Finished | Sep 24 08:53:30 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053199267 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1053199267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.1570098321 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1452419139 ps |
| CPU time | 7.92 seconds |
| Started | Sep 24 08:53:17 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570098321 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1570098321 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.510136473 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 27460903 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:53:17 AM UTC 24 |
| Finished | Sep 24 08:53:40 AM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510136473 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.510136473 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2828347694 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 145980642 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 08:53:26 AM UTC 24 |
| Finished | Sep 24 08:53:38 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2828347694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_ rw_with_rand_reset.2828347694 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.3378725757 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 43630628 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:53:17 AM UTC 24 |
| Finished | Sep 24 08:53:40 AM UTC 24 |
| Peak memory | 224188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378725757 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3378725757 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3915582115 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 14020439 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:53:16 AM UTC 24 |
| Finished | Sep 24 08:53:38 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915582115 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3915582115 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3157177991 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 156185960 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:53:14 AM UTC 24 |
| Finished | Sep 24 08:53:38 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157177991 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3157177991 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.2558042661 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 23355459 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 08:53:14 AM UTC 24 |
| Finished | Sep 24 08:53:37 AM UTC 24 |
| Peak memory | 224456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558042661 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2558042661 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1745614212 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 85565617 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:53:20 AM UTC 24 |
| Finished | Sep 24 08:53:40 AM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745614212 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.1745614212 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.336690049 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 53555036 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:53:13 AM UTC 24 |
| Finished | Sep 24 08:53:38 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336690049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.336690049 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2171069711 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 161437808 ps |
| CPU time | 2.37 seconds |
| Started | Sep 24 08:53:14 AM UTC 24 |
| Finished | Sep 24 08:53:39 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171069711 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2171069711 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2166059067 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 30536442 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166059067 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2166059067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.550782944 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 53695130 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550782944 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.550782944 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1515998834 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 13547175 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515998834 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1515998834 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.73967596 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 40006809 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:03 AM UTC 24 |
| Peak memory | 224436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73967596 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.73967596 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.256367295 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 31803758 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256367295 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.256367295 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2042022066 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 24108519 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:03 AM UTC 24 |
| Peak memory | 224404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042022066 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2042022066 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2238698170 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 12612698 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:03 AM UTC 24 |
| Peak memory | 224548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238698170 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2238698170 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.4084434790 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 42495461 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 08:54:00 AM UTC 24 |
| Finished | Sep 24 08:54:02 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084434790 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.4084434790 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.487888644 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 30883164 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:03 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487888644 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.487888644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3501128310 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 33593616 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:04 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501128310 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3501128310 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.4006039029 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 380859282 ps |
| CPU time | 5.97 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:44 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006039029 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.4006039029 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.450861305 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 8888204440 ps |
| CPU time | 25.48 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:54:04 AM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450861305 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.450861305 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2116784928 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 27250580 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:39 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116784928 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2116784928 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2164775189 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 41402610 ps |
| CPU time | 1.88 seconds |
| Started | Sep 24 08:53:38 AM UTC 24 |
| Finished | Sep 24 08:53:41 AM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2164775189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_ rw_with_rand_reset.2164775189 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.170614381 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 58716157 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:39 AM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170614381 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.170614381 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.823417720 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 17649431 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:39 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823417720 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.823417720 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.946911074 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 113423096 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:39 AM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946911074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.946911074 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.2774389008 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 29947169 ps |
| CPU time | 0.77 seconds |
| Started | Sep 24 08:53:34 AM UTC 24 |
| Finished | Sep 24 08:53:36 AM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774389008 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2774389008 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2162751682 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 47816783 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:40 AM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162751682 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.2162751682 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.612723292 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 23809805 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:53:29 AM UTC 24 |
| Finished | Sep 24 08:53:39 AM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612723292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.612723292 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3183640392 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 59768433 ps |
| CPU time | 2.66 seconds |
| Started | Sep 24 08:53:31 AM UTC 24 |
| Finished | Sep 24 08:53:41 AM UTC 24 |
| Peak memory | 230636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183640392 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.3183 640392 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.1352111807 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 65323126 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:40 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352111807 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1352111807 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1442073706 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 148457157 ps |
| CPU time | 3.13 seconds |
| Started | Sep 24 08:53:37 AM UTC 24 |
| Finished | Sep 24 08:53:41 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442073706 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.1442073706 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3762425719 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 11685101 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:03 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762425719 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3762425719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2974508782 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 22810050 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:03 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974508782 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2974508782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.4055713907 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 43305295 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:04 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055713907 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.4055713907 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.2180400694 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 16406248 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:03 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180400694 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2180400694 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.781027347 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 29949663 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:04 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781027347 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.781027347 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.4147918229 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 27355582 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:04 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147918229 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.4147918229 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1580533208 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 11915825 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 08:54:01 AM UTC 24 |
| Finished | Sep 24 08:54:04 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580533208 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1580533208 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.117189615 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 27793413 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:54:02 AM UTC 24 |
| Finished | Sep 24 08:54:04 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117189615 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.117189615 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3336694090 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 15266373 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:54:03 AM UTC 24 |
| Finished | Sep 24 08:54:05 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336694090 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3336694090 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3919992382 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 154418364 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:54:03 AM UTC 24 |
| Finished | Sep 24 08:54:08 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919992382 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3919992382 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4147658555 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 33196883 ps |
| CPU time | 2.34 seconds |
| Started | Sep 24 08:53:40 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4147658555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_ rw_with_rand_reset.4147658555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.3984621977 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 17937841 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:53:40 AM UTC 24 |
| Finished | Sep 24 08:53:42 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984621977 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3984621977 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2225318861 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 18687482 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:53:39 AM UTC 24 |
| Finished | Sep 24 08:53:42 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225318861 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2225318861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2576412694 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 25881093 ps |
| CPU time | 1.92 seconds |
| Started | Sep 24 08:53:40 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576412694 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.2576412694 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4078017133 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 27952560 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:53:38 AM UTC 24 |
| Finished | Sep 24 08:53:41 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078017133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.4078017133 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2035749445 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 55626754 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 08:53:38 AM UTC 24 |
| Finished | Sep 24 08:53:41 AM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035749445 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.2035 749445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3098994702 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 137778958 ps |
| CPU time | 2.64 seconds |
| Started | Sep 24 08:53:39 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098994702 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3098994702 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3048577551 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 189546401 ps |
| CPU time | 5.51 seconds |
| Started | Sep 24 08:53:39 AM UTC 24 |
| Finished | Sep 24 08:53:46 AM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048577551 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.3048577551 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3238496385 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 96251145 ps |
| CPU time | 3.1 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3238496385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_ rw_with_rand_reset.3238496385 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.1491753685 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 20809964 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491753685 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1491753685 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3717170169 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 75226001 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717170169 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3717170169 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1198296325 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 337916482 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198296325 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1198296325 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3481400949 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 34445171 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 08:53:40 AM UTC 24 |
| Finished | Sep 24 08:53:42 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481400949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.3481400949 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.940471583 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 134921146 ps |
| CPU time | 2.5 seconds |
| Started | Sep 24 08:53:40 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940471583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.94047 1583 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.684433987 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 67827006 ps |
| CPU time | 2.6 seconds |
| Started | Sep 24 08:53:40 AM UTC 24 |
| Finished | Sep 24 08:53:43 AM UTC 24 |
| Peak memory | 226000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684433987 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.684433987 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1002052301 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1008922014 ps |
| CPU time | 4.6 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:47 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002052301 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.1002052301 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2090936276 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 86025995 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:46 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2090936276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_ rw_with_rand_reset.2090936276 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.1100928596 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 28179067 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:53:42 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100928596 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1100928596 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.903711724 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 19179751 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:53:42 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903711724 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.903711724 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3124991838 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 103079755 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:53:42 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124991838 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3124991838 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2269657595 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 73055246 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:44 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269657595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2269657595 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.907616234 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 397497257 ps |
| CPU time | 2.6 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907616234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.90761 6234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1248048663 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 35120198 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:44 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248048663 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1248048663 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1702298719 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 241668742 ps |
| CPU time | 3.27 seconds |
| Started | Sep 24 08:53:41 AM UTC 24 |
| Finished | Sep 24 08:53:46 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702298719 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1702298719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2913949242 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 87176327 ps |
| CPU time | 3.22 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:48 AM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2913949242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_ rw_with_rand_reset.2913949242 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.4105264762 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 28529851 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105264762 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4105264762 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.977499837 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 13975221 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977499837 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.977499837 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.588586534 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 80206199 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:46 AM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588586534 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.588586534 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.26810026 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 24522436 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:45 AM UTC 24 |
| Peak memory | 224328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26810026 -assert nopostproc + UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.26810026 +enable_masking=1 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.478075606 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 233501009 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:46 AM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478075606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.47807 5606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2380506534 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 235282629 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:46 AM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380506534 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2380506534 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4002974413 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 216835730 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 08:53:43 AM UTC 24 |
| Finished | Sep 24 08:53:47 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002974413 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.4002974413 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1918138622 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 31072247 ps |
| CPU time | 2.47 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:48 AM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1918138622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_ rw_with_rand_reset.1918138622 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2848328533 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 168885405 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:47 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848328533 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2848328533 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4148169222 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 64716966 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:46 AM UTC 24 |
| Peak memory | 224572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148169222 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.4148169222 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2281360662 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 42351024 ps |
| CPU time | 2.11 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:47 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281360662 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.2281360662 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3716941864 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 98822727 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:47 AM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716941864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.3716941864 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3979921410 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 176792674 ps |
| CPU time | 2.96 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:48 AM UTC 24 |
| Peak memory | 226208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979921410 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.3979 921410 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.226522344 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 56458088 ps |
| CPU time | 2.25 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:47 AM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226522344 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.226522344 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2853000580 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1022304598 ps |
| CPU time | 6.04 seconds |
| Started | Sep 24 08:53:44 AM UTC 24 |
| Finished | Sep 24 08:53:51 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853000580 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.2853000580 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_app.2332973773 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 20557095438 ps |
| CPU time | 193.08 seconds |
| Started | Sep 24 12:46:14 PM UTC 24 |
| Finished | Sep 24 12:49:30 PM UTC 24 |
| Peak memory | 341008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332973773 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2332973773 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.2591398243 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10745565529 ps |
| CPU time | 251.61 seconds |
| Started | Sep 24 12:46:14 PM UTC 24 |
| Finished | Sep 24 12:50:29 PM UTC 24 |
| Peak memory | 402596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591398243 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2591398243 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.3080374280 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 29071934625 ps |
| CPU time | 1505.35 seconds |
| Started | Sep 24 12:46:12 PM UTC 24 |
| Finished | Sep 24 01:11:35 PM UTC 24 |
| Peak memory | 275372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080374280 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3080374280 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.961156844 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5529363666 ps |
| CPU time | 53.14 seconds |
| Started | Sep 24 12:46:16 PM UTC 24 |
| Finished | Sep 24 12:47:10 PM UTC 24 |
| Peak memory | 236304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961156844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.961156844 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.628540958 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 249778572009 ps |
| CPU time | 5061.08 seconds |
| Started | Sep 24 12:46:12 PM UTC 24 |
| Finished | Sep 24 02:11:29 PM UTC 24 |
| Peak memory | 4707560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628540958 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.628540958 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.1380040779 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 18018104368 ps |
| CPU time | 65.44 seconds |
| Started | Sep 24 12:46:17 PM UTC 24 |
| Finished | Sep 24 12:47:24 PM UTC 24 |
| Peak memory | 290944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380040779 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1380040779 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.756698345 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 21522535778 ps |
| CPU time | 2099.41 seconds |
| Started | Sep 24 12:46:16 PM UTC 24 |
| Finished | Sep 24 01:21:43 PM UTC 24 |
| Peak memory | 724348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756698345 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.756698345 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.202513545 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 289760597 ps |
| CPU time | 2.56 seconds |
| Started | Sep 24 12:46:14 PM UTC 24 |
| Finished | Sep 24 12:46:17 PM UTC 24 |
| Peak memory | 236540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202513545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.202513545 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3292545256 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 133423411 ps |
| CPU time | 3.55 seconds |
| Started | Sep 24 12:46:14 PM UTC 24 |
| Finished | Sep 24 12:46:18 PM UTC 24 |
| Peak memory | 236600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292545256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3292545256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.982231408 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8488752705 ps |
| CPU time | 52.88 seconds |
| Started | Sep 24 12:46:12 PM UTC 24 |
| Finished | Sep 24 12:47:06 PM UTC 24 |
| Peak memory | 263308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982231408 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.982231408 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2455040326 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 308848409850 ps |
| CPU time | 2944.23 seconds |
| Started | Sep 24 12:46:12 PM UTC 24 |
| Finished | Sep 24 01:35:52 PM UTC 24 |
| Peak memory | 2964520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455040326 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2455040326 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.2356132326 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2453070314 ps |
| CPU time | 39.12 seconds |
| Started | Sep 24 12:46:13 PM UTC 24 |
| Finished | Sep 24 12:46:54 PM UTC 24 |
| Peak memory | 236504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356132326 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2356132326 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.390027725 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 102176991378 ps |
| CPU time | 1783.25 seconds |
| Started | Sep 24 12:46:13 PM UTC 24 |
| Finished | Sep 24 01:16:17 PM UTC 24 |
| Peak memory | 1721172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390027725 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.390027725 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.2224966396 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 293693722298 ps |
| CPU time | 3434.83 seconds |
| Started | Sep 24 12:46:13 PM UTC 24 |
| Finished | Sep 24 01:44:09 PM UTC 24 |
| Peak memory | 3599188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224966396 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2224966396 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.244196713 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 62619522243 ps |
| CPU time | 2617.83 seconds |
| Started | Sep 24 12:46:14 PM UTC 24 |
| Finished | Sep 24 01:30:24 PM UTC 24 |
| Peak memory | 3099648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244196713 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.244196713 +ena ble_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.891047610 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 16785094 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 12:47:11 PM UTC 24 |
| Finished | Sep 24 12:47:13 PM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891047610 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.891047610 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_app.3795327651 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 14011540444 ps |
| CPU time | 173.94 seconds |
| Started | Sep 24 12:46:33 PM UTC 24 |
| Finished | Sep 24 12:49:30 PM UTC 24 |
| Peak memory | 347408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795327651 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3795327651 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.2217440472 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 22584252481 ps |
| CPU time | 365.68 seconds |
| Started | Sep 24 12:46:33 PM UTC 24 |
| Finished | Sep 24 12:52:45 PM UTC 24 |
| Peak memory | 326624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217440472 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2217440472 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.11554416 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 42385505001 ps |
| CPU time | 1258.37 seconds |
| Started | Sep 24 12:46:19 PM UTC 24 |
| Finished | Sep 24 01:07:34 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11554416 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.11554416 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.1396648029 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 158521161 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 12:46:59 PM UTC 24 |
| Finished | Sep 24 12:47:02 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396648029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1396648029 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.1448743990 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 25007436767 ps |
| CPU time | 68.01 seconds |
| Started | Sep 24 12:47:05 PM UTC 24 |
| Finished | Sep 24 12:48:15 PM UTC 24 |
| Peak memory | 236580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448743990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1448743990 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.1808144113 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 66783069283 ps |
| CPU time | 297.86 seconds |
| Started | Sep 24 12:46:48 PM UTC 24 |
| Finished | Sep 24 12:51:51 PM UTC 24 |
| Peak memory | 422864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808144113 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1808144113 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_error.2185113892 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1391044996 ps |
| CPU time | 29.81 seconds |
| Started | Sep 24 12:46:54 PM UTC 24 |
| Finished | Sep 24 12:47:26 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185113892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2185113892 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.3240083123 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3956028427 ps |
| CPU time | 14.73 seconds |
| Started | Sep 24 12:46:55 PM UTC 24 |
| Finished | Sep 24 12:47:12 PM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240083123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3240083123 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.3960785544 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 53887888 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 12:47:07 PM UTC 24 |
| Finished | Sep 24 12:47:10 PM UTC 24 |
| Peak memory | 233964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960785544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3960785544 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.3754640926 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 82964492303 ps |
| CPU time | 4197.35 seconds |
| Started | Sep 24 12:46:18 PM UTC 24 |
| Finished | Sep 24 01:57:06 PM UTC 24 |
| Peak memory | 4091012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754640926 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.3754640926 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.1719391627 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9144449428 ps |
| CPU time | 303.17 seconds |
| Started | Sep 24 12:46:53 PM UTC 24 |
| Finished | Sep 24 12:52:01 PM UTC 24 |
| Peak memory | 419212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719391627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1719391627 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.18161237 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10122217586 ps |
| CPU time | 49.07 seconds |
| Started | Sep 24 12:47:10 PM UTC 24 |
| Finished | Sep 24 12:48:01 PM UTC 24 |
| Peak memory | 278708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18161237 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.18161237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.1423564199 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 50166829495 ps |
| CPU time | 494.46 seconds |
| Started | Sep 24 12:46:18 PM UTC 24 |
| Finished | Sep 24 12:54:39 PM UTC 24 |
| Peak memory | 566356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423564199 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1423564199 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.3322184111 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 11130877873 ps |
| CPU time | 73.93 seconds |
| Started | Sep 24 12:46:17 PM UTC 24 |
| Finished | Sep 24 12:47:33 PM UTC 24 |
| Peak memory | 236524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322184111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3322184111 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.1940708599 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 133012344797 ps |
| CPU time | 1149.69 seconds |
| Started | Sep 24 12:47:07 PM UTC 24 |
| Finished | Sep 24 01:06:30 PM UTC 24 |
| Peak memory | 1160776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940708599 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1940708599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2269115480 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 310827526 ps |
| CPU time | 4.33 seconds |
| Started | Sep 24 12:46:27 PM UTC 24 |
| Finished | Sep 24 12:46:32 PM UTC 24 |
| Peak memory | 236452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269115480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.2269115480 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.1601714069 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 112516030 ps |
| CPU time | 3.32 seconds |
| Started | Sep 24 12:46:28 PM UTC 24 |
| Finished | Sep 24 12:46:33 PM UTC 24 |
| Peak memory | 236660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601714069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1601714069 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.995148118 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 67442530488 ps |
| CPU time | 2310.71 seconds |
| Started | Sep 24 12:46:20 PM UTC 24 |
| Finished | Sep 24 01:25:18 PM UTC 24 |
| Peak memory | 1129356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995148118 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.995148118 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.2551946615 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 13785314869 ps |
| CPU time | 1610.46 seconds |
| Started | Sep 24 12:46:21 PM UTC 24 |
| Finished | Sep 24 01:13:30 PM UTC 24 |
| Peak memory | 922720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551946615 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2551946615 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.4068377886 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 83334591757 ps |
| CPU time | 1771.76 seconds |
| Started | Sep 24 12:46:21 PM UTC 24 |
| Finished | Sep 24 01:16:15 PM UTC 24 |
| Peak memory | 1715364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068377886 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.4068377886 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.1081169765 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 288156718770 ps |
| CPU time | 3493.05 seconds |
| Started | Sep 24 12:46:23 PM UTC 24 |
| Finished | Sep 24 01:45:16 PM UTC 24 |
| Peak memory | 3681164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081169765 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1081169765 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1620727134 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 113583784697 ps |
| CPU time | 2678.88 seconds |
| Started | Sep 24 12:46:27 PM UTC 24 |
| Finished | Sep 24 01:31:36 PM UTC 24 |
| Peak memory | 2935692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620727134 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1620727134 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.2926746012 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 18045918 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 01:09:44 PM UTC 24 |
| Finished | Sep 24 01:09:46 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926746012 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2926746012 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_app.1285950741 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 8835964615 ps |
| CPU time | 47.82 seconds |
| Started | Sep 24 01:09:14 PM UTC 24 |
| Finished | Sep 24 01:10:03 PM UTC 24 |
| Peak memory | 267300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285950741 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1285950741 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.2401608529 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 104579232238 ps |
| CPU time | 1156.34 seconds |
| Started | Sep 24 01:09:12 PM UTC 24 |
| Finished | Sep 24 01:28:44 PM UTC 24 |
| Peak memory | 265444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401608529 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2401608529 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.4124060898 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 142378097 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 01:09:32 PM UTC 24 |
| Finished | Sep 24 01:09:35 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124060898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.4124060898 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.123378041 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 9284326554 ps |
| CPU time | 69.68 seconds |
| Started | Sep 24 01:09:33 PM UTC 24 |
| Finished | Sep 24 01:10:45 PM UTC 24 |
| Peak memory | 236488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123378041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.123378041 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.2720935901 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 43051176454 ps |
| CPU time | 478.02 seconds |
| Started | Sep 24 01:09:18 PM UTC 24 |
| Finished | Sep 24 01:17:23 PM UTC 24 |
| Peak memory | 527404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720935901 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2720935901 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_error.1964154025 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 20258030634 ps |
| CPU time | 271.04 seconds |
| Started | Sep 24 01:09:22 PM UTC 24 |
| Finished | Sep 24 01:13:58 PM UTC 24 |
| Peak memory | 463964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964154025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1964154025 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.677084670 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2774026057 ps |
| CPU time | 17.4 seconds |
| Started | Sep 24 01:09:31 PM UTC 24 |
| Finished | Sep 24 01:09:50 PM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677084670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.677084670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.2264032066 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 27994483 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 01:09:36 PM UTC 24 |
| Finished | Sep 24 01:09:40 PM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264032066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2264032066 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.801560205 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 340982646 ps |
| CPU time | 17.27 seconds |
| Started | Sep 24 01:09:03 PM UTC 24 |
| Finished | Sep 24 01:09:21 PM UTC 24 |
| Peak memory | 246880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801560205 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.801560205 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.766817234 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 91627860 ps |
| CPU time | 4.36 seconds |
| Started | Sep 24 01:09:08 PM UTC 24 |
| Finished | Sep 24 01:09:13 PM UTC 24 |
| Peak memory | 236356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766817234 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.766817234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.2963418876 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 525206739 ps |
| CPU time | 16.56 seconds |
| Started | Sep 24 01:08:49 PM UTC 24 |
| Finished | Sep 24 01:09:07 PM UTC 24 |
| Peak memory | 236400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963418876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2963418876 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.837929444 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 39297767681 ps |
| CPU time | 1014.43 seconds |
| Started | Sep 24 01:09:40 PM UTC 24 |
| Finished | Sep 24 01:26:47 PM UTC 24 |
| Peak memory | 1056360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837929444 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.837929444 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.3297894173 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 47298697 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 01:11:03 PM UTC 24 |
| Finished | Sep 24 01:11:05 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297894173 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3297894173 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_app.3889280907 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4698313067 ps |
| CPU time | 353.07 seconds |
| Started | Sep 24 01:09:58 PM UTC 24 |
| Finished | Sep 24 01:15:56 PM UTC 24 |
| Peak memory | 336980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889280907 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3889280907 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.2017163595 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 21217613074 ps |
| CPU time | 995.69 seconds |
| Started | Sep 24 01:09:51 PM UTC 24 |
| Finished | Sep 24 01:26:39 PM UTC 24 |
| Peak memory | 263200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017163595 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2017163595 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.150106504 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3910656179 ps |
| CPU time | 36.3 seconds |
| Started | Sep 24 01:10:45 PM UTC 24 |
| Finished | Sep 24 01:11:23 PM UTC 24 |
| Peak memory | 236328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150106504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.150106504 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.314407084 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 67943657 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 01:10:54 PM UTC 24 |
| Finished | Sep 24 01:10:56 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314407084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.314407084 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.1808102599 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4212601088 ps |
| CPU time | 210.89 seconds |
| Started | Sep 24 01:10:04 PM UTC 24 |
| Finished | Sep 24 01:13:38 PM UTC 24 |
| Peak memory | 300124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808102599 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1808102599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_error.2388391489 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 16332408639 ps |
| CPU time | 45.92 seconds |
| Started | Sep 24 01:10:14 PM UTC 24 |
| Finished | Sep 24 01:11:02 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388391489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2388391489 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.2411535665 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 967192884 ps |
| CPU time | 10.48 seconds |
| Started | Sep 24 01:10:41 PM UTC 24 |
| Finished | Sep 24 01:10:53 PM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411535665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2411535665 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.3966460475 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 248900407 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 01:10:57 PM UTC 24 |
| Finished | Sep 24 01:11:00 PM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966460475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3966460475 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.2050743114 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 39906820260 ps |
| CPU time | 1367.23 seconds |
| Started | Sep 24 01:09:47 PM UTC 24 |
| Finished | Sep 24 01:32:51 PM UTC 24 |
| Peak memory | 1598500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050743114 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.2050743114 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.4141489559 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 19243295956 ps |
| CPU time | 425.79 seconds |
| Started | Sep 24 01:09:49 PM UTC 24 |
| Finished | Sep 24 01:17:01 PM UTC 24 |
| Peak memory | 486428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141489559 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.4141489559 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.733712463 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 8356430248 ps |
| CPU time | 77.09 seconds |
| Started | Sep 24 01:09:46 PM UTC 24 |
| Finished | Sep 24 01:11:05 PM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733712463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.733712463 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.1012117852 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 16406438475 ps |
| CPU time | 1395.61 seconds |
| Started | Sep 24 01:11:01 PM UTC 24 |
| Finished | Sep 24 01:34:36 PM UTC 24 |
| Peak memory | 830832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012117852 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1012117852 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.1492879122 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 28951619 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 01:12:05 PM UTC 24 |
| Finished | Sep 24 01:12:08 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492879122 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1492879122 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_app.2016045132 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 17046281306 ps |
| CPU time | 232.87 seconds |
| Started | Sep 24 01:11:33 PM UTC 24 |
| Finished | Sep 24 01:15:30 PM UTC 24 |
| Peak memory | 316592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016045132 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2016045132 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.89141494 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 15458645596 ps |
| CPU time | 470.08 seconds |
| Started | Sep 24 01:11:26 PM UTC 24 |
| Finished | Sep 24 01:19:24 PM UTC 24 |
| Peak memory | 252956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89141494 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.89141494 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2860823180 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 865642215 ps |
| CPU time | 39.77 seconds |
| Started | Sep 24 01:11:49 PM UTC 24 |
| Finished | Sep 24 01:12:30 PM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860823180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2860823180 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3868025787 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 18247694 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 01:11:59 PM UTC 24 |
| Finished | Sep 24 01:12:01 PM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868025787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3868025787 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_error.244385498 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4610115161 ps |
| CPU time | 240.72 seconds |
| Started | Sep 24 01:11:37 PM UTC 24 |
| Finished | Sep 24 01:15:42 PM UTC 24 |
| Peak memory | 302056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244385498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.244385498 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.783715446 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2596642205 ps |
| CPU time | 13.21 seconds |
| Started | Sep 24 01:11:44 PM UTC 24 |
| Finished | Sep 24 01:11:58 PM UTC 24 |
| Peak memory | 228696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783715446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.783715446 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.1341900297 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 40574260 ps |
| CPU time | 2.19 seconds |
| Started | Sep 24 01:12:01 PM UTC 24 |
| Finished | Sep 24 01:12:05 PM UTC 24 |
| Peak memory | 234528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341900297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1341900297 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.1537092718 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 417712163961 ps |
| CPU time | 3387.51 seconds |
| Started | Sep 24 01:11:06 PM UTC 24 |
| Finished | Sep 24 02:08:10 PM UTC 24 |
| Peak memory | 3706032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537092718 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.1537092718 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.3728235837 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 766126531 ps |
| CPU time | 35.63 seconds |
| Started | Sep 24 01:11:06 PM UTC 24 |
| Finished | Sep 24 01:11:43 PM UTC 24 |
| Peak memory | 236508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728235837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3728235837 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.3528836042 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3229625880 ps |
| CPU time | 112.98 seconds |
| Started | Sep 24 01:12:02 PM UTC 24 |
| Finished | Sep 24 01:13:57 PM UTC 24 |
| Peak memory | 279920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528836042 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3528836042 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.2944949830 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 98922598 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 01:14:20 PM UTC 24 |
| Finished | Sep 24 01:14:22 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944949830 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2944949830 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_app.3949521336 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 20691697288 ps |
| CPU time | 381.15 seconds |
| Started | Sep 24 01:13:37 PM UTC 24 |
| Finished | Sep 24 01:20:04 PM UTC 24 |
| Peak memory | 318500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949521336 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3949521336 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.2161962460 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 92439647 ps |
| CPU time | 13.56 seconds |
| Started | Sep 24 01:13:31 PM UTC 24 |
| Finished | Sep 24 01:13:46 PM UTC 24 |
| Peak memory | 236444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161962460 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2161962460 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.10491192 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 320017415 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 01:13:59 PM UTC 24 |
| Finished | Sep 24 01:14:01 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10491192 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.10491192 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.659679222 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 376127878 ps |
| CPU time | 32.57 seconds |
| Started | Sep 24 01:13:59 PM UTC 24 |
| Finished | Sep 24 01:14:33 PM UTC 24 |
| Peak memory | 234736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659679222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.659679222 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.1189467914 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 45956920662 ps |
| CPU time | 433.81 seconds |
| Started | Sep 24 01:13:39 PM UTC 24 |
| Finished | Sep 24 01:21:00 PM UTC 24 |
| Peak memory | 464024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189467914 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1189467914 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_error.2086195935 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 9921684229 ps |
| CPU time | 76.71 seconds |
| Started | Sep 24 01:13:47 PM UTC 24 |
| Finished | Sep 24 01:15:06 PM UTC 24 |
| Peak memory | 285936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086195935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2086195935 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.3091988463 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3247078457 ps |
| CPU time | 19.94 seconds |
| Started | Sep 24 01:13:58 PM UTC 24 |
| Finished | Sep 24 01:14:19 PM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091988463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3091988463 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.272220023 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 503786913 ps |
| CPU time | 43.26 seconds |
| Started | Sep 24 01:14:02 PM UTC 24 |
| Finished | Sep 24 01:14:47 PM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272220023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.272220023 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.760714432 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 217043983283 ps |
| CPU time | 3332.51 seconds |
| Started | Sep 24 01:12:32 PM UTC 24 |
| Finished | Sep 24 02:08:43 PM UTC 24 |
| Peak memory | 3062972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760714432 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.760714432 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.864860069 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 31278542772 ps |
| CPU time | 128.27 seconds |
| Started | Sep 24 01:12:41 PM UTC 24 |
| Finished | Sep 24 01:14:51 PM UTC 24 |
| Peak memory | 320732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864860069 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.864860069 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.2864039782 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6234031852 ps |
| CPU time | 104.28 seconds |
| Started | Sep 24 01:12:09 PM UTC 24 |
| Finished | Sep 24 01:13:57 PM UTC 24 |
| Peak memory | 236636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864039782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2864039782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.1011204123 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 17946290940 ps |
| CPU time | 1076.29 seconds |
| Started | Sep 24 01:14:14 PM UTC 24 |
| Finished | Sep 24 01:32:23 PM UTC 24 |
| Peak memory | 367952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011204123 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1011204123 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.4238573350 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 59344394 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 01:15:37 PM UTC 24 |
| Finished | Sep 24 01:15:39 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238573350 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.4238573350 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_app.3612465646 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 26335835152 ps |
| CPU time | 182.78 seconds |
| Started | Sep 24 01:14:47 PM UTC 24 |
| Finished | Sep 24 01:17:53 PM UTC 24 |
| Peak memory | 312280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612465646 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3612465646 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.1722554564 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4033210228 ps |
| CPU time | 251.5 seconds |
| Started | Sep 24 01:14:44 PM UTC 24 |
| Finished | Sep 24 01:19:00 PM UTC 24 |
| Peak memory | 240608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722554564 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1722554564 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.1623179592 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 282646685 ps |
| CPU time | 8.88 seconds |
| Started | Sep 24 01:15:22 PM UTC 24 |
| Finished | Sep 24 01:15:32 PM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623179592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1623179592 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.2409226888 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 23473397 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 01:15:31 PM UTC 24 |
| Finished | Sep 24 01:15:33 PM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409226888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2409226888 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.1558158371 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 17339867840 ps |
| CPU time | 148.45 seconds |
| Started | Sep 24 01:14:52 PM UTC 24 |
| Finished | Sep 24 01:17:24 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558158371 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1558158371 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_error.3898912161 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 11109054671 ps |
| CPU time | 468.08 seconds |
| Started | Sep 24 01:15:07 PM UTC 24 |
| Finished | Sep 24 01:23:02 PM UTC 24 |
| Peak memory | 521176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898912161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3898912161 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.3534268290 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5636948719 ps |
| CPU time | 10.88 seconds |
| Started | Sep 24 01:15:09 PM UTC 24 |
| Finished | Sep 24 01:15:21 PM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534268290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3534268290 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.3288237215 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 168931798 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 01:15:33 PM UTC 24 |
| Finished | Sep 24 01:15:36 PM UTC 24 |
| Peak memory | 232504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288237215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3288237215 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.917574283 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 850857475360 ps |
| CPU time | 5107.38 seconds |
| Started | Sep 24 01:14:29 PM UTC 24 |
| Finished | Sep 24 02:40:33 PM UTC 24 |
| Peak memory | 4824196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917574283 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.917574283 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.3967982776 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 6616597703 ps |
| CPU time | 502.83 seconds |
| Started | Sep 24 01:14:33 PM UTC 24 |
| Finished | Sep 24 01:23:03 PM UTC 24 |
| Peak memory | 390124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967982776 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3967982776 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.1598708422 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 488508089 ps |
| CPU time | 19.2 seconds |
| Started | Sep 24 01:14:23 PM UTC 24 |
| Finished | Sep 24 01:14:43 PM UTC 24 |
| Peak memory | 236428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598708422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1598708422 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.616922199 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 55929830202 ps |
| CPU time | 1417.84 seconds |
| Started | Sep 24 01:15:34 PM UTC 24 |
| Finished | Sep 24 01:39:30 PM UTC 24 |
| Peak memory | 1012768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616922199 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.616922199 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.609027202 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 26507757 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 01:16:49 PM UTC 24 |
| Finished | Sep 24 01:16:51 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609027202 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.609027202 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_app.3627646242 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1836905709 ps |
| CPU time | 17.13 seconds |
| Started | Sep 24 01:15:57 PM UTC 24 |
| Finished | Sep 24 01:16:15 PM UTC 24 |
| Peak memory | 246692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627646242 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3627646242 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.4023380064 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 77071187937 ps |
| CPU time | 1238.29 seconds |
| Started | Sep 24 01:15:55 PM UTC 24 |
| Finished | Sep 24 01:36:49 PM UTC 24 |
| Peak memory | 263244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023380064 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.4023380064 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.405385813 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 190316821 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 01:16:25 PM UTC 24 |
| Finished | Sep 24 01:16:28 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405385813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.405385813 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.925024069 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 52133913 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 01:16:29 PM UTC 24 |
| Finished | Sep 24 01:16:31 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925024069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.925024069 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.226531429 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 6472575722 ps |
| CPU time | 299.14 seconds |
| Started | Sep 24 01:16:16 PM UTC 24 |
| Finished | Sep 24 01:21:20 PM UTC 24 |
| Peak memory | 330760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226531429 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.226531429 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_error.3414350436 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5444382195 ps |
| CPU time | 154.87 seconds |
| Started | Sep 24 01:16:16 PM UTC 24 |
| Finished | Sep 24 01:18:54 PM UTC 24 |
| Peak memory | 283680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414350436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3414350436 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.3832505327 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 280156487 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 01:16:18 PM UTC 24 |
| Finished | Sep 24 01:16:24 PM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832505327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3832505327 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.3720015534 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 387956479 ps |
| CPU time | 14.98 seconds |
| Started | Sep 24 01:16:32 PM UTC 24 |
| Finished | Sep 24 01:16:48 PM UTC 24 |
| Peak memory | 246684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720015534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3720015534 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.2161707138 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 88479164127 ps |
| CPU time | 837.02 seconds |
| Started | Sep 24 01:15:42 PM UTC 24 |
| Finished | Sep 24 01:29:50 PM UTC 24 |
| Peak memory | 1125388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161707138 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.2161707138 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.1799945785 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 40488136158 ps |
| CPU time | 367.57 seconds |
| Started | Sep 24 01:15:52 PM UTC 24 |
| Finished | Sep 24 01:22:05 PM UTC 24 |
| Peak memory | 455712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799945785 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1799945785 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.1188218222 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 18087329507 ps |
| CPU time | 62.21 seconds |
| Started | Sep 24 01:15:40 PM UTC 24 |
| Finished | Sep 24 01:16:44 PM UTC 24 |
| Peak memory | 236784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188218222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1188218222 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.3066383771 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 63625746674 ps |
| CPU time | 625.1 seconds |
| Started | Sep 24 01:16:45 PM UTC 24 |
| Finished | Sep 24 01:27:18 PM UTC 24 |
| Peak memory | 335168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066383771 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3066383771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.2214091849 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 43334567 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 01:18:50 PM UTC 24 |
| Finished | Sep 24 01:18:52 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214091849 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2214091849 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_app.4251017528 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 9397811790 ps |
| CPU time | 258.29 seconds |
| Started | Sep 24 01:17:36 PM UTC 24 |
| Finished | Sep 24 01:21:59 PM UTC 24 |
| Peak memory | 371772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251017528 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.4251017528 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.4186783667 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 38376346440 ps |
| CPU time | 640.11 seconds |
| Started | Sep 24 01:17:24 PM UTC 24 |
| Finished | Sep 24 01:28:13 PM UTC 24 |
| Peak memory | 244720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186783667 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.4186783667 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3355562255 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 137008820 ps |
| CPU time | 11.23 seconds |
| Started | Sep 24 01:18:39 PM UTC 24 |
| Finished | Sep 24 01:18:51 PM UTC 24 |
| Peak memory | 236120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355562255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3355562255 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.538767239 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 74816024 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 01:18:41 PM UTC 24 |
| Finished | Sep 24 01:18:44 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538767239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.538767239 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.4289729930 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2366063776 ps |
| CPU time | 42.48 seconds |
| Started | Sep 24 01:17:55 PM UTC 24 |
| Finished | Sep 24 01:18:39 PM UTC 24 |
| Peak memory | 261160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289729930 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.4289729930 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_error.3052707250 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1912313563 ps |
| CPU time | 184.57 seconds |
| Started | Sep 24 01:18:13 PM UTC 24 |
| Finished | Sep 24 01:21:21 PM UTC 24 |
| Peak memory | 295852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052707250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3052707250 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.4112599647 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1269593877 ps |
| CPU time | 16.09 seconds |
| Started | Sep 24 01:18:30 PM UTC 24 |
| Finished | Sep 24 01:18:48 PM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112599647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.4112599647 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.964806054 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 169508663489 ps |
| CPU time | 4371.87 seconds |
| Started | Sep 24 01:17:02 PM UTC 24 |
| Finished | Sep 24 02:30:51 PM UTC 24 |
| Peak memory | 3988512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964806054 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.964806054 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.999897085 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1287867527 ps |
| CPU time | 64.18 seconds |
| Started | Sep 24 01:17:23 PM UTC 24 |
| Finished | Sep 24 01:18:29 PM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999897085 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.999897085 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.73924603 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 8819636983 ps |
| CPU time | 41.9 seconds |
| Started | Sep 24 01:16:52 PM UTC 24 |
| Finished | Sep 24 01:17:36 PM UTC 24 |
| Peak memory | 236820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73924603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.73924603 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.2906181410 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 166681681746 ps |
| CPU time | 1077.04 seconds |
| Started | Sep 24 01:18:48 PM UTC 24 |
| Finished | Sep 24 01:36:58 PM UTC 24 |
| Peak memory | 988552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906181410 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2906181410 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.2925637040 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 29835451 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 01:21:13 PM UTC 24 |
| Finished | Sep 24 01:21:15 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925637040 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2925637040 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_app.2153833734 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4406714656 ps |
| CPU time | 238.81 seconds |
| Started | Sep 24 01:19:06 PM UTC 24 |
| Finished | Sep 24 01:23:09 PM UTC 24 |
| Peak memory | 291908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153833734 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2153833734 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.3679285999 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 22283093429 ps |
| CPU time | 600.97 seconds |
| Started | Sep 24 01:19:01 PM UTC 24 |
| Finished | Sep 24 01:29:09 PM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679285999 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3679285999 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1251019430 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1487512275 ps |
| CPU time | 47.7 seconds |
| Started | Sep 24 01:20:22 PM UTC 24 |
| Finished | Sep 24 01:21:12 PM UTC 24 |
| Peak memory | 236184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251019430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1251019430 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.4115699084 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 119697207 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 01:21:02 PM UTC 24 |
| Finished | Sep 24 01:21:05 PM UTC 24 |
| Peak memory | 228284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115699084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.4115699084 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2759353767 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 7485016310 ps |
| CPU time | 110.31 seconds |
| Started | Sep 24 01:19:24 PM UTC 24 |
| Finished | Sep 24 01:21:17 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759353767 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2759353767 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_error.2115294409 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 172111182216 ps |
| CPU time | 383.01 seconds |
| Started | Sep 24 01:19:45 PM UTC 24 |
| Finished | Sep 24 01:26:14 PM UTC 24 |
| Peak memory | 515108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115294409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2115294409 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.2691990115 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1301368924 ps |
| CPU time | 15.18 seconds |
| Started | Sep 24 01:20:05 PM UTC 24 |
| Finished | Sep 24 01:20:22 PM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691990115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2691990115 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.4285096591 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 39911835 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 01:21:06 PM UTC 24 |
| Finished | Sep 24 01:21:09 PM UTC 24 |
| Peak memory | 232528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285096591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.4285096591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1471942821 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 21026201284 ps |
| CPU time | 2752.98 seconds |
| Started | Sep 24 01:18:53 PM UTC 24 |
| Finished | Sep 24 02:05:19 PM UTC 24 |
| Peak memory | 1453092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471942821 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.1471942821 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.2707580094 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2722380281 ps |
| CPU time | 225.59 seconds |
| Started | Sep 24 01:18:55 PM UTC 24 |
| Finished | Sep 24 01:22:44 PM UTC 24 |
| Peak memory | 308264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707580094 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2707580094 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.487858732 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 633874882 ps |
| CPU time | 11.06 seconds |
| Started | Sep 24 01:18:53 PM UTC 24 |
| Finished | Sep 24 01:19:05 PM UTC 24 |
| Peak memory | 236568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487858732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.487858732 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.3774803860 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 19719850430 ps |
| CPU time | 587.12 seconds |
| Started | Sep 24 01:21:10 PM UTC 24 |
| Finished | Sep 24 01:31:05 PM UTC 24 |
| Peak memory | 345636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774803860 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3774803860 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.1579776089 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 18088437 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 01:22:45 PM UTC 24 |
| Finished | Sep 24 01:22:48 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579776089 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1579776089 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_app.1493074073 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 15741916288 ps |
| CPU time | 455.46 seconds |
| Started | Sep 24 01:21:44 PM UTC 24 |
| Finished | Sep 24 01:29:25 PM UTC 24 |
| Peak memory | 560100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493074073 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1493074073 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.4146357949 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 21514138753 ps |
| CPU time | 1217.82 seconds |
| Started | Sep 24 01:21:21 PM UTC 24 |
| Finished | Sep 24 01:41:54 PM UTC 24 |
| Peak memory | 265176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146357949 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.4146357949 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.1461789233 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1112542905 ps |
| CPU time | 46.7 seconds |
| Started | Sep 24 01:22:21 PM UTC 24 |
| Finished | Sep 24 01:23:09 PM UTC 24 |
| Peak memory | 236320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461789233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1461789233 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.45084848 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1581299740 ps |
| CPU time | 26.8 seconds |
| Started | Sep 24 01:22:22 PM UTC 24 |
| Finished | Sep 24 01:22:50 PM UTC 24 |
| Peak memory | 236356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45084848 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.45084848 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.4067929719 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 6247865189 ps |
| CPU time | 188.81 seconds |
| Started | Sep 24 01:22:00 PM UTC 24 |
| Finished | Sep 24 01:25:12 PM UTC 24 |
| Peak memory | 330760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067929719 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.4067929719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_error.2279580303 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 75107949634 ps |
| CPU time | 604.72 seconds |
| Started | Sep 24 01:22:06 PM UTC 24 |
| Finished | Sep 24 01:32:19 PM UTC 24 |
| Peak memory | 609456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279580303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2279580303 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.2452356958 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2106310503 ps |
| CPU time | 8.19 seconds |
| Started | Sep 24 01:22:12 PM UTC 24 |
| Finished | Sep 24 01:22:21 PM UTC 24 |
| Peak memory | 228504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452356958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2452356958 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.2780459317 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 138379635 ps |
| CPU time | 2.38 seconds |
| Started | Sep 24 01:22:38 PM UTC 24 |
| Finished | Sep 24 01:22:42 PM UTC 24 |
| Peak memory | 234580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780459317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2780459317 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1073964067 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 117530127289 ps |
| CPU time | 4929.72 seconds |
| Started | Sep 24 01:21:17 PM UTC 24 |
| Finished | Sep 24 02:44:27 PM UTC 24 |
| Peak memory | 4609156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073964067 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1073964067 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.3254771727 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2348644492 ps |
| CPU time | 58.09 seconds |
| Started | Sep 24 01:21:20 PM UTC 24 |
| Finished | Sep 24 01:22:20 PM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254771727 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3254771727 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.1471988555 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 17079416662 ps |
| CPU time | 97.12 seconds |
| Started | Sep 24 01:21:16 PM UTC 24 |
| Finished | Sep 24 01:22:55 PM UTC 24 |
| Peak memory | 238684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471988555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1471988555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.2247960403 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 68513717451 ps |
| CPU time | 579.35 seconds |
| Started | Sep 24 01:22:42 PM UTC 24 |
| Finished | Sep 24 01:32:30 PM UTC 24 |
| Peak memory | 396652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247960403 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2247960403 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.2145034238 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 25659033 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 01:23:33 PM UTC 24 |
| Finished | Sep 24 01:23:35 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145034238 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2145034238 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_app.1616412297 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 8677574841 ps |
| CPU time | 208.25 seconds |
| Started | Sep 24 01:23:04 PM UTC 24 |
| Finished | Sep 24 01:26:35 PM UTC 24 |
| Peak memory | 363492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616412297 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1616412297 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.942640800 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 78508755858 ps |
| CPU time | 1296.52 seconds |
| Started | Sep 24 01:23:03 PM UTC 24 |
| Finished | Sep 24 01:44:55 PM UTC 24 |
| Peak memory | 265164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942640800 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.942640800 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.1385216619 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1674011822 ps |
| CPU time | 11.3 seconds |
| Started | Sep 24 01:23:16 PM UTC 24 |
| Finished | Sep 24 01:23:28 PM UTC 24 |
| Peak memory | 235492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385216619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1385216619 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.4174268363 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 27682098 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 01:23:29 PM UTC 24 |
| Finished | Sep 24 01:23:31 PM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174268363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.4174268363 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.609955028 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 17072264424 ps |
| CPU time | 100.06 seconds |
| Started | Sep 24 01:23:10 PM UTC 24 |
| Finished | Sep 24 01:24:52 PM UTC 24 |
| Peak memory | 279532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609955028 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.609955028 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_error.3955014853 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2683522853 ps |
| CPU time | 226.35 seconds |
| Started | Sep 24 01:23:10 PM UTC 24 |
| Finished | Sep 24 01:27:00 PM UTC 24 |
| Peak memory | 318432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955014853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3955014853 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.1901895256 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1016504011 ps |
| CPU time | 12.93 seconds |
| Started | Sep 24 01:23:13 PM UTC 24 |
| Finished | Sep 24 01:23:27 PM UTC 24 |
| Peak memory | 228508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901895256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1901895256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.1422520475 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 40731835 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 01:23:29 PM UTC 24 |
| Finished | Sep 24 01:23:32 PM UTC 24 |
| Peak memory | 234472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422520475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1422520475 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.3883760804 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 161413079812 ps |
| CPU time | 2600.49 seconds |
| Started | Sep 24 01:22:51 PM UTC 24 |
| Finished | Sep 24 02:06:44 PM UTC 24 |
| Peak memory | 2634792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883760804 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.3883760804 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.2672750600 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4457564103 ps |
| CPU time | 116.06 seconds |
| Started | Sep 24 01:22:57 PM UTC 24 |
| Finished | Sep 24 01:24:55 PM UTC 24 |
| Peak memory | 330792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672750600 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2672750600 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.189513645 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4129383962 ps |
| CPU time | 79.77 seconds |
| Started | Sep 24 01:22:48 PM UTC 24 |
| Finished | Sep 24 01:24:10 PM UTC 24 |
| Peak memory | 236776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189513645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.189513645 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.2329432678 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 32672377616 ps |
| CPU time | 449.47 seconds |
| Started | Sep 24 01:23:32 PM UTC 24 |
| Finished | Sep 24 01:31:08 PM UTC 24 |
| Peak memory | 351584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329432678 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2329432678 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.3593130008 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 42198581 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 12:48:28 PM UTC 24 |
| Finished | Sep 24 12:48:30 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593130008 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3593130008 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_app.1507521960 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 13661158703 ps |
| CPU time | 233.85 seconds |
| Started | Sep 24 12:47:46 PM UTC 24 |
| Finished | Sep 24 12:51:44 PM UTC 24 |
| Peak memory | 306268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507521960 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1507521960 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.1706351974 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5274843970 ps |
| CPU time | 156.61 seconds |
| Started | Sep 24 12:47:49 PM UTC 24 |
| Finished | Sep 24 12:50:29 PM UTC 24 |
| Peak memory | 279576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706351974 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1706351974 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2473820285 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 70623247 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 12:48:07 PM UTC 24 |
| Finished | Sep 24 12:48:10 PM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473820285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2473820285 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.2363365927 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 56838224 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 12:48:10 PM UTC 24 |
| Finished | Sep 24 12:48:13 PM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363365927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2363365927 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.2308831983 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6911989745 ps |
| CPU time | 49.19 seconds |
| Started | Sep 24 12:48:13 PM UTC 24 |
| Finished | Sep 24 12:49:04 PM UTC 24 |
| Peak memory | 236628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308831983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2308831983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3394646238 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 331397813 ps |
| CPU time | 11.23 seconds |
| Started | Sep 24 12:47:54 PM UTC 24 |
| Finished | Sep 24 12:48:06 PM UTC 24 |
| Peak memory | 236388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394646238 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3394646238 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.1748724387 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 887719453 ps |
| CPU time | 12.79 seconds |
| Started | Sep 24 12:48:01 PM UTC 24 |
| Finished | Sep 24 12:48:15 PM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748724387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1748724387 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.809970714 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 36956866 ps |
| CPU time | 2.49 seconds |
| Started | Sep 24 12:48:14 PM UTC 24 |
| Finished | Sep 24 12:48:18 PM UTC 24 |
| Peak memory | 234524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809970714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.809970714 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.3907445432 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 350931925898 ps |
| CPU time | 3778.14 seconds |
| Started | Sep 24 12:47:14 PM UTC 24 |
| Finished | Sep 24 01:51:05 PM UTC 24 |
| Peak memory | 3486740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907445432 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.3907445432 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.1867909365 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 54476227632 ps |
| CPU time | 476.91 seconds |
| Started | Sep 24 12:47:15 PM UTC 24 |
| Finished | Sep 24 12:55:19 PM UTC 24 |
| Peak memory | 586780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867909365 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1867909365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.4076022273 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5279533872 ps |
| CPU time | 73.1 seconds |
| Started | Sep 24 12:47:12 PM UTC 24 |
| Finished | Sep 24 12:48:27 PM UTC 24 |
| Peak memory | 236784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076022273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.4076022273 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.280718961 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 135536432602 ps |
| CPU time | 1537.35 seconds |
| Started | Sep 24 12:48:16 PM UTC 24 |
| Finished | Sep 24 01:14:13 PM UTC 24 |
| Peak memory | 413056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280718961 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.280718961 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.2685692997 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 6881350626 ps |
| CPU time | 93.56 seconds |
| Started | Sep 24 12:48:17 PM UTC 24 |
| Finished | Sep 24 12:49:52 PM UTC 24 |
| Peak memory | 279740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2685692997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_r and_reset.2685692997 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3809947264 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 152796644 ps |
| CPU time | 4.1 seconds |
| Started | Sep 24 12:47:40 PM UTC 24 |
| Finished | Sep 24 12:47:45 PM UTC 24 |
| Peak memory | 236476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809947264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3809947264 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.2551118005 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 36578727 ps |
| CPU time | 3.27 seconds |
| Started | Sep 24 12:47:44 PM UTC 24 |
| Finished | Sep 24 12:47:48 PM UTC 24 |
| Peak memory | 236636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551118005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2551118005 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.2864893827 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1164471227 ps |
| CPU time | 60.54 seconds |
| Started | Sep 24 12:47:25 PM UTC 24 |
| Finished | Sep 24 12:48:27 PM UTC 24 |
| Peak memory | 236348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864893827 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2864893827 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.1691430078 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2654388409 ps |
| CPU time | 69.69 seconds |
| Started | Sep 24 12:47:26 PM UTC 24 |
| Finished | Sep 24 12:48:38 PM UTC 24 |
| Peak memory | 257208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691430078 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1691430078 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3830207564 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 949504209 ps |
| CPU time | 31.36 seconds |
| Started | Sep 24 12:47:26 PM UTC 24 |
| Finished | Sep 24 12:47:59 PM UTC 24 |
| Peak memory | 236344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830207564 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3830207564 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.1735746462 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 45060951318 ps |
| CPU time | 1435.3 seconds |
| Started | Sep 24 12:47:34 PM UTC 24 |
| Finished | Sep 24 01:11:48 PM UTC 24 |
| Peak memory | 709532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735746462 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1735746462 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1135868501 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 55796913177 ps |
| CPU time | 188.76 seconds |
| Started | Sep 24 12:47:34 PM UTC 24 |
| Finished | Sep 24 12:50:47 PM UTC 24 |
| Peak memory | 292052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135868501 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1135868501 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.9746140 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 68907816833 ps |
| CPU time | 2079.1 seconds |
| Started | Sep 24 12:47:34 PM UTC 24 |
| Finished | Sep 24 01:22:37 PM UTC 24 |
| Peak memory | 1147788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9746140 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.9746140 +enable_ masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.669820398 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 16759371 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 01:26:14 PM UTC 24 |
| Finished | Sep 24 01:26:16 PM UTC 24 |
| Peak memory | 226648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669820398 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.669820398 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_app.656720067 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 10135347057 ps |
| CPU time | 155.48 seconds |
| Started | Sep 24 01:24:56 PM UTC 24 |
| Finished | Sep 24 01:27:34 PM UTC 24 |
| Peak memory | 273436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656720067 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.656720067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.3455195484 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 22719192528 ps |
| CPU time | 1132.53 seconds |
| Started | Sep 24 01:24:54 PM UTC 24 |
| Finished | Sep 24 01:44:00 PM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455195484 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3455195484 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2589862375 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4404337436 ps |
| CPU time | 233.75 seconds |
| Started | Sep 24 01:25:12 PM UTC 24 |
| Finished | Sep 24 01:29:10 PM UTC 24 |
| Peak memory | 295912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589862375 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2589862375 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_error.3524253703 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 8901149506 ps |
| CPU time | 407.49 seconds |
| Started | Sep 24 01:25:13 PM UTC 24 |
| Finished | Sep 24 01:32:07 PM UTC 24 |
| Peak memory | 367628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524253703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3524253703 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.711031123 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2635525554 ps |
| CPU time | 10.47 seconds |
| Started | Sep 24 01:25:19 PM UTC 24 |
| Finished | Sep 24 01:25:31 PM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711031123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.711031123 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.2092207315 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1225513545 ps |
| CPU time | 14.72 seconds |
| Started | Sep 24 01:25:32 PM UTC 24 |
| Finished | Sep 24 01:25:48 PM UTC 24 |
| Peak memory | 246956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092207315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2092207315 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2672019420 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 175774418925 ps |
| CPU time | 2688.85 seconds |
| Started | Sep 24 01:24:11 PM UTC 24 |
| Finished | Sep 24 02:09:35 PM UTC 24 |
| Peak memory | 2819088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672019420 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2672019420 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.1158549281 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 458772240 ps |
| CPU time | 29.15 seconds |
| Started | Sep 24 01:24:40 PM UTC 24 |
| Finished | Sep 24 01:25:11 PM UTC 24 |
| Peak memory | 246688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158549281 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1158549281 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.4089544236 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1957038668 ps |
| CPU time | 61.98 seconds |
| Started | Sep 24 01:23:36 PM UTC 24 |
| Finished | Sep 24 01:24:40 PM UTC 24 |
| Peak memory | 232848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089544236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.4089544236 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.3665218385 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 8060917405 ps |
| CPU time | 758.27 seconds |
| Started | Sep 24 01:25:49 PM UTC 24 |
| Finished | Sep 24 01:38:38 PM UTC 24 |
| Peak memory | 450096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665218385 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3665218385 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.1243843791 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 29618060 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 01:27:57 PM UTC 24 |
| Finished | Sep 24 01:27:59 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243843791 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1243843791 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_app.2192118591 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 27567320660 ps |
| CPU time | 374.95 seconds |
| Started | Sep 24 01:27:01 PM UTC 24 |
| Finished | Sep 24 01:33:21 PM UTC 24 |
| Peak memory | 343012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192118591 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2192118591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.3379273835 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 98102086480 ps |
| CPU time | 1473.98 seconds |
| Started | Sep 24 01:26:49 PM UTC 24 |
| Finished | Sep 24 01:51:41 PM UTC 24 |
| Peak memory | 273356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379273835 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3379273835 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.4228395179 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 52564830910 ps |
| CPU time | 293.35 seconds |
| Started | Sep 24 01:27:19 PM UTC 24 |
| Finished | Sep 24 01:32:17 PM UTC 24 |
| Peak memory | 371696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228395179 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.4228395179 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_error.2226667377 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3295560440 ps |
| CPU time | 259.02 seconds |
| Started | Sep 24 01:27:28 PM UTC 24 |
| Finished | Sep 24 01:31:51 PM UTC 24 |
| Peak memory | 316392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226667377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2226667377 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.4215440149 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4197340883 ps |
| CPU time | 14.56 seconds |
| Started | Sep 24 01:27:35 PM UTC 24 |
| Finished | Sep 24 01:27:51 PM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215440149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.4215440149 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.2940190131 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 46332897 ps |
| CPU time | 2.17 seconds |
| Started | Sep 24 01:27:52 PM UTC 24 |
| Finished | Sep 24 01:27:56 PM UTC 24 |
| Peak memory | 232528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940190131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2940190131 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3277415840 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 12524092987 ps |
| CPU time | 526 seconds |
| Started | Sep 24 01:26:37 PM UTC 24 |
| Finished | Sep 24 01:35:30 PM UTC 24 |
| Peak memory | 803916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277415840 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.3277415840 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.3574088071 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 33036316455 ps |
| CPU time | 563.26 seconds |
| Started | Sep 24 01:26:40 PM UTC 24 |
| Finished | Sep 24 01:36:10 PM UTC 24 |
| Peak memory | 402408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574088071 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3574088071 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.2936213637 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 11215909515 ps |
| CPU time | 93.83 seconds |
| Started | Sep 24 01:26:17 PM UTC 24 |
| Finished | Sep 24 01:27:54 PM UTC 24 |
| Peak memory | 236868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936213637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2936213637 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.347608868 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 8464679253 ps |
| CPU time | 531.35 seconds |
| Started | Sep 24 01:27:55 PM UTC 24 |
| Finished | Sep 24 01:36:53 PM UTC 24 |
| Peak memory | 379936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347608868 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.347608868 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.72672651 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 39312462 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 01:29:57 PM UTC 24 |
| Finished | Sep 24 01:30:00 PM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72672651 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.72672651 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_app.1452616134 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 6210447832 ps |
| CPU time | 300.32 seconds |
| Started | Sep 24 01:29:10 PM UTC 24 |
| Finished | Sep 24 01:34:15 PM UTC 24 |
| Peak memory | 330772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452616134 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1452616134 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.1668811516 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 130845333658 ps |
| CPU time | 600.46 seconds |
| Started | Sep 24 01:28:44 PM UTC 24 |
| Finished | Sep 24 01:38:53 PM UTC 24 |
| Peak memory | 250920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668811516 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1668811516 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.522705669 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 73334493443 ps |
| CPU time | 362.06 seconds |
| Started | Sep 24 01:29:11 PM UTC 24 |
| Finished | Sep 24 01:35:18 PM UTC 24 |
| Peak memory | 316444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522705669 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.522705669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_error.2728983890 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 42226654589 ps |
| CPU time | 213.95 seconds |
| Started | Sep 24 01:29:27 PM UTC 24 |
| Finished | Sep 24 01:33:04 PM UTC 24 |
| Peak memory | 394224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728983890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2728983890 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.603579233 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 800259038 ps |
| CPU time | 9.58 seconds |
| Started | Sep 24 01:29:51 PM UTC 24 |
| Finished | Sep 24 01:30:02 PM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603579233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.603579233 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2627993891 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 21486534835 ps |
| CPU time | 1221.5 seconds |
| Started | Sep 24 01:28:10 PM UTC 24 |
| Finished | Sep 24 01:48:47 PM UTC 24 |
| Peak memory | 842784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627993891 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2627993891 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.3977292256 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 10326696877 ps |
| CPU time | 386.04 seconds |
| Started | Sep 24 01:28:14 PM UTC 24 |
| Finished | Sep 24 01:34:46 PM UTC 24 |
| Peak memory | 492560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977292256 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3977292256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.3489121568 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 54956188115 ps |
| CPU time | 109.02 seconds |
| Started | Sep 24 01:28:00 PM UTC 24 |
| Finished | Sep 24 01:29:51 PM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489121568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3489121568 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.1847362000 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 67134686287 ps |
| CPU time | 2638.19 seconds |
| Started | Sep 24 01:29:57 PM UTC 24 |
| Finished | Sep 24 02:14:29 PM UTC 24 |
| Peak memory | 1154448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847362000 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1847362000 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.2580925116 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 67717430 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 01:31:46 PM UTC 24 |
| Finished | Sep 24 01:31:48 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580925116 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2580925116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_app.1365834925 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 13866029744 ps |
| CPU time | 196.51 seconds |
| Started | Sep 24 01:31:06 PM UTC 24 |
| Finished | Sep 24 01:34:26 PM UTC 24 |
| Peak memory | 330764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365834925 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1365834925 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.102241611 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 14476231103 ps |
| CPU time | 332.44 seconds |
| Started | Sep 24 01:30:25 PM UTC 24 |
| Finished | Sep 24 01:36:02 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102241611 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.102241611 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.359229476 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 59515652223 ps |
| CPU time | 467.04 seconds |
| Started | Sep 24 01:31:09 PM UTC 24 |
| Finished | Sep 24 01:39:03 PM UTC 24 |
| Peak memory | 515112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359229476 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.359229476 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_error.3006146615 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2981904639 ps |
| CPU time | 46.93 seconds |
| Started | Sep 24 01:31:25 PM UTC 24 |
| Finished | Sep 24 01:32:13 PM UTC 24 |
| Peak memory | 281644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006146615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3006146615 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.2970841461 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2223523377 ps |
| CPU time | 13.95 seconds |
| Started | Sep 24 01:31:30 PM UTC 24 |
| Finished | Sep 24 01:31:45 PM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970841461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2970841461 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.2707652973 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 43953995 ps |
| CPU time | 2.19 seconds |
| Started | Sep 24 01:31:37 PM UTC 24 |
| Finished | Sep 24 01:31:40 PM UTC 24 |
| Peak memory | 232416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707652973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2707652973 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2713031759 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 13920919408 ps |
| CPU time | 1744.84 seconds |
| Started | Sep 24 01:30:03 PM UTC 24 |
| Finished | Sep 24 01:59:31 PM UTC 24 |
| Peak memory | 1016864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713031759 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2713031759 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.4076709725 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 20054515406 ps |
| CPU time | 514.82 seconds |
| Started | Sep 24 01:30:09 PM UTC 24 |
| Finished | Sep 24 01:38:50 PM UTC 24 |
| Peak memory | 588836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076709725 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.4076709725 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.3207416140 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 15618970177 ps |
| CPU time | 81.15 seconds |
| Started | Sep 24 01:30:01 PM UTC 24 |
| Finished | Sep 24 01:31:24 PM UTC 24 |
| Peak memory | 236528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207416140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3207416140 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.2630866853 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 18860529319 ps |
| CPU time | 141.89 seconds |
| Started | Sep 24 01:31:41 PM UTC 24 |
| Finished | Sep 24 01:34:05 PM UTC 24 |
| Peak memory | 328752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630866853 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2630866853 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.105667222 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 17388839 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 01:32:31 PM UTC 24 |
| Finished | Sep 24 01:32:33 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105667222 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.105667222 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_app.3667885220 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 23275095943 ps |
| CPU time | 393.23 seconds |
| Started | Sep 24 01:32:14 PM UTC 24 |
| Finished | Sep 24 01:38:53 PM UTC 24 |
| Peak memory | 467928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667885220 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3667885220 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.48681293 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 39862371127 ps |
| CPU time | 1745.97 seconds |
| Started | Sep 24 01:32:08 PM UTC 24 |
| Finished | Sep 24 02:01:36 PM UTC 24 |
| Peak memory | 279588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48681293 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.48681293 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.3730955741 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 12916781036 ps |
| CPU time | 140.13 seconds |
| Started | Sep 24 01:32:14 PM UTC 24 |
| Finished | Sep 24 01:34:38 PM UTC 24 |
| Peak memory | 291876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730955741 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3730955741 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_error.3017318822 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 8173193364 ps |
| CPU time | 193.07 seconds |
| Started | Sep 24 01:32:18 PM UTC 24 |
| Finished | Sep 24 01:35:35 PM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017318822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3017318822 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.3491717163 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3069577183 ps |
| CPU time | 18.21 seconds |
| Started | Sep 24 01:32:20 PM UTC 24 |
| Finished | Sep 24 01:32:39 PM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491717163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3491717163 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.748400549 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 99409265338 ps |
| CPU time | 2353.4 seconds |
| Started | Sep 24 01:31:52 PM UTC 24 |
| Finished | Sep 24 02:11:36 PM UTC 24 |
| Peak memory | 1348648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748400549 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.748400549 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.562277796 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 10566039157 ps |
| CPU time | 387.83 seconds |
| Started | Sep 24 01:31:53 PM UTC 24 |
| Finished | Sep 24 01:38:27 PM UTC 24 |
| Peak memory | 519204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562277796 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.562277796 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.3803619835 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2381885385 ps |
| CPU time | 49.58 seconds |
| Started | Sep 24 01:32:29 PM UTC 24 |
| Finished | Sep 24 01:33:20 PM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803619835 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3803619835 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.51216833 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 46432405 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 01:34:07 PM UTC 24 |
| Finished | Sep 24 01:34:09 PM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51216833 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.51216833 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_app.2547753401 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1706642358 ps |
| CPU time | 103.64 seconds |
| Started | Sep 24 01:33:20 PM UTC 24 |
| Finished | Sep 24 01:35:06 PM UTC 24 |
| Peak memory | 265168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547753401 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2547753401 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.1333207228 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 18268186116 ps |
| CPU time | 539.11 seconds |
| Started | Sep 24 01:33:05 PM UTC 24 |
| Finished | Sep 24 01:42:13 PM UTC 24 |
| Peak memory | 252932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333207228 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1333207228 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2217640136 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 7805825140 ps |
| CPU time | 241.41 seconds |
| Started | Sep 24 01:33:22 PM UTC 24 |
| Finished | Sep 24 01:37:27 PM UTC 24 |
| Peak memory | 312364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217640136 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2217640136 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_error.3175218589 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3470830285 ps |
| CPU time | 112.25 seconds |
| Started | Sep 24 01:33:44 PM UTC 24 |
| Finished | Sep 24 01:35:39 PM UTC 24 |
| Peak memory | 308460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175218589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3175218589 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.3986680746 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2059768486 ps |
| CPU time | 15.1 seconds |
| Started | Sep 24 01:33:46 PM UTC 24 |
| Finished | Sep 24 01:34:02 PM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986680746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3986680746 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.586599011 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 33613818 ps |
| CPU time | 2.02 seconds |
| Started | Sep 24 01:34:03 PM UTC 24 |
| Finished | Sep 24 01:34:06 PM UTC 24 |
| Peak memory | 234668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586599011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.586599011 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.4238844576 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 41521825102 ps |
| CPU time | 1283.48 seconds |
| Started | Sep 24 01:32:40 PM UTC 24 |
| Finished | Sep 24 01:54:19 PM UTC 24 |
| Peak memory | 1692704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238844576 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.4238844576 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.3583717560 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 8090740902 ps |
| CPU time | 74.17 seconds |
| Started | Sep 24 01:32:51 PM UTC 24 |
| Finished | Sep 24 01:34:07 PM UTC 24 |
| Peak memory | 281876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583717560 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3583717560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.1904405474 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1248856185 ps |
| CPU time | 67.38 seconds |
| Started | Sep 24 01:32:34 PM UTC 24 |
| Finished | Sep 24 01:33:43 PM UTC 24 |
| Peak memory | 236700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904405474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1904405474 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.3977579575 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 63268937476 ps |
| CPU time | 1083.99 seconds |
| Started | Sep 24 01:34:06 PM UTC 24 |
| Finished | Sep 24 01:52:25 PM UTC 24 |
| Peak memory | 984036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977579575 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3977579575 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.787265007 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 36671623 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 01:35:19 PM UTC 24 |
| Finished | Sep 24 01:35:22 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787265007 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.787265007 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.35575789 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 26995651668 ps |
| CPU time | 370.46 seconds |
| Started | Sep 24 01:34:27 PM UTC 24 |
| Finished | Sep 24 01:40:44 PM UTC 24 |
| Peak memory | 242664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35575789 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.35575789 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2565133182 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 6603984783 ps |
| CPU time | 161.36 seconds |
| Started | Sep 24 01:34:39 PM UTC 24 |
| Finished | Sep 24 01:37:23 PM UTC 24 |
| Peak memory | 361492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565133182 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2565133182 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_error.2788013666 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 36407046348 ps |
| CPU time | 468.48 seconds |
| Started | Sep 24 01:34:47 PM UTC 24 |
| Finished | Sep 24 01:42:43 PM UTC 24 |
| Peak memory | 498924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788013666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2788013666 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.1459209182 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 441798779 ps |
| CPU time | 6.35 seconds |
| Started | Sep 24 01:34:52 PM UTC 24 |
| Finished | Sep 24 01:34:59 PM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459209182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1459209182 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.803551902 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1400437577 ps |
| CPU time | 31.14 seconds |
| Started | Sep 24 01:35:00 PM UTC 24 |
| Finished | Sep 24 01:35:33 PM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803551902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.803551902 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3203249562 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 222193646296 ps |
| CPU time | 2565.24 seconds |
| Started | Sep 24 01:34:10 PM UTC 24 |
| Finished | Sep 24 02:17:24 PM UTC 24 |
| Peak memory | 2862120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203249562 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3203249562 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.13995360 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2694233812 ps |
| CPU time | 110.95 seconds |
| Started | Sep 24 01:34:16 PM UTC 24 |
| Finished | Sep 24 01:36:10 PM UTC 24 |
| Peak memory | 304140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13995360 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.13995360 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.3947382870 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 8544193068 ps |
| CPU time | 137.9 seconds |
| Started | Sep 24 01:34:08 PM UTC 24 |
| Finished | Sep 24 01:36:29 PM UTC 24 |
| Peak memory | 238628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947382870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3947382870 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.3325690907 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 27921306652 ps |
| CPU time | 2652.49 seconds |
| Started | Sep 24 01:35:07 PM UTC 24 |
| Finished | Sep 24 02:19:51 PM UTC 24 |
| Peak memory | 824704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325690907 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3325690907 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.3044409314 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 28272486 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 01:36:15 PM UTC 24 |
| Finished | Sep 24 01:36:18 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044409314 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3044409314 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_app.3086546951 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3171951285 ps |
| CPU time | 64.12 seconds |
| Started | Sep 24 01:35:40 PM UTC 24 |
| Finished | Sep 24 01:36:46 PM UTC 24 |
| Peak memory | 248860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086546951 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3086546951 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.2145699296 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 12079671269 ps |
| CPU time | 554 seconds |
| Started | Sep 24 01:35:36 PM UTC 24 |
| Finished | Sep 24 01:44:57 PM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145699296 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2145699296 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.1652915623 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 5007769906 ps |
| CPU time | 69.13 seconds |
| Started | Sep 24 01:35:49 PM UTC 24 |
| Finished | Sep 24 01:37:00 PM UTC 24 |
| Peak memory | 250980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652915623 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1652915623 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_error.2626071207 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 10531977167 ps |
| CPU time | 367.15 seconds |
| Started | Sep 24 01:35:53 PM UTC 24 |
| Finished | Sep 24 01:42:06 PM UTC 24 |
| Peak memory | 494636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626071207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2626071207 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.1488813285 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1252217003 ps |
| CPU time | 15.44 seconds |
| Started | Sep 24 01:36:03 PM UTC 24 |
| Finished | Sep 24 01:36:20 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488813285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1488813285 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.743805390 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 199055803 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 01:36:11 PM UTC 24 |
| Finished | Sep 24 01:36:14 PM UTC 24 |
| Peak memory | 234544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743805390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.743805390 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.2230299147 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 105515547446 ps |
| CPU time | 3047.23 seconds |
| Started | Sep 24 01:35:30 PM UTC 24 |
| Finished | Sep 24 02:26:53 PM UTC 24 |
| Peak memory | 1612828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230299147 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.2230299147 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.152275493 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 739566604 ps |
| CPU time | 78.65 seconds |
| Started | Sep 24 01:35:34 PM UTC 24 |
| Finished | Sep 24 01:36:54 PM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152275493 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.152275493 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.1406578963 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2040014067 ps |
| CPU time | 23.87 seconds |
| Started | Sep 24 01:35:22 PM UTC 24 |
| Finished | Sep 24 01:35:48 PM UTC 24 |
| Peak memory | 236428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406578963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1406578963 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.3235504919 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 678461183 ps |
| CPU time | 21.29 seconds |
| Started | Sep 24 01:36:11 PM UTC 24 |
| Finished | Sep 24 01:36:34 PM UTC 24 |
| Peak memory | 236408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235504919 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3235504919 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.3301459170 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 58969468 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 01:37:03 PM UTC 24 |
| Finished | Sep 24 01:37:06 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301459170 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3301459170 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_app.3021609559 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 11731163623 ps |
| CPU time | 434.68 seconds |
| Started | Sep 24 01:36:47 PM UTC 24 |
| Finished | Sep 24 01:44:08 PM UTC 24 |
| Peak memory | 508968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021609559 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3021609559 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.901473918 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 58404450448 ps |
| CPU time | 1290.07 seconds |
| Started | Sep 24 01:36:35 PM UTC 24 |
| Finished | Sep 24 01:58:20 PM UTC 24 |
| Peak memory | 271592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901473918 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.901473918 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.1783433860 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 17638331044 ps |
| CPU time | 229.71 seconds |
| Started | Sep 24 01:36:50 PM UTC 24 |
| Finished | Sep 24 01:40:43 PM UTC 24 |
| Peak memory | 296212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783433860 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1783433860 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_error.547051241 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1393967605 ps |
| CPU time | 102.13 seconds |
| Started | Sep 24 01:36:54 PM UTC 24 |
| Finished | Sep 24 01:38:38 PM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547051241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.547051241 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.2110079663 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 11475908446 ps |
| CPU time | 19.71 seconds |
| Started | Sep 24 01:36:55 PM UTC 24 |
| Finished | Sep 24 01:37:16 PM UTC 24 |
| Peak memory | 228688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110079663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2110079663 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.3714244893 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 506636023196 ps |
| CPU time | 4813.31 seconds |
| Started | Sep 24 01:36:21 PM UTC 24 |
| Finished | Sep 24 02:57:28 PM UTC 24 |
| Peak memory | 4371636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714244893 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.3714244893 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.2974713501 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 66157249775 ps |
| CPU time | 540.42 seconds |
| Started | Sep 24 01:36:30 PM UTC 24 |
| Finished | Sep 24 01:45:38 PM UTC 24 |
| Peak memory | 615596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974713501 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2974713501 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.3818773435 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2607316672 ps |
| CPU time | 78.61 seconds |
| Started | Sep 24 01:36:18 PM UTC 24 |
| Finished | Sep 24 01:37:40 PM UTC 24 |
| Peak memory | 236892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818773435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3818773435 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.2918915845 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 58238657571 ps |
| CPU time | 1101.36 seconds |
| Started | Sep 24 01:37:00 PM UTC 24 |
| Finished | Sep 24 01:55:35 PM UTC 24 |
| Peak memory | 640388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918915845 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2918915845 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.3125333523 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 49541715 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 01:38:27 PM UTC 24 |
| Finished | Sep 24 01:38:30 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125333523 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3125333523 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_app.1399133094 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 8425257370 ps |
| CPU time | 351.62 seconds |
| Started | Sep 24 01:37:30 PM UTC 24 |
| Finished | Sep 24 01:43:28 PM UTC 24 |
| Peak memory | 332772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399133094 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1399133094 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.1025091201 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3364114268 ps |
| CPU time | 383.62 seconds |
| Started | Sep 24 01:37:28 PM UTC 24 |
| Finished | Sep 24 01:43:57 PM UTC 24 |
| Peak memory | 240624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025091201 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.1025091201 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.301627875 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 35610710351 ps |
| CPU time | 501.64 seconds |
| Started | Sep 24 01:37:41 PM UTC 24 |
| Finished | Sep 24 01:46:09 PM UTC 24 |
| Peak memory | 556064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301627875 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.301627875 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_error.4003065807 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 33064350585 ps |
| CPU time | 576.52 seconds |
| Started | Sep 24 01:38:01 PM UTC 24 |
| Finished | Sep 24 01:47:46 PM UTC 24 |
| Peak memory | 621536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003065807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.4003065807 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.542116450 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 589148114 ps |
| CPU time | 8.58 seconds |
| Started | Sep 24 01:38:06 PM UTC 24 |
| Finished | Sep 24 01:38:16 PM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542116450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.542116450 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.3264715604 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3522549672 ps |
| CPU time | 33.95 seconds |
| Started | Sep 24 01:38:17 PM UTC 24 |
| Finished | Sep 24 01:38:53 PM UTC 24 |
| Peak memory | 263476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264715604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3264715604 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.2385951103 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 78675396310 ps |
| CPU time | 3250.35 seconds |
| Started | Sep 24 01:37:16 PM UTC 24 |
| Finished | Sep 24 02:32:06 PM UTC 24 |
| Peak memory | 3165220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385951103 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.2385951103 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.1031466297 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 52940594565 ps |
| CPU time | 688.95 seconds |
| Started | Sep 24 01:37:24 PM UTC 24 |
| Finished | Sep 24 01:49:02 PM UTC 24 |
| Peak memory | 580648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031466297 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1031466297 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.1619198500 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 435862831 ps |
| CPU time | 20.91 seconds |
| Started | Sep 24 01:37:06 PM UTC 24 |
| Finished | Sep 24 01:37:29 PM UTC 24 |
| Peak memory | 236460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619198500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1619198500 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.1039455842 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 16462259547 ps |
| CPU time | 113.24 seconds |
| Started | Sep 24 01:38:20 PM UTC 24 |
| Finished | Sep 24 01:40:16 PM UTC 24 |
| Peak memory | 316768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039455842 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1039455842 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.1237220152 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 23590683 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 12:51:44 PM UTC 24 |
| Finished | Sep 24 12:51:47 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237220152 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1237220152 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_app.1111155893 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 56674437324 ps |
| CPU time | 453.35 seconds |
| Started | Sep 24 12:49:48 PM UTC 24 |
| Finished | Sep 24 12:57:27 PM UTC 24 |
| Peak memory | 525348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111155893 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.1111155893 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3425766420 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 72159610857 ps |
| CPU time | 416.75 seconds |
| Started | Sep 24 12:49:50 PM UTC 24 |
| Finished | Sep 24 12:56:52 PM UTC 24 |
| Peak memory | 513076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425766420 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3425766420 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.1896759358 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 37307696020 ps |
| CPU time | 863.77 seconds |
| Started | Sep 24 12:48:44 PM UTC 24 |
| Finished | Sep 24 01:03:17 PM UTC 24 |
| Peak memory | 261104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896759358 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1896759358 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.665677412 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2156164191 ps |
| CPU time | 75.84 seconds |
| Started | Sep 24 12:50:30 PM UTC 24 |
| Finished | Sep 24 12:51:48 PM UTC 24 |
| Peak memory | 246556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665677412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.665677412 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.2917886329 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 31299811 ps |
| CPU time | 1.77 seconds |
| Started | Sep 24 12:50:46 PM UTC 24 |
| Finished | Sep 24 12:50:49 PM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917886329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2917886329 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3836389862 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2574072855 ps |
| CPU time | 13.83 seconds |
| Started | Sep 24 12:50:48 PM UTC 24 |
| Finished | Sep 24 12:51:03 PM UTC 24 |
| Peak memory | 230924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836389862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3836389862 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_error.1025118719 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1773261876 ps |
| CPU time | 132.96 seconds |
| Started | Sep 24 12:50:23 PM UTC 24 |
| Finished | Sep 24 12:52:38 PM UTC 24 |
| Peak memory | 285744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025118719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1025118719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.2042719339 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3521816835 ps |
| CPU time | 13.92 seconds |
| Started | Sep 24 12:50:30 PM UTC 24 |
| Finished | Sep 24 12:50:45 PM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042719339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2042719339 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.3441594417 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 29870526896 ps |
| CPU time | 3608.07 seconds |
| Started | Sep 24 12:48:31 PM UTC 24 |
| Finished | Sep 24 01:49:24 PM UTC 24 |
| Peak memory | 1958948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441594417 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3441594417 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.995781688 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1731032976 ps |
| CPU time | 66.79 seconds |
| Started | Sep 24 12:49:54 PM UTC 24 |
| Finished | Sep 24 12:51:03 PM UTC 24 |
| Peak memory | 247032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995781688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.995781688 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.608755254 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 9792359486 ps |
| CPU time | 57.09 seconds |
| Started | Sep 24 12:51:04 PM UTC 24 |
| Finished | Sep 24 12:52:03 PM UTC 24 |
| Peak memory | 278588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608755254 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.608755254 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.1819090329 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2971637715 ps |
| CPU time | 309.15 seconds |
| Started | Sep 24 12:48:39 PM UTC 24 |
| Finished | Sep 24 12:53:54 PM UTC 24 |
| Peak memory | 310340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819090329 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1819090329 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.1467764622 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2163946206 ps |
| CPU time | 71.33 seconds |
| Started | Sep 24 12:48:28 PM UTC 24 |
| Finished | Sep 24 12:49:42 PM UTC 24 |
| Peak memory | 236828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467764622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1467764622 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.417688100 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 5011606858 ps |
| CPU time | 60.64 seconds |
| Started | Sep 24 12:50:53 PM UTC 24 |
| Finished | Sep 24 12:51:56 PM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417688100 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.417688100 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.2043770041 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 118349780 ps |
| CPU time | 3.63 seconds |
| Started | Sep 24 12:49:42 PM UTC 24 |
| Finished | Sep 24 12:49:47 PM UTC 24 |
| Peak memory | 236708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043770041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.2043770041 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.869710469 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 117877442 ps |
| CPU time | 5.24 seconds |
| Started | Sep 24 12:49:42 PM UTC 24 |
| Finished | Sep 24 12:49:49 PM UTC 24 |
| Peak memory | 236456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869710469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.869710469 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1597560967 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 72168206400 ps |
| CPU time | 2281.79 seconds |
| Started | Sep 24 12:48:54 PM UTC 24 |
| Finished | Sep 24 01:27:27 PM UTC 24 |
| Peak memory | 1192852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597560967 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1597560967 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.2283812102 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1048405437 ps |
| CPU time | 34.72 seconds |
| Started | Sep 24 12:49:05 PM UTC 24 |
| Finished | Sep 24 12:49:41 PM UTC 24 |
| Peak memory | 236452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283812102 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2283812102 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2487450883 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4214895388 ps |
| CPU time | 36.23 seconds |
| Started | Sep 24 12:49:11 PM UTC 24 |
| Finished | Sep 24 12:49:49 PM UTC 24 |
| Peak memory | 236584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487450883 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2487450883 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.2385286853 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 171953205548 ps |
| CPU time | 1391.48 seconds |
| Started | Sep 24 12:49:12 PM UTC 24 |
| Finished | Sep 24 01:12:40 PM UTC 24 |
| Peak memory | 1692580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385286853 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2385286853 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3231481142 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 47336710407 ps |
| CPU time | 303.6 seconds |
| Started | Sep 24 12:49:31 PM UTC 24 |
| Finished | Sep 24 12:54:40 PM UTC 24 |
| Peak memory | 440960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231481142 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3231481142 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.1560063348 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 65196177946 ps |
| CPU time | 2531.05 seconds |
| Started | Sep 24 12:49:31 PM UTC 24 |
| Finished | Sep 24 01:32:13 PM UTC 24 |
| Peak memory | 2980464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560063348 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1560063348 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.112159433 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 33721361 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 01:39:32 PM UTC 24 |
| Finished | Sep 24 01:39:34 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112159433 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.112159433 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_app.2001752751 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 23067182845 ps |
| CPU time | 473.14 seconds |
| Started | Sep 24 01:38:54 PM UTC 24 |
| Finished | Sep 24 01:46:54 PM UTC 24 |
| Peak memory | 341212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001752751 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2001752751 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.2743682770 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 12713276488 ps |
| CPU time | 824.65 seconds |
| Started | Sep 24 01:38:52 PM UTC 24 |
| Finished | Sep 24 01:52:47 PM UTC 24 |
| Peak memory | 253152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743682770 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2743682770 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2503683282 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 9184178383 ps |
| CPU time | 161.12 seconds |
| Started | Sep 24 01:38:54 PM UTC 24 |
| Finished | Sep 24 01:41:38 PM UTC 24 |
| Peak memory | 316460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503683282 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2503683282 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_error.954275451 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 23427808001 ps |
| CPU time | 509.23 seconds |
| Started | Sep 24 01:38:54 PM UTC 24 |
| Finished | Sep 24 01:47:31 PM UTC 24 |
| Peak memory | 537900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954275451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.954275451 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.2606097577 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5275837599 ps |
| CPU time | 13 seconds |
| Started | Sep 24 01:39:04 PM UTC 24 |
| Finished | Sep 24 01:39:18 PM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606097577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2606097577 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.3675682614 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 177445257613 ps |
| CPU time | 642.82 seconds |
| Started | Sep 24 01:38:40 PM UTC 24 |
| Finished | Sep 24 01:49:31 PM UTC 24 |
| Peak memory | 908264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675682614 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.3675682614 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.1406465793 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6112342141 ps |
| CPU time | 65.21 seconds |
| Started | Sep 24 01:38:40 PM UTC 24 |
| Finished | Sep 24 01:39:47 PM UTC 24 |
| Peak memory | 269400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406465793 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1406465793 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.4050170883 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 14939141610 ps |
| CPU time | 81.48 seconds |
| Started | Sep 24 01:38:31 PM UTC 24 |
| Finished | Sep 24 01:39:55 PM UTC 24 |
| Peak memory | 236564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050170883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.4050170883 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.4035438985 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 57867350568 ps |
| CPU time | 686.44 seconds |
| Started | Sep 24 01:39:23 PM UTC 24 |
| Finished | Sep 24 01:50:59 PM UTC 24 |
| Peak memory | 351284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035438985 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.4035438985 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.2770348550 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 71670507 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 01:41:39 PM UTC 24 |
| Finished | Sep 24 01:41:41 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770348550 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2770348550 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_app.3605479882 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 11005484726 ps |
| CPU time | 89.56 seconds |
| Started | Sep 24 01:40:44 PM UTC 24 |
| Finished | Sep 24 01:42:16 PM UTC 24 |
| Peak memory | 283624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605479882 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3605479882 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.2929466938 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 23484466757 ps |
| CPU time | 599.95 seconds |
| Started | Sep 24 01:40:17 PM UTC 24 |
| Finished | Sep 24 01:50:25 PM UTC 24 |
| Peak memory | 248864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929466938 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2929466938 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.3922043679 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 7070464969 ps |
| CPU time | 170.37 seconds |
| Started | Sep 24 01:40:44 PM UTC 24 |
| Finished | Sep 24 01:43:38 PM UTC 24 |
| Peak memory | 285732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922043679 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3922043679 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_error.483516439 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 12159644578 ps |
| CPU time | 497.24 seconds |
| Started | Sep 24 01:40:45 PM UTC 24 |
| Finished | Sep 24 01:49:10 PM UTC 24 |
| Peak memory | 390164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483516439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.483516439 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.3056176350 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 157738825 ps |
| CPU time | 2.49 seconds |
| Started | Sep 24 01:41:28 PM UTC 24 |
| Finished | Sep 24 01:41:31 PM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056176350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3056176350 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2213544406 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 667165474714 ps |
| CPU time | 1609.03 seconds |
| Started | Sep 24 01:39:48 PM UTC 24 |
| Finished | Sep 24 02:06:57 PM UTC 24 |
| Peak memory | 1803300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213544406 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2213544406 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.1557670596 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 29102797264 ps |
| CPU time | 274.93 seconds |
| Started | Sep 24 01:39:56 PM UTC 24 |
| Finished | Sep 24 01:44:36 PM UTC 24 |
| Peak memory | 422884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557670596 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1557670596 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.2635551761 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1221628196 ps |
| CPU time | 66.92 seconds |
| Started | Sep 24 01:39:35 PM UTC 24 |
| Finished | Sep 24 01:40:44 PM UTC 24 |
| Peak memory | 236500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635551761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2635551761 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.1810864166 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 67260120190 ps |
| CPU time | 2266.35 seconds |
| Started | Sep 24 01:41:33 PM UTC 24 |
| Finished | Sep 24 02:19:47 PM UTC 24 |
| Peak memory | 1150276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810864166 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1810864166 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.734469599 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 46543530 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 01:43:29 PM UTC 24 |
| Finished | Sep 24 01:43:32 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734469599 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.734469599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_app.2759117588 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3966004342 ps |
| CPU time | 254.81 seconds |
| Started | Sep 24 01:42:13 PM UTC 24 |
| Finished | Sep 24 01:46:32 PM UTC 24 |
| Peak memory | 316580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759117588 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2759117588 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.3774627600 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 25197349868 ps |
| CPU time | 590.28 seconds |
| Started | Sep 24 01:42:06 PM UTC 24 |
| Finished | Sep 24 01:52:05 PM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774627600 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3774627600 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.414081340 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 4199548940 ps |
| CPU time | 151.6 seconds |
| Started | Sep 24 01:42:16 PM UTC 24 |
| Finished | Sep 24 01:44:51 PM UTC 24 |
| Peak memory | 310356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414081340 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.414081340 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_error.2935450523 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2816256626 ps |
| CPU time | 109.93 seconds |
| Started | Sep 24 01:42:45 PM UTC 24 |
| Finished | Sep 24 01:44:37 PM UTC 24 |
| Peak memory | 283684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935450523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2935450523 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.1812247369 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 492004995 ps |
| CPU time | 7.05 seconds |
| Started | Sep 24 01:42:55 PM UTC 24 |
| Finished | Sep 24 01:43:03 PM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812247369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1812247369 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.2086570466 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 4860827763 ps |
| CPU time | 22.23 seconds |
| Started | Sep 24 01:43:04 PM UTC 24 |
| Finished | Sep 24 01:43:28 PM UTC 24 |
| Peak memory | 253232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086570466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2086570466 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.420047864 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 219293668291 ps |
| CPU time | 3412.87 seconds |
| Started | Sep 24 01:41:55 PM UTC 24 |
| Finished | Sep 24 02:39:33 PM UTC 24 |
| Peak memory | 3099620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420047864 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.420047864 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.1602672206 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 4549125859 ps |
| CPU time | 515.18 seconds |
| Started | Sep 24 01:42:01 PM UTC 24 |
| Finished | Sep 24 01:50:44 PM UTC 24 |
| Peak memory | 361752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602672206 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1602672206 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.3804867263 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2932664810 ps |
| CPU time | 69.39 seconds |
| Started | Sep 24 01:41:42 PM UTC 24 |
| Finished | Sep 24 01:42:54 PM UTC 24 |
| Peak memory | 236632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804867263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3804867263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.825537474 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2834489659 ps |
| CPU time | 189.25 seconds |
| Started | Sep 24 01:43:29 PM UTC 24 |
| Finished | Sep 24 01:46:42 PM UTC 24 |
| Peak memory | 269876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825537474 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.825537474 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.2863686696 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 42247193 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 01:44:56 PM UTC 24 |
| Finished | Sep 24 01:44:59 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863686696 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2863686696 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_app.1789096229 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3250491411 ps |
| CPU time | 85.45 seconds |
| Started | Sep 24 01:44:09 PM UTC 24 |
| Finished | Sep 24 01:45:36 PM UTC 24 |
| Peak memory | 300016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789096229 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1789096229 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.17079219 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 8705338731 ps |
| CPU time | 754.94 seconds |
| Started | Sep 24 01:44:02 PM UTC 24 |
| Finished | Sep 24 01:56:47 PM UTC 24 |
| Peak memory | 246816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17079219 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.17079219 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.1628450007 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 37059424106 ps |
| CPU time | 288.26 seconds |
| Started | Sep 24 01:44:10 PM UTC 24 |
| Finished | Sep 24 01:49:03 PM UTC 24 |
| Peak memory | 404460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628450007 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1628450007 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_error.1289734059 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 96504983678 ps |
| CPU time | 425.32 seconds |
| Started | Sep 24 01:44:37 PM UTC 24 |
| Finished | Sep 24 01:51:48 PM UTC 24 |
| Peak memory | 525296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289734059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1289734059 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.2828303404 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 4025977154 ps |
| CPU time | 13.57 seconds |
| Started | Sep 24 01:44:38 PM UTC 24 |
| Finished | Sep 24 01:44:53 PM UTC 24 |
| Peak memory | 228672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828303404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2828303404 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.1382408162 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 204756699 ps |
| CPU time | 5.83 seconds |
| Started | Sep 24 01:44:52 PM UTC 24 |
| Finished | Sep 24 01:44:59 PM UTC 24 |
| Peak memory | 235752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382408162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1382408162 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.1054486732 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 31913738306 ps |
| CPU time | 916.35 seconds |
| Started | Sep 24 01:43:38 PM UTC 24 |
| Finished | Sep 24 01:59:07 PM UTC 24 |
| Peak memory | 687080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054486732 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.1054486732 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.894986983 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 9793755140 ps |
| CPU time | 344.57 seconds |
| Started | Sep 24 01:43:57 PM UTC 24 |
| Finished | Sep 24 01:49:47 PM UTC 24 |
| Peak memory | 341160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894986983 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.894986983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.658146958 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 6332644831 ps |
| CPU time | 103.68 seconds |
| Started | Sep 24 01:43:32 PM UTC 24 |
| Finished | Sep 24 01:45:18 PM UTC 24 |
| Peak memory | 236720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658146958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.658146958 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.4202349159 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 18019244154 ps |
| CPU time | 313.1 seconds |
| Started | Sep 24 01:44:54 PM UTC 24 |
| Finished | Sep 24 01:50:12 PM UTC 24 |
| Peak memory | 353708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202349159 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.4202349159 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.47963630 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 22474686 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 01:46:10 PM UTC 24 |
| Finished | Sep 24 01:46:13 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47963630 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.47963630 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_app.2833302609 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 8809202170 ps |
| CPU time | 208.35 seconds |
| Started | Sep 24 01:45:17 PM UTC 24 |
| Finished | Sep 24 01:48:48 PM UTC 24 |
| Peak memory | 384200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833302609 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2833302609 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.1392147771 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 8583895019 ps |
| CPU time | 989.97 seconds |
| Started | Sep 24 01:45:07 PM UTC 24 |
| Finished | Sep 24 02:01:49 PM UTC 24 |
| Peak memory | 250924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392147771 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1392147771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.4018200277 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 18662361663 ps |
| CPU time | 553.64 seconds |
| Started | Sep 24 01:45:19 PM UTC 24 |
| Finished | Sep 24 01:54:40 PM UTC 24 |
| Peak memory | 519212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018200277 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.4018200277 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_error.3034928406 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 47246027785 ps |
| CPU time | 105.29 seconds |
| Started | Sep 24 01:45:37 PM UTC 24 |
| Finished | Sep 24 01:47:24 PM UTC 24 |
| Peak memory | 310252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034928406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3034928406 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.1281335197 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 660970138 ps |
| CPU time | 9.61 seconds |
| Started | Sep 24 01:45:39 PM UTC 24 |
| Finished | Sep 24 01:45:50 PM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281335197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1281335197 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.2109185559 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 27874527 ps |
| CPU time | 2.14 seconds |
| Started | Sep 24 01:45:50 PM UTC 24 |
| Finished | Sep 24 01:45:53 PM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109185559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2109185559 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.1554483029 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 64131355488 ps |
| CPU time | 2899.16 seconds |
| Started | Sep 24 01:44:59 PM UTC 24 |
| Finished | Sep 24 02:33:54 PM UTC 24 |
| Peak memory | 3089380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554483029 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.1554483029 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.275093811 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3994277733 ps |
| CPU time | 110.11 seconds |
| Started | Sep 24 01:45:01 PM UTC 24 |
| Finished | Sep 24 01:46:53 PM UTC 24 |
| Peak memory | 322788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275093811 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.275093811 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.1899236782 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 244549905 ps |
| CPU time | 6.49 seconds |
| Started | Sep 24 01:44:58 PM UTC 24 |
| Finished | Sep 24 01:45:06 PM UTC 24 |
| Peak memory | 236376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899236782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1899236782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.2203755265 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 101407689685 ps |
| CPU time | 2680.32 seconds |
| Started | Sep 24 01:45:54 PM UTC 24 |
| Finished | Sep 24 02:31:08 PM UTC 24 |
| Peak memory | 1019264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203755265 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2203755265 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.508425880 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 29186782 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 01:47:40 PM UTC 24 |
| Finished | Sep 24 01:47:42 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508425880 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.508425880 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_app.2271380294 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1584296938 ps |
| CPU time | 38.94 seconds |
| Started | Sep 24 01:46:43 PM UTC 24 |
| Finished | Sep 24 01:47:23 PM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271380294 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2271380294 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.3070272247 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 12272407171 ps |
| CPU time | 123.96 seconds |
| Started | Sep 24 01:46:34 PM UTC 24 |
| Finished | Sep 24 01:48:41 PM UTC 24 |
| Peak memory | 246980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070272247 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3070272247 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.2876595388 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 14615300768 ps |
| CPU time | 489.33 seconds |
| Started | Sep 24 01:46:54 PM UTC 24 |
| Finished | Sep 24 01:55:10 PM UTC 24 |
| Peak memory | 517084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876595388 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2876595388 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_error.4268948101 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 50518549655 ps |
| CPU time | 391.2 seconds |
| Started | Sep 24 01:46:55 PM UTC 24 |
| Finished | Sep 24 01:53:32 PM UTC 24 |
| Peak memory | 488484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268948101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.4268948101 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.2467474820 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 4233957383 ps |
| CPU time | 15.95 seconds |
| Started | Sep 24 01:47:24 PM UTC 24 |
| Finished | Sep 24 01:47:41 PM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467474820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2467474820 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.754021526 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 431743379 ps |
| CPU time | 14.12 seconds |
| Started | Sep 24 01:47:25 PM UTC 24 |
| Finished | Sep 24 01:47:41 PM UTC 24 |
| Peak memory | 246692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754021526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.754021526 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.505016153 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 201537988418 ps |
| CPU time | 4116.38 seconds |
| Started | Sep 24 01:46:16 PM UTC 24 |
| Finished | Sep 24 02:55:40 PM UTC 24 |
| Peak memory | 3734596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505016153 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.505016153 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.2431517170 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 23932410925 ps |
| CPU time | 581.46 seconds |
| Started | Sep 24 01:46:24 PM UTC 24 |
| Finished | Sep 24 01:56:14 PM UTC 24 |
| Peak memory | 392252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431517170 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2431517170 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.1991364228 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 12463853639 ps |
| CPU time | 82.64 seconds |
| Started | Sep 24 01:46:13 PM UTC 24 |
| Finished | Sep 24 01:47:38 PM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991364228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1991364228 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.3581976234 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 78453672335 ps |
| CPU time | 3429.07 seconds |
| Started | Sep 24 01:47:31 PM UTC 24 |
| Finished | Sep 24 02:45:26 PM UTC 24 |
| Peak memory | 1221620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581976234 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3581976234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.1283289789 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 13793421 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 01:49:04 PM UTC 24 |
| Finished | Sep 24 01:49:06 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283289789 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1283289789 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_app.2209309861 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 3979771506 ps |
| CPU time | 120.31 seconds |
| Started | Sep 24 01:47:48 PM UTC 24 |
| Finished | Sep 24 01:49:51 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209309861 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2209309861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.323718122 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 6951356267 ps |
| CPU time | 181.75 seconds |
| Started | Sep 24 01:47:47 PM UTC 24 |
| Finished | Sep 24 01:50:52 PM UTC 24 |
| Peak memory | 240668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323718122 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.323718122 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.3967016033 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 11133855451 ps |
| CPU time | 303.88 seconds |
| Started | Sep 24 01:48:41 PM UTC 24 |
| Finished | Sep 24 01:53:50 PM UTC 24 |
| Peak memory | 449572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967016033 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3967016033 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_error.1285748525 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 91123303453 ps |
| CPU time | 380.72 seconds |
| Started | Sep 24 01:48:48 PM UTC 24 |
| Finished | Sep 24 01:55:15 PM UTC 24 |
| Peak memory | 478244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285748525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1285748525 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.3398198453 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 643821352 ps |
| CPU time | 8.4 seconds |
| Started | Sep 24 01:48:49 PM UTC 24 |
| Finished | Sep 24 01:48:59 PM UTC 24 |
| Peak memory | 230420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398198453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3398198453 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.1776782288 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 110931108 ps |
| CPU time | 2.2 seconds |
| Started | Sep 24 01:48:59 PM UTC 24 |
| Finished | Sep 24 01:49:03 PM UTC 24 |
| Peak memory | 234724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776782288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1776782288 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.166154697 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 43892333484 ps |
| CPU time | 920.29 seconds |
| Started | Sep 24 01:47:43 PM UTC 24 |
| Finished | Sep 24 02:03:16 PM UTC 24 |
| Peak memory | 1160424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166154697 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.166154697 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.3171552436 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3735637163 ps |
| CPU time | 308.73 seconds |
| Started | Sep 24 01:47:43 PM UTC 24 |
| Finished | Sep 24 01:52:56 PM UTC 24 |
| Peak memory | 334864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171552436 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3171552436 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.3026992447 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 108442842 ps |
| CPU time | 4.36 seconds |
| Started | Sep 24 01:47:42 PM UTC 24 |
| Finished | Sep 24 01:47:47 PM UTC 24 |
| Peak memory | 236460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026992447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3026992447 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.1816330030 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3709318595 ps |
| CPU time | 78.79 seconds |
| Started | Sep 24 01:49:04 PM UTC 24 |
| Finished | Sep 24 01:50:24 PM UTC 24 |
| Peak memory | 252988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816330030 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1816330030 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.152016543 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 22914291 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 01:49:52 PM UTC 24 |
| Finished | Sep 24 01:49:54 PM UTC 24 |
| Peak memory | 226768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152016543 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.152016543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_app.1486352693 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 301336782 ps |
| CPU time | 11.27 seconds |
| Started | Sep 24 01:49:17 PM UTC 24 |
| Finished | Sep 24 01:49:29 PM UTC 24 |
| Peak memory | 246192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486352693 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1486352693 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.1176153696 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 45811564557 ps |
| CPU time | 986.98 seconds |
| Started | Sep 24 01:49:15 PM UTC 24 |
| Finished | Sep 24 02:05:55 PM UTC 24 |
| Peak memory | 250884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176153696 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1176153696 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.2770046989 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 4086734138 ps |
| CPU time | 240.32 seconds |
| Started | Sep 24 01:49:25 PM UTC 24 |
| Finished | Sep 24 01:53:30 PM UTC 24 |
| Peak memory | 302116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770046989 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2770046989 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_error.2003750529 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4088045525 ps |
| CPU time | 67.66 seconds |
| Started | Sep 24 01:49:30 PM UTC 24 |
| Finished | Sep 24 01:50:40 PM UTC 24 |
| Peak memory | 267416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003750529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2003750529 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.1088914996 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 7814729589 ps |
| CPU time | 17.61 seconds |
| Started | Sep 24 01:49:32 PM UTC 24 |
| Finished | Sep 24 01:49:51 PM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088914996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1088914996 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.2098265010 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 79780661 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 01:49:48 PM UTC 24 |
| Finished | Sep 24 01:49:51 PM UTC 24 |
| Peak memory | 234060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098265010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2098265010 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.637962965 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 614286916 ps |
| CPU time | 6.49 seconds |
| Started | Sep 24 01:49:07 PM UTC 24 |
| Finished | Sep 24 01:49:14 PM UTC 24 |
| Peak memory | 246868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637962965 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.637962965 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.3703706402 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 6823296497 ps |
| CPU time | 310.91 seconds |
| Started | Sep 24 01:49:11 PM UTC 24 |
| Finished | Sep 24 01:54:27 PM UTC 24 |
| Peak memory | 324696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703706402 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3703706402 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.3520883884 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1355271640 ps |
| CPU time | 11.77 seconds |
| Started | Sep 24 01:49:04 PM UTC 24 |
| Finished | Sep 24 01:49:17 PM UTC 24 |
| Peak memory | 236652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520883884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3520883884 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.1493361542 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 19707790120 ps |
| CPU time | 1594.83 seconds |
| Started | Sep 24 01:49:52 PM UTC 24 |
| Finished | Sep 24 02:16:46 PM UTC 24 |
| Peak memory | 648736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493361542 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1493361542 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.1220432487 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 41884004 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 01:51:03 PM UTC 24 |
| Finished | Sep 24 01:51:05 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220432487 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1220432487 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_app.2046482771 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 42059845474 ps |
| CPU time | 297.08 seconds |
| Started | Sep 24 01:50:26 PM UTC 24 |
| Finished | Sep 24 01:55:28 PM UTC 24 |
| Peak memory | 441552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046482771 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.2046482771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.1337872006 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 13454101244 ps |
| CPU time | 1306.4 seconds |
| Started | Sep 24 01:50:25 PM UTC 24 |
| Finished | Sep 24 02:12:28 PM UTC 24 |
| Peak memory | 254996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337872006 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1337872006 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.2654994811 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 9014116866 ps |
| CPU time | 195.13 seconds |
| Started | Sep 24 01:50:40 PM UTC 24 |
| Finished | Sep 24 01:53:59 PM UTC 24 |
| Peak memory | 351216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654994811 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2654994811 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_error.1046933518 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1043187833 ps |
| CPU time | 29.54 seconds |
| Started | Sep 24 01:50:45 PM UTC 24 |
| Finished | Sep 24 01:51:16 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046933518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1046933518 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.2309013473 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1360752927 ps |
| CPU time | 4.56 seconds |
| Started | Sep 24 01:50:53 PM UTC 24 |
| Finished | Sep 24 01:50:58 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309013473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2309013473 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.1597231181 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 36905905 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 01:50:59 PM UTC 24 |
| Finished | Sep 24 01:51:02 PM UTC 24 |
| Peak memory | 232420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597231181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1597231181 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.1899910580 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 29087471402 ps |
| CPU time | 992.02 seconds |
| Started | Sep 24 01:49:55 PM UTC 24 |
| Finished | Sep 24 02:06:39 PM UTC 24 |
| Peak memory | 1178704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899910580 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.1899910580 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.2127004861 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 15981179604 ps |
| CPU time | 146.81 seconds |
| Started | Sep 24 01:50:13 PM UTC 24 |
| Finished | Sep 24 01:52:42 PM UTC 24 |
| Peak memory | 345320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127004861 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2127004861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.2789334569 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 22343038455 ps |
| CPU time | 129.48 seconds |
| Started | Sep 24 01:49:53 PM UTC 24 |
| Finished | Sep 24 01:52:05 PM UTC 24 |
| Peak memory | 238568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789334569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2789334569 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.2382711138 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 303904572313 ps |
| CPU time | 2581 seconds |
| Started | Sep 24 01:51:01 PM UTC 24 |
| Finished | Sep 24 02:34:33 PM UTC 24 |
| Peak memory | 1666680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382711138 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2382711138 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.3969737791 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 11174890 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 01:52:22 PM UTC 24 |
| Finished | Sep 24 01:52:24 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969737791 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3969737791 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_app.1459900886 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 6529520937 ps |
| CPU time | 34.92 seconds |
| Started | Sep 24 01:51:42 PM UTC 24 |
| Finished | Sep 24 01:52:19 PM UTC 24 |
| Peak memory | 238632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459900886 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1459900886 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.2994085794 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 24227980514 ps |
| CPU time | 1235.93 seconds |
| Started | Sep 24 01:51:22 PM UTC 24 |
| Finished | Sep 24 02:12:15 PM UTC 24 |
| Peak memory | 255004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994085794 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2994085794 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.3427329126 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2218565608 ps |
| CPU time | 132.43 seconds |
| Started | Sep 24 01:51:49 PM UTC 24 |
| Finished | Sep 24 01:54:05 PM UTC 24 |
| Peak memory | 263344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427329126 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3427329126 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_error.2761770428 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 96480376890 ps |
| CPU time | 506.98 seconds |
| Started | Sep 24 01:52:06 PM UTC 24 |
| Finished | Sep 24 02:00:39 PM UTC 24 |
| Peak memory | 638188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761770428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2761770428 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.2500253327 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4904173086 ps |
| CPU time | 11.33 seconds |
| Started | Sep 24 01:52:06 PM UTC 24 |
| Finished | Sep 24 01:52:18 PM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500253327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2500253327 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.2012362049 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 75184406 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 01:52:19 PM UTC 24 |
| Finished | Sep 24 01:52:21 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012362049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2012362049 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.1316143232 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1995770822 ps |
| CPU time | 269.89 seconds |
| Started | Sep 24 01:51:06 PM UTC 24 |
| Finished | Sep 24 01:55:40 PM UTC 24 |
| Peak memory | 349108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316143232 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.1316143232 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.363403993 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 9856983496 ps |
| CPU time | 289.67 seconds |
| Started | Sep 24 01:51:17 PM UTC 24 |
| Finished | Sep 24 01:56:11 PM UTC 24 |
| Peak memory | 435492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363403993 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.363403993 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.2975228689 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 583762813 ps |
| CPU time | 14.31 seconds |
| Started | Sep 24 01:51:06 PM UTC 24 |
| Finished | Sep 24 01:51:21 PM UTC 24 |
| Peak memory | 236592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975228689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2975228689 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.2773621944 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 7733505322 ps |
| CPU time | 634.41 seconds |
| Started | Sep 24 01:52:20 PM UTC 24 |
| Finished | Sep 24 02:03:02 PM UTC 24 |
| Peak memory | 312680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773621944 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2773621944 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.2892785500 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 49381171 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 12:54:45 PM UTC 24 |
| Finished | Sep 24 12:54:47 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892785500 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2892785500 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_app.2908314291 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 80959496115 ps |
| CPU time | 574.63 seconds |
| Started | Sep 24 12:53:00 PM UTC 24 |
| Finished | Sep 24 01:02:43 PM UTC 24 |
| Peak memory | 523244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908314291 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2908314291 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2689859130 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 17680810956 ps |
| CPU time | 141.64 seconds |
| Started | Sep 24 12:53:03 PM UTC 24 |
| Finished | Sep 24 12:55:28 PM UTC 24 |
| Peak memory | 297960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689859130 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2689859130 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.2822903082 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 9476680755 ps |
| CPU time | 1160.72 seconds |
| Started | Sep 24 12:51:57 PM UTC 24 |
| Finished | Sep 24 01:11:32 PM UTC 24 |
| Peak memory | 250916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822903082 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2822903082 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3048130565 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1490624333 ps |
| CPU time | 67.02 seconds |
| Started | Sep 24 12:54:29 PM UTC 24 |
| Finished | Sep 24 12:55:38 PM UTC 24 |
| Peak memory | 246624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048130565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3048130565 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.128003320 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 113082333 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 12:54:30 PM UTC 24 |
| Finished | Sep 24 12:54:33 PM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128003320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.128003320 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.3515843444 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 10491693752 ps |
| CPU time | 40.37 seconds |
| Started | Sep 24 12:54:31 PM UTC 24 |
| Finished | Sep 24 12:55:13 PM UTC 24 |
| Peak memory | 236560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515843444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3515843444 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1995510982 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3816262035 ps |
| CPU time | 92.49 seconds |
| Started | Sep 24 12:53:42 PM UTC 24 |
| Finished | Sep 24 12:55:17 PM UTC 24 |
| Peak memory | 257020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995510982 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1995510982 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_error.1267348196 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 28768414111 ps |
| CPU time | 536.9 seconds |
| Started | Sep 24 12:53:55 PM UTC 24 |
| Finished | Sep 24 01:02:59 PM UTC 24 |
| Peak memory | 642080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267348196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1267348196 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.2839371539 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1728904779 ps |
| CPU time | 7.01 seconds |
| Started | Sep 24 12:54:22 PM UTC 24 |
| Finished | Sep 24 12:54:30 PM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839371539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2839371539 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.1437263885 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 58792144 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 12:54:33 PM UTC 24 |
| Finished | Sep 24 12:54:36 PM UTC 24 |
| Peak memory | 234512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437263885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1437263885 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.4285580775 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 613987229989 ps |
| CPU time | 4426.08 seconds |
| Started | Sep 24 12:51:49 PM UTC 24 |
| Finished | Sep 24 02:06:25 PM UTC 24 |
| Peak memory | 3890248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285580775 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.4285580775 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.2460319653 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 33066564308 ps |
| CPU time | 295.18 seconds |
| Started | Sep 24 12:53:48 PM UTC 24 |
| Finished | Sep 24 12:58:48 PM UTC 24 |
| Peak memory | 312728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460319653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2460319653 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.895154069 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 31343542253 ps |
| CPU time | 138.79 seconds |
| Started | Sep 24 12:54:41 PM UTC 24 |
| Finished | Sep 24 12:57:03 PM UTC 24 |
| Peak memory | 317612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895154069 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.895154069 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.3753437959 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 16465370539 ps |
| CPU time | 452.8 seconds |
| Started | Sep 24 12:51:52 PM UTC 24 |
| Finished | Sep 24 12:59:31 PM UTC 24 |
| Peak memory | 363504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753437959 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3753437959 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.2425312757 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 7259119134 ps |
| CPU time | 58.13 seconds |
| Started | Sep 24 12:51:48 PM UTC 24 |
| Finished | Sep 24 12:52:47 PM UTC 24 |
| Peak memory | 236628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425312757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2425312757 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.3625603755 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 250633839864 ps |
| CPU time | 2105.49 seconds |
| Started | Sep 24 12:54:37 PM UTC 24 |
| Finished | Sep 24 01:30:08 PM UTC 24 |
| Peak memory | 1056140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625603755 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3625603755 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.881219496 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 86252611 ps |
| CPU time | 4.04 seconds |
| Started | Sep 24 12:52:48 PM UTC 24 |
| Finished | Sep 24 12:52:53 PM UTC 24 |
| Peak memory | 236468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881219496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.881219496 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.2368808619 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 147028032 ps |
| CPU time | 4.56 seconds |
| Started | Sep 24 12:52:54 PM UTC 24 |
| Finished | Sep 24 12:53:00 PM UTC 24 |
| Peak memory | 236408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368808619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2368808619 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.4045150800 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2782111500 ps |
| CPU time | 58.95 seconds |
| Started | Sep 24 12:52:02 PM UTC 24 |
| Finished | Sep 24 12:53:03 PM UTC 24 |
| Peak memory | 236668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045150800 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4045150800 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.1598052498 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 124016776646 ps |
| CPU time | 2919.6 seconds |
| Started | Sep 24 12:52:04 PM UTC 24 |
| Finished | Sep 24 01:41:21 PM UTC 24 |
| Peak memory | 3079060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598052498 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1598052498 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3534933241 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 492734140539 ps |
| CPU time | 2314.66 seconds |
| Started | Sep 24 12:52:25 PM UTC 24 |
| Finished | Sep 24 01:31:29 PM UTC 24 |
| Peak memory | 2343844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534933241 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3534933241 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.4071499753 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 9556782083 ps |
| CPU time | 1301.8 seconds |
| Started | Sep 24 12:52:30 PM UTC 24 |
| Finished | Sep 24 01:14:28 PM UTC 24 |
| Peak memory | 705436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071499753 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4071499753 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.540913371 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 15219064810 ps |
| CPU time | 207.07 seconds |
| Started | Sep 24 12:52:39 PM UTC 24 |
| Finished | Sep 24 12:56:10 PM UTC 24 |
| Peak memory | 291936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540913371 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.540913371 +ena ble_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.1277806588 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 113655786999 ps |
| CPU time | 2686.2 seconds |
| Started | Sep 24 12:52:46 PM UTC 24 |
| Finished | Sep 24 01:38:05 PM UTC 24 |
| Peak memory | 2976656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277806588 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1277806588 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.4204564188 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 30022893 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 01:53:55 PM UTC 24 |
| Finished | Sep 24 01:53:58 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204564188 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.4204564188 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_app.2955299673 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 30700253192 ps |
| CPU time | 235.55 seconds |
| Started | Sep 24 01:52:53 PM UTC 24 |
| Finished | Sep 24 01:56:53 PM UTC 24 |
| Peak memory | 386076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955299673 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2955299673 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.835076177 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 27414641155 ps |
| CPU time | 1828.54 seconds |
| Started | Sep 24 01:52:48 PM UTC 24 |
| Finished | Sep 24 02:23:42 PM UTC 24 |
| Peak memory | 257056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835076177 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.835076177 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_error.464542730 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 4832318934 ps |
| CPU time | 117 seconds |
| Started | Sep 24 01:53:31 PM UTC 24 |
| Finished | Sep 24 01:55:30 PM UTC 24 |
| Peak memory | 269344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464542730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.464542730 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2652353116 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 4477129322 ps |
| CPU time | 17.94 seconds |
| Started | Sep 24 01:53:33 PM UTC 24 |
| Finished | Sep 24 01:53:52 PM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652353116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2652353116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.3164059466 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 82604446 ps |
| CPU time | 2.5 seconds |
| Started | Sep 24 01:53:51 PM UTC 24 |
| Finished | Sep 24 01:53:54 PM UTC 24 |
| Peak memory | 234532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164059466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3164059466 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.1649922045 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 468028083326 ps |
| CPU time | 5190.5 seconds |
| Started | Sep 24 01:52:26 PM UTC 24 |
| Finished | Sep 24 03:19:58 PM UTC 24 |
| Peak memory | 4953204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649922045 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.1649922045 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.798318737 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2432330601 ps |
| CPU time | 118.64 seconds |
| Started | Sep 24 01:52:43 PM UTC 24 |
| Finished | Sep 24 01:54:44 PM UTC 24 |
| Peak memory | 267492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798318737 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.798318737 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.3612500828 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 925642584 ps |
| CPU time | 26.16 seconds |
| Started | Sep 24 01:52:25 PM UTC 24 |
| Finished | Sep 24 01:52:53 PM UTC 24 |
| Peak memory | 236428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612500828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3612500828 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.4093924406 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 7892421741 ps |
| CPU time | 599.38 seconds |
| Started | Sep 24 01:53:53 PM UTC 24 |
| Finished | Sep 24 02:04:00 PM UTC 24 |
| Peak memory | 329096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093924406 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.4093924406 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.3898437536 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 18669191 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 01:55:11 PM UTC 24 |
| Finished | Sep 24 01:55:14 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898437536 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3898437536 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_app.2095188795 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 19490889743 ps |
| CPU time | 361.85 seconds |
| Started | Sep 24 01:54:28 PM UTC 24 |
| Finished | Sep 24 02:00:35 PM UTC 24 |
| Peak memory | 414696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095188795 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2095188795 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.4148310558 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 12401036447 ps |
| CPU time | 1488.07 seconds |
| Started | Sep 24 01:54:19 PM UTC 24 |
| Finished | Sep 24 02:19:26 PM UTC 24 |
| Peak memory | 255204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148310558 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.4148310558 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.1710480528 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 9741991462 ps |
| CPU time | 72.22 seconds |
| Started | Sep 24 01:54:41 PM UTC 24 |
| Finished | Sep 24 01:55:55 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710480528 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1710480528 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_error.2994901606 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 19109290766 ps |
| CPU time | 493.04 seconds |
| Started | Sep 24 01:54:44 PM UTC 24 |
| Finished | Sep 24 02:03:03 PM UTC 24 |
| Peak memory | 592936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994901606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2994901606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.4031447615 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1773083536 ps |
| CPU time | 11.61 seconds |
| Started | Sep 24 01:54:45 PM UTC 24 |
| Finished | Sep 24 01:54:58 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031447615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.4031447615 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.3318524996 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 56317871 ps |
| CPU time | 2.34 seconds |
| Started | Sep 24 01:54:59 PM UTC 24 |
| Finished | Sep 24 01:55:02 PM UTC 24 |
| Peak memory | 234572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318524996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3318524996 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.655694957 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 15682109245 ps |
| CPU time | 2022 seconds |
| Started | Sep 24 01:54:00 PM UTC 24 |
| Finished | Sep 24 02:28:07 PM UTC 24 |
| Peak memory | 1111212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655694957 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.655694957 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.1154810846 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 19599645581 ps |
| CPU time | 644.77 seconds |
| Started | Sep 24 01:54:05 PM UTC 24 |
| Finished | Sep 24 02:05:00 PM UTC 24 |
| Peak memory | 650276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154810846 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1154810846 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.81408446 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 7632708801 ps |
| CPU time | 43.4 seconds |
| Started | Sep 24 01:53:58 PM UTC 24 |
| Finished | Sep 24 01:54:43 PM UTC 24 |
| Peak memory | 236516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81408446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.81408446 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.3488958653 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 46521455172 ps |
| CPU time | 822.76 seconds |
| Started | Sep 24 01:55:03 PM UTC 24 |
| Finished | Sep 24 02:08:57 PM UTC 24 |
| Peak memory | 728152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488958653 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3488958653 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.1923974594 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 17857402 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 01:56:12 PM UTC 24 |
| Finished | Sep 24 01:56:14 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923974594 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1923974594 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_app.1882315437 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 7316889723 ps |
| CPU time | 239.23 seconds |
| Started | Sep 24 01:55:32 PM UTC 24 |
| Finished | Sep 24 01:59:35 PM UTC 24 |
| Peak memory | 398420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882315437 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1882315437 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.1145110594 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 31947385855 ps |
| CPU time | 1527.33 seconds |
| Started | Sep 24 01:55:31 PM UTC 24 |
| Finished | Sep 24 02:21:18 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145110594 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1145110594 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.3283000623 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 45125055902 ps |
| CPU time | 445.64 seconds |
| Started | Sep 24 01:55:37 PM UTC 24 |
| Finished | Sep 24 02:03:09 PM UTC 24 |
| Peak memory | 451672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283000623 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3283000623 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_error.541461096 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1410215781 ps |
| CPU time | 135.09 seconds |
| Started | Sep 24 01:55:41 PM UTC 24 |
| Finished | Sep 24 01:57:59 PM UTC 24 |
| Peak memory | 279516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541461096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.541461096 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.3468767368 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1190351432 ps |
| CPU time | 4.74 seconds |
| Started | Sep 24 01:55:56 PM UTC 24 |
| Finished | Sep 24 01:56:02 PM UTC 24 |
| Peak memory | 228600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468767368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3468767368 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.4053055359 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 117379637 ps |
| CPU time | 2.14 seconds |
| Started | Sep 24 01:56:03 PM UTC 24 |
| Finished | Sep 24 01:56:06 PM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053055359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.4053055359 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1945533708 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 22700613689 ps |
| CPU time | 2852.05 seconds |
| Started | Sep 24 01:55:15 PM UTC 24 |
| Finished | Sep 24 02:43:24 PM UTC 24 |
| Peak memory | 1571920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945533708 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1945533708 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.2905436486 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2468033413 ps |
| CPU time | 125.46 seconds |
| Started | Sep 24 01:55:28 PM UTC 24 |
| Finished | Sep 24 01:57:37 PM UTC 24 |
| Peak memory | 263148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905436486 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2905436486 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.3085337791 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1925286491 ps |
| CPU time | 15.49 seconds |
| Started | Sep 24 01:55:14 PM UTC 24 |
| Finished | Sep 24 01:55:31 PM UTC 24 |
| Peak memory | 236400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085337791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3085337791 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.2329776049 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 60937023864 ps |
| CPU time | 2803.31 seconds |
| Started | Sep 24 01:56:07 PM UTC 24 |
| Finished | Sep 24 02:43:25 PM UTC 24 |
| Peak memory | 1758768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329776049 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2329776049 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.543459179 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 46619290 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 01:58:26 PM UTC 24 |
| Finished | Sep 24 01:58:28 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543459179 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.543459179 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_app.154884783 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 5683885403 ps |
| CPU time | 340.18 seconds |
| Started | Sep 24 01:57:07 PM UTC 24 |
| Finished | Sep 24 02:02:53 PM UTC 24 |
| Peak memory | 336872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154884783 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.154884783 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.1121453755 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 5576427672 ps |
| CPU time | 657.95 seconds |
| Started | Sep 24 01:56:54 PM UTC 24 |
| Finished | Sep 24 02:08:01 PM UTC 24 |
| Peak memory | 244708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121453755 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1121453755 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.3486251293 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 4260387197 ps |
| CPU time | 64.31 seconds |
| Started | Sep 24 01:57:38 PM UTC 24 |
| Finished | Sep 24 01:58:44 PM UTC 24 |
| Peak memory | 248852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486251293 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3486251293 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_error.242782397 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 7723916487 ps |
| CPU time | 274.96 seconds |
| Started | Sep 24 01:57:59 PM UTC 24 |
| Finished | Sep 24 02:02:39 PM UTC 24 |
| Peak memory | 416752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242782397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.242782397 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.711030138 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 703022828 ps |
| CPU time | 5.79 seconds |
| Started | Sep 24 01:58:14 PM UTC 24 |
| Finished | Sep 24 01:58:21 PM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711030138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.711030138 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.3355239384 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 142713460 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 01:58:21 PM UTC 24 |
| Finished | Sep 24 01:58:25 PM UTC 24 |
| Peak memory | 232008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355239384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3355239384 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.1512127823 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 323454123457 ps |
| CPU time | 3160.46 seconds |
| Started | Sep 24 01:56:15 PM UTC 24 |
| Finished | Sep 24 02:49:33 PM UTC 24 |
| Peak memory | 3054672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512127823 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.1512127823 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.104733130 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 22092254652 ps |
| CPU time | 248 seconds |
| Started | Sep 24 01:56:48 PM UTC 24 |
| Finished | Sep 24 02:01:00 PM UTC 24 |
| Peak memory | 406560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104733130 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.104733130 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.3868608207 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 80255234883 ps |
| CPU time | 116.49 seconds |
| Started | Sep 24 01:56:14 PM UTC 24 |
| Finished | Sep 24 01:58:13 PM UTC 24 |
| Peak memory | 238636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868608207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3868608207 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.4269147555 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 5554766627 ps |
| CPU time | 243.71 seconds |
| Started | Sep 24 01:58:23 PM UTC 24 |
| Finished | Sep 24 02:02:30 PM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269147555 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4269147555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.3029049761 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 26578134 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:00:46 PM UTC 24 |
| Finished | Sep 24 02:00:49 PM UTC 24 |
| Peak memory | 226652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029049761 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3029049761 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_app.3981055148 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 48040648870 ps |
| CPU time | 402.93 seconds |
| Started | Sep 24 01:59:35 PM UTC 24 |
| Finished | Sep 24 02:06:24 PM UTC 24 |
| Peak memory | 482388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981055148 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3981055148 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.1612388571 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 12333093590 ps |
| CPU time | 898.72 seconds |
| Started | Sep 24 01:59:32 PM UTC 24 |
| Finished | Sep 24 02:14:43 PM UTC 24 |
| Peak memory | 253152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612388571 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1612388571 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.1936347842 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 9378111410 ps |
| CPU time | 324.25 seconds |
| Started | Sep 24 01:59:48 PM UTC 24 |
| Finished | Sep 24 02:05:18 PM UTC 24 |
| Peak memory | 439332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936347842 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1936347842 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_error.1131232290 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 58433662853 ps |
| CPU time | 379.35 seconds |
| Started | Sep 24 02:00:06 PM UTC 24 |
| Finished | Sep 24 02:06:32 PM UTC 24 |
| Peak memory | 449564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131232290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1131232290 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.1506453925 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1032744004 ps |
| CPU time | 8.23 seconds |
| Started | Sep 24 02:00:36 PM UTC 24 |
| Finished | Sep 24 02:00:45 PM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506453925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1506453925 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.2743115730 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 165364976 ps |
| CPU time | 2.31 seconds |
| Started | Sep 24 02:00:40 PM UTC 24 |
| Finished | Sep 24 02:00:43 PM UTC 24 |
| Peak memory | 232480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743115730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2743115730 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.3777977705 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 33927143461 ps |
| CPU time | 276 seconds |
| Started | Sep 24 01:58:45 PM UTC 24 |
| Finished | Sep 24 02:03:25 PM UTC 24 |
| Peak memory | 547820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777977705 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.3777977705 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.2436172742 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 22631775719 ps |
| CPU time | 358.23 seconds |
| Started | Sep 24 01:59:08 PM UTC 24 |
| Finished | Sep 24 02:05:12 PM UTC 24 |
| Peak memory | 482340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436172742 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2436172742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.3345014182 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 9704056482 ps |
| CPU time | 91.67 seconds |
| Started | Sep 24 01:58:29 PM UTC 24 |
| Finished | Sep 24 02:00:03 PM UTC 24 |
| Peak memory | 236528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345014182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3345014182 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.622478370 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 64758878824 ps |
| CPU time | 2309.99 seconds |
| Started | Sep 24 02:00:44 PM UTC 24 |
| Finished | Sep 24 02:39:42 PM UTC 24 |
| Peak memory | 1508732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622478370 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.622478370 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.3560215756 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 16348840 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 02:03:07 PM UTC 24 |
| Finished | Sep 24 02:03:10 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560215756 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3560215756 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_app.3433931632 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 16801683082 ps |
| CPU time | 417.79 seconds |
| Started | Sep 24 02:02:08 PM UTC 24 |
| Finished | Sep 24 02:09:11 PM UTC 24 |
| Peak memory | 519208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433931632 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3433931632 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.2208230653 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 31376486584 ps |
| CPU time | 699.13 seconds |
| Started | Sep 24 02:01:50 PM UTC 24 |
| Finished | Sep 24 02:13:39 PM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208230653 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2208230653 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.2621796575 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 20715087337 ps |
| CPU time | 277.42 seconds |
| Started | Sep 24 02:02:32 PM UTC 24 |
| Finished | Sep 24 02:07:14 PM UTC 24 |
| Peak memory | 314460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621796575 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2621796575 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_error.110837936 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 5036817560 ps |
| CPU time | 500.12 seconds |
| Started | Sep 24 02:02:40 PM UTC 24 |
| Finished | Sep 24 02:11:07 PM UTC 24 |
| Peak memory | 375896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110837936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.110837936 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.3390201608 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 7220002907 ps |
| CPU time | 18.08 seconds |
| Started | Sep 24 02:02:53 PM UTC 24 |
| Finished | Sep 24 02:03:12 PM UTC 24 |
| Peak memory | 228540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390201608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3390201608 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.715669481 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 155263036 ps |
| CPU time | 2.27 seconds |
| Started | Sep 24 02:03:03 PM UTC 24 |
| Finished | Sep 24 02:03:06 PM UTC 24 |
| Peak memory | 232464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715669481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.715669481 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.3258958395 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 8150214036 ps |
| CPU time | 397.14 seconds |
| Started | Sep 24 02:01:01 PM UTC 24 |
| Finished | Sep 24 02:07:45 PM UTC 24 |
| Peak memory | 617512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258958395 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.3258958395 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.3154436485 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 4615002894 ps |
| CPU time | 98.14 seconds |
| Started | Sep 24 02:01:36 PM UTC 24 |
| Finished | Sep 24 02:03:17 PM UTC 24 |
| Peak memory | 289764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154436485 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3154436485 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.2832843253 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 6143378573 ps |
| CPU time | 75.99 seconds |
| Started | Sep 24 02:00:49 PM UTC 24 |
| Finished | Sep 24 02:02:07 PM UTC 24 |
| Peak memory | 236636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832843253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2832843253 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.3568247041 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 44192124855 ps |
| CPU time | 452.12 seconds |
| Started | Sep 24 02:03:04 PM UTC 24 |
| Finished | Sep 24 02:10:43 PM UTC 24 |
| Peak memory | 341372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568247041 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3568247041 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.3640357783 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 28208981 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 02:05:01 PM UTC 24 |
| Finished | Sep 24 02:05:03 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640357783 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3640357783 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_app.2552901872 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 11313819336 ps |
| CPU time | 210.09 seconds |
| Started | Sep 24 02:03:18 PM UTC 24 |
| Finished | Sep 24 02:06:52 PM UTC 24 |
| Peak memory | 286036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552901872 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2552901872 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.375622787 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 14266611278 ps |
| CPU time | 1495.84 seconds |
| Started | Sep 24 02:03:17 PM UTC 24 |
| Finished | Sep 24 02:28:31 PM UTC 24 |
| Peak memory | 255012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375622787 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.375622787 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2538897213 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 10290735692 ps |
| CPU time | 469.44 seconds |
| Started | Sep 24 02:03:26 PM UTC 24 |
| Finished | Sep 24 02:11:22 PM UTC 24 |
| Peak memory | 353292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538897213 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2538897213 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_error.1197100724 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 45463406719 ps |
| CPU time | 237.92 seconds |
| Started | Sep 24 02:04:01 PM UTC 24 |
| Finished | Sep 24 02:08:03 PM UTC 24 |
| Peak memory | 422956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197100724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1197100724 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.4217936541 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 867771680 ps |
| CPU time | 11.39 seconds |
| Started | Sep 24 02:04:02 PM UTC 24 |
| Finished | Sep 24 02:04:15 PM UTC 24 |
| Peak memory | 228376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217936541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.4217936541 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.1581743315 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 78462872 ps |
| CPU time | 2.22 seconds |
| Started | Sep 24 02:04:15 PM UTC 24 |
| Finished | Sep 24 02:04:19 PM UTC 24 |
| Peak memory | 234472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581743315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1581743315 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.1370968642 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 10439383227 ps |
| CPU time | 815.59 seconds |
| Started | Sep 24 02:03:10 PM UTC 24 |
| Finished | Sep 24 02:16:57 PM UTC 24 |
| Peak memory | 662504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370968642 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.1370968642 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.4171197160 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 50657757342 ps |
| CPU time | 413.11 seconds |
| Started | Sep 24 02:03:14 PM UTC 24 |
| Finished | Sep 24 02:10:13 PM UTC 24 |
| Peak memory | 517272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171197160 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.4171197160 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.712237291 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1118769221 ps |
| CPU time | 50.08 seconds |
| Started | Sep 24 02:03:09 PM UTC 24 |
| Finished | Sep 24 02:04:01 PM UTC 24 |
| Peak memory | 236592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712237291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.712237291 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.3066581470 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 11515505226 ps |
| CPU time | 301.05 seconds |
| Started | Sep 24 02:04:19 PM UTC 24 |
| Finished | Sep 24 02:09:25 PM UTC 24 |
| Peak memory | 345476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066581470 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3066581470 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.3518649094 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 23906425 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 02:06:40 PM UTC 24 |
| Finished | Sep 24 02:06:42 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518649094 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3518649094 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_app.4207146335 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 13988623044 ps |
| CPU time | 240.94 seconds |
| Started | Sep 24 02:05:31 PM UTC 24 |
| Finished | Sep 24 02:09:36 PM UTC 24 |
| Peak memory | 304088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207146335 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4207146335 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.3825213787 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 59824018804 ps |
| CPU time | 1738.84 seconds |
| Started | Sep 24 02:05:20 PM UTC 24 |
| Finished | Sep 24 02:34:42 PM UTC 24 |
| Peak memory | 256996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825213787 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3825213787 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.3057794844 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 61547159733 ps |
| CPU time | 360.71 seconds |
| Started | Sep 24 02:05:56 PM UTC 24 |
| Finished | Sep 24 02:12:02 PM UTC 24 |
| Peak memory | 474176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057794844 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3057794844 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_error.2538705919 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 46257458022 ps |
| CPU time | 439.52 seconds |
| Started | Sep 24 02:06:26 PM UTC 24 |
| Finished | Sep 24 02:13:51 PM UTC 24 |
| Peak memory | 537576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538705919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2538705919 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.2787766757 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1542263987 ps |
| CPU time | 16.12 seconds |
| Started | Sep 24 02:06:26 PM UTC 24 |
| Finished | Sep 24 02:06:43 PM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787766757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2787766757 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.2358939080 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 90964266 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 02:06:33 PM UTC 24 |
| Finished | Sep 24 02:06:36 PM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358939080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2358939080 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.1191725432 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 15245971009 ps |
| CPU time | 1723.05 seconds |
| Started | Sep 24 02:05:13 PM UTC 24 |
| Finished | Sep 24 02:34:17 PM UTC 24 |
| Peak memory | 1049632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191725432 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.1191725432 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.1250024627 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 15783297437 ps |
| CPU time | 319.17 seconds |
| Started | Sep 24 02:05:19 PM UTC 24 |
| Finished | Sep 24 02:10:43 PM UTC 24 |
| Peak memory | 443372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250024627 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1250024627 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.1495595693 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 615717808 ps |
| CPU time | 24.82 seconds |
| Started | Sep 24 02:05:04 PM UTC 24 |
| Finished | Sep 24 02:05:30 PM UTC 24 |
| Peak memory | 236436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495595693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1495595693 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.3936324915 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 26938976581 ps |
| CPU time | 764.55 seconds |
| Started | Sep 24 02:06:37 PM UTC 24 |
| Finished | Sep 24 02:19:32 PM UTC 24 |
| Peak memory | 415328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936324915 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3936324915 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.549497012 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 18103351 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 02:08:03 PM UTC 24 |
| Finished | Sep 24 02:08:05 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549497012 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.549497012 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_app.1701756093 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 21333563291 ps |
| CPU time | 159.97 seconds |
| Started | Sep 24 02:06:53 PM UTC 24 |
| Finished | Sep 24 02:09:36 PM UTC 24 |
| Peak memory | 330724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701756093 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1701756093 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.4186059143 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 76093787932 ps |
| CPU time | 1059.57 seconds |
| Started | Sep 24 02:06:46 PM UTC 24 |
| Finished | Sep 24 02:24:40 PM UTC 24 |
| Peak memory | 265248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186059143 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.4186059143 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.2875927095 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 52698149964 ps |
| CPU time | 400.88 seconds |
| Started | Sep 24 02:06:58 PM UTC 24 |
| Finished | Sep 24 02:13:45 PM UTC 24 |
| Peak memory | 431172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875927095 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2875927095 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_error.775623491 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 14021388428 ps |
| CPU time | 296.02 seconds |
| Started | Sep 24 02:07:14 PM UTC 24 |
| Finished | Sep 24 02:12:15 PM UTC 24 |
| Peak memory | 332832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775623491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.775623491 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.1312007987 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1007915461 ps |
| CPU time | 11.19 seconds |
| Started | Sep 24 02:07:46 PM UTC 24 |
| Finished | Sep 24 02:07:58 PM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312007987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1312007987 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.3992011432 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 42077926 ps |
| CPU time | 2.08 seconds |
| Started | Sep 24 02:07:59 PM UTC 24 |
| Finished | Sep 24 02:08:02 PM UTC 24 |
| Peak memory | 232612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992011432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3992011432 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3013959936 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 60547265970 ps |
| CPU time | 1439.47 seconds |
| Started | Sep 24 02:06:44 PM UTC 24 |
| Finished | Sep 24 02:31:01 PM UTC 24 |
| Peak memory | 965672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013959936 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3013959936 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.429194960 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 29768518638 ps |
| CPU time | 341.41 seconds |
| Started | Sep 24 02:06:45 PM UTC 24 |
| Finished | Sep 24 02:12:32 PM UTC 24 |
| Peak memory | 443684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429194960 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.429194960 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.3895742342 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 27593631345 ps |
| CPU time | 77.73 seconds |
| Started | Sep 24 02:06:43 PM UTC 24 |
| Finished | Sep 24 02:08:03 PM UTC 24 |
| Peak memory | 236528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895742342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3895742342 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.550666318 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 34780394645 ps |
| CPU time | 1581.7 seconds |
| Started | Sep 24 02:08:02 PM UTC 24 |
| Finished | Sep 24 02:34:43 PM UTC 24 |
| Peak memory | 695392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550666318 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.550666318 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.3750328606 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 44979776 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 02:09:13 PM UTC 24 |
| Finished | Sep 24 02:09:16 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750328606 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3750328606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_app.329806215 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 10373863692 ps |
| CPU time | 86.17 seconds |
| Started | Sep 24 02:08:26 PM UTC 24 |
| Finished | Sep 24 02:09:55 PM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329806215 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.329806215 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.3696427680 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 201692606417 ps |
| CPU time | 1681.6 seconds |
| Started | Sep 24 02:08:11 PM UTC 24 |
| Finished | Sep 24 02:36:35 PM UTC 24 |
| Peak memory | 273436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696427680 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3696427680 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.946072231 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 13237633477 ps |
| CPU time | 407.71 seconds |
| Started | Sep 24 02:08:44 PM UTC 24 |
| Finished | Sep 24 02:15:39 PM UTC 24 |
| Peak memory | 470032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946072231 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.946072231 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_error.1872275796 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 12757587461 ps |
| CPU time | 321.72 seconds |
| Started | Sep 24 02:08:59 PM UTC 24 |
| Finished | Sep 24 02:14:26 PM UTC 24 |
| Peak memory | 334884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872275796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1872275796 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.1958647744 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 841442246 ps |
| CPU time | 4.57 seconds |
| Started | Sep 24 02:09:02 PM UTC 24 |
| Finished | Sep 24 02:09:08 PM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958647744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1958647744 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.4037559800 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 57169929 ps |
| CPU time | 2.34 seconds |
| Started | Sep 24 02:09:09 PM UTC 24 |
| Finished | Sep 24 02:09:13 PM UTC 24 |
| Peak memory | 232412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037559800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.4037559800 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.2802885585 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 88496174703 ps |
| CPU time | 3443.57 seconds |
| Started | Sep 24 02:08:04 PM UTC 24 |
| Finished | Sep 24 03:06:07 PM UTC 24 |
| Peak memory | 3466468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802885585 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.2802885585 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.2795436628 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 17760982767 ps |
| CPU time | 270.92 seconds |
| Started | Sep 24 02:08:06 PM UTC 24 |
| Finished | Sep 24 02:12:42 PM UTC 24 |
| Peak memory | 406604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795436628 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2795436628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.639388030 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 816449602 ps |
| CPU time | 19.98 seconds |
| Started | Sep 24 02:08:04 PM UTC 24 |
| Finished | Sep 24 02:08:25 PM UTC 24 |
| Peak memory | 236436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639388030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.639388030 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.2191731995 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4031587392 ps |
| CPU time | 301.76 seconds |
| Started | Sep 24 02:09:12 PM UTC 24 |
| Finished | Sep 24 02:14:19 PM UTC 24 |
| Peak memory | 351288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191731995 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2191731995 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.2056764540 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 51477454 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 12:57:07 PM UTC 24 |
| Finished | Sep 24 12:57:09 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056764540 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2056764540 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_app.2569174880 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 17613826446 ps |
| CPU time | 523.9 seconds |
| Started | Sep 24 12:55:20 PM UTC 24 |
| Finished | Sep 24 01:04:12 PM UTC 24 |
| Peak memory | 523352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569174880 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2569174880 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.3401756693 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 17802399515 ps |
| CPU time | 259.34 seconds |
| Started | Sep 24 12:55:28 PM UTC 24 |
| Finished | Sep 24 12:59:53 PM UTC 24 |
| Peak memory | 347112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401756693 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3401756693 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.3579190597 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 8038379337 ps |
| CPU time | 440.8 seconds |
| Started | Sep 24 12:55:18 PM UTC 24 |
| Finished | Sep 24 01:02:46 PM UTC 24 |
| Peak memory | 247084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579190597 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3579190597 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1403982637 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1943716781 ps |
| CPU time | 29.56 seconds |
| Started | Sep 24 12:56:35 PM UTC 24 |
| Finished | Sep 24 12:57:06 PM UTC 24 |
| Peak memory | 245072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403982637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1403982637 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.1140141939 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 34366592 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 12:56:53 PM UTC 24 |
| Finished | Sep 24 12:56:55 PM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140141939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1140141939 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.84330013 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2569252177 ps |
| CPU time | 37.72 seconds |
| Started | Sep 24 12:56:54 PM UTC 24 |
| Finished | Sep 24 12:57:34 PM UTC 24 |
| Peak memory | 230800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84330013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_mask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.84330013 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.7344616 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 4789821378 ps |
| CPU time | 120.18 seconds |
| Started | Sep 24 12:55:29 PM UTC 24 |
| Finished | Sep 24 12:57:31 PM UTC 24 |
| Peak memory | 304352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7344616 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.7344616 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_error.3002974961 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 75862538 ps |
| CPU time | 9.26 seconds |
| Started | Sep 24 12:56:11 PM UTC 24 |
| Finished | Sep 24 12:56:21 PM UTC 24 |
| Peak memory | 236524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002974961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3002974961 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.3897647491 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2691941009 ps |
| CPU time | 11.3 seconds |
| Started | Sep 24 12:56:22 PM UTC 24 |
| Finished | Sep 24 12:56:34 PM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897647491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3897647491 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.1625676339 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 23858507244 ps |
| CPU time | 2304.33 seconds |
| Started | Sep 24 12:54:53 PM UTC 24 |
| Finished | Sep 24 01:33:45 PM UTC 24 |
| Peak memory | 1274952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625676339 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.1625676339 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.3964870056 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9809659650 ps |
| CPU time | 290.88 seconds |
| Started | Sep 24 12:55:39 PM UTC 24 |
| Finished | Sep 24 01:00:34 PM UTC 24 |
| Peak memory | 419376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964870056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3964870056 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.1146338985 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 28672914844 ps |
| CPU time | 236.75 seconds |
| Started | Sep 24 12:55:14 PM UTC 24 |
| Finished | Sep 24 12:59:15 PM UTC 24 |
| Peak memory | 410796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146338985 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1146338985 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.2352501968 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1258842641 ps |
| CPU time | 38.51 seconds |
| Started | Sep 24 12:54:48 PM UTC 24 |
| Finished | Sep 24 12:55:28 PM UTC 24 |
| Peak memory | 236500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352501968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2352501968 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.3960529879 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 82549106390 ps |
| CPU time | 2664.8 seconds |
| Started | Sep 24 12:57:02 PM UTC 24 |
| Finished | Sep 24 01:42:00 PM UTC 24 |
| Peak memory | 1646004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960529879 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3960529879 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.394650352 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 36037580 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 12:59:32 PM UTC 24 |
| Finished | Sep 24 12:59:34 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394650352 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.394650352 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_app.4033504456 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 27654920463 ps |
| CPU time | 393.77 seconds |
| Started | Sep 24 12:57:32 PM UTC 24 |
| Finished | Sep 24 01:04:12 PM UTC 24 |
| Peak memory | 492528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033504456 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4033504456 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.3632639235 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 11768685964 ps |
| CPU time | 371.72 seconds |
| Started | Sep 24 12:57:35 PM UTC 24 |
| Finished | Sep 24 01:03:52 PM UTC 24 |
| Peak memory | 431324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632639235 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3632639235 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.3209297863 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 27213778468 ps |
| CPU time | 782.06 seconds |
| Started | Sep 24 12:57:28 PM UTC 24 |
| Finished | Sep 24 01:10:40 PM UTC 24 |
| Peak memory | 248876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209297863 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3209297863 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.1227980237 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 528386800 ps |
| CPU time | 18.3 seconds |
| Started | Sep 24 12:59:10 PM UTC 24 |
| Finished | Sep 24 12:59:30 PM UTC 24 |
| Peak memory | 244640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227980237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1227980237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.2533951971 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 177984342 ps |
| CPU time | 2.17 seconds |
| Started | Sep 24 12:59:16 PM UTC 24 |
| Finished | Sep 24 12:59:19 PM UTC 24 |
| Peak memory | 228284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533951971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2533951971 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.2025304184 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 65262927558 ps |
| CPU time | 75.18 seconds |
| Started | Sep 24 12:59:19 PM UTC 24 |
| Finished | Sep 24 01:00:36 PM UTC 24 |
| Peak memory | 236580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025304184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2025304184 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3349925668 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3897239267 ps |
| CPU time | 84.32 seconds |
| Started | Sep 24 12:57:52 PM UTC 24 |
| Finished | Sep 24 12:59:18 PM UTC 24 |
| Peak memory | 291872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349925668 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3349925668 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_error.470281828 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 17764507034 ps |
| CPU time | 417.9 seconds |
| Started | Sep 24 12:58:34 PM UTC 24 |
| Finished | Sep 24 01:05:38 PM UTC 24 |
| Peak memory | 367648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470281828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.470281828 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.1875521940 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1289829378 ps |
| CPU time | 18.79 seconds |
| Started | Sep 24 12:58:49 PM UTC 24 |
| Finished | Sep 24 12:59:09 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875521940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1875521940 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.2785056446 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 88483772 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 12:59:20 PM UTC 24 |
| Finished | Sep 24 12:59:23 PM UTC 24 |
| Peak memory | 234648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785056446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2785056446 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.1899312848 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 117752089543 ps |
| CPU time | 2908.1 seconds |
| Started | Sep 24 12:57:11 PM UTC 24 |
| Finished | Sep 24 01:46:15 PM UTC 24 |
| Peak memory | 2987044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899312848 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.1899312848 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.3506386605 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2850934668 ps |
| CPU time | 202.36 seconds |
| Started | Sep 24 12:58:31 PM UTC 24 |
| Finished | Sep 24 01:01:57 PM UTC 24 |
| Peak memory | 288092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506386605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3506386605 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.2727622744 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 29448289701 ps |
| CPU time | 213.28 seconds |
| Started | Sep 24 12:57:17 PM UTC 24 |
| Finished | Sep 24 01:00:54 PM UTC 24 |
| Peak memory | 388080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727622744 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2727622744 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.2202566865 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 6350546760 ps |
| CPU time | 81.58 seconds |
| Started | Sep 24 12:57:10 PM UTC 24 |
| Finished | Sep 24 12:58:33 PM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202566865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2202566865 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.3279701742 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 26652161033 ps |
| CPU time | 932.71 seconds |
| Started | Sep 24 12:59:24 PM UTC 24 |
| Finished | Sep 24 01:15:08 PM UTC 24 |
| Peak memory | 994412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279701742 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3279701742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.3047675995 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3890144237 ps |
| CPU time | 276.58 seconds |
| Started | Sep 24 12:59:31 PM UTC 24 |
| Finished | Sep 24 01:04:12 PM UTC 24 |
| Peak memory | 302652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3047675995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_r and_reset.3047675995 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.457541472 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 25791964 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 01:03:09 PM UTC 24 |
| Finished | Sep 24 01:03:11 PM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457541472 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.457541472 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_app.3984782312 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1862579344 ps |
| CPU time | 65.19 seconds |
| Started | Sep 24 01:00:37 PM UTC 24 |
| Finished | Sep 24 01:01:44 PM UTC 24 |
| Peak memory | 267212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984782312 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3984782312 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.868231697 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 21075964585 ps |
| CPU time | 130.69 seconds |
| Started | Sep 24 01:00:55 PM UTC 24 |
| Finished | Sep 24 01:03:08 PM UTC 24 |
| Peak memory | 289820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868231697 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.868231697 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.3612700778 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 10552871422 ps |
| CPU time | 1279.13 seconds |
| Started | Sep 24 01:00:35 PM UTC 24 |
| Finished | Sep 24 01:22:11 PM UTC 24 |
| Peak memory | 252884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612700778 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3612700778 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.1524725933 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 366510057 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 01:02:47 PM UTC 24 |
| Finished | Sep 24 01:02:49 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524725933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1524725933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.1488544615 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 81922851 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 01:02:51 PM UTC 24 |
| Finished | Sep 24 01:02:53 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488544615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1488544615 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.2744860792 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 4177247820 ps |
| CPU time | 71.69 seconds |
| Started | Sep 24 01:02:55 PM UTC 24 |
| Finished | Sep 24 01:04:08 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744860792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2744860792 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3225023384 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5295294531 ps |
| CPU time | 158.5 seconds |
| Started | Sep 24 01:01:45 PM UTC 24 |
| Finished | Sep 24 01:04:27 PM UTC 24 |
| Peak memory | 332832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225023384 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3225023384 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_error.2639212423 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 11320117358 ps |
| CPU time | 382.18 seconds |
| Started | Sep 24 01:02:43 PM UTC 24 |
| Finished | Sep 24 01:09:11 PM UTC 24 |
| Peak memory | 527340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639212423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.2639212423 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.3439152118 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 6315057329 ps |
| CPU time | 24.17 seconds |
| Started | Sep 24 01:02:45 PM UTC 24 |
| Finished | Sep 24 01:03:10 PM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439152118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3439152118 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.1525656664 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 57887912 ps |
| CPU time | 2.47 seconds |
| Started | Sep 24 01:03:00 PM UTC 24 |
| Finished | Sep 24 01:03:03 PM UTC 24 |
| Peak memory | 234540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525656664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1525656664 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.2924877255 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7966969319 ps |
| CPU time | 272.08 seconds |
| Started | Sep 24 12:59:53 PM UTC 24 |
| Finished | Sep 24 01:04:30 PM UTC 24 |
| Peak memory | 523532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924877255 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.2924877255 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.3929949338 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 11379953316 ps |
| CPU time | 432.29 seconds |
| Started | Sep 24 01:01:58 PM UTC 24 |
| Finished | Sep 24 01:09:17 PM UTC 24 |
| Peak memory | 341368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929949338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3929949338 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.3337442378 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 8444962261 ps |
| CPU time | 142.05 seconds |
| Started | Sep 24 01:00:18 PM UTC 24 |
| Finished | Sep 24 01:02:43 PM UTC 24 |
| Peak memory | 324844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337442378 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3337442378 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.2848198847 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5635679971 ps |
| CPU time | 40.95 seconds |
| Started | Sep 24 12:59:35 PM UTC 24 |
| Finished | Sep 24 01:00:18 PM UTC 24 |
| Peak memory | 236500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848198847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2848198847 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.1639192012 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 29503095594 ps |
| CPU time | 2087.89 seconds |
| Started | Sep 24 01:03:03 PM UTC 24 |
| Finished | Sep 24 01:38:19 PM UTC 24 |
| Peak memory | 722308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639192012 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1639192012 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.3052356716 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 37630529 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 01:04:50 PM UTC 24 |
| Finished | Sep 24 01:04:53 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052356716 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3052356716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_app.1664219328 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8871005569 ps |
| CPU time | 344.05 seconds |
| Started | Sep 24 01:03:53 PM UTC 24 |
| Finished | Sep 24 01:09:43 PM UTC 24 |
| Peak memory | 439380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664219328 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1664219328 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.4078670313 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1604877482 ps |
| CPU time | 65.03 seconds |
| Started | Sep 24 01:04:01 PM UTC 24 |
| Finished | Sep 24 01:05:08 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078670313 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.4078670313 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.496911537 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5305132929 ps |
| CPU time | 160.44 seconds |
| Started | Sep 24 01:03:43 PM UTC 24 |
| Finished | Sep 24 01:06:27 PM UTC 24 |
| Peak memory | 236580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496911537 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.496911537 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.4095957525 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 218137362 ps |
| CPU time | 7.02 seconds |
| Started | Sep 24 01:04:25 PM UTC 24 |
| Finished | Sep 24 01:04:33 PM UTC 24 |
| Peak memory | 235648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095957525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.4095957525 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.3141344711 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 73051530 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 01:04:28 PM UTC 24 |
| Finished | Sep 24 01:04:31 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141344711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3141344711 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.861640850 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7544320249 ps |
| CPU time | 53.8 seconds |
| Started | Sep 24 01:04:31 PM UTC 24 |
| Finished | Sep 24 01:05:27 PM UTC 24 |
| Peak memory | 232800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861640850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.861640850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.3268002189 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 8488697306 ps |
| CPU time | 211.89 seconds |
| Started | Sep 24 01:04:09 PM UTC 24 |
| Finished | Sep 24 01:07:45 PM UTC 24 |
| Peak memory | 381988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268002189 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3268002189 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_error.2067983851 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 7296844167 ps |
| CPU time | 329.87 seconds |
| Started | Sep 24 01:04:13 PM UTC 24 |
| Finished | Sep 24 01:09:48 PM UTC 24 |
| Peak memory | 420844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067983851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2067983851 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.462291750 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2072481572 ps |
| CPU time | 10.26 seconds |
| Started | Sep 24 01:04:13 PM UTC 24 |
| Finished | Sep 24 01:04:24 PM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462291750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.462291750 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.3698641786 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 133271277 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 01:04:32 PM UTC 24 |
| Finished | Sep 24 01:04:35 PM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698641786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3698641786 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.3962907052 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 28353255240 ps |
| CPU time | 3768.22 seconds |
| Started | Sep 24 01:03:12 PM UTC 24 |
| Finished | Sep 24 02:06:45 PM UTC 24 |
| Peak memory | 1918088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962907052 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.3962907052 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.1765368586 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4948983248 ps |
| CPU time | 263 seconds |
| Started | Sep 24 01:04:13 PM UTC 24 |
| Finished | Sep 24 01:08:40 PM UTC 24 |
| Peak memory | 327156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765368586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1765368586 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2199510451 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3698273319 ps |
| CPU time | 365.78 seconds |
| Started | Sep 24 01:03:19 PM UTC 24 |
| Finished | Sep 24 01:09:30 PM UTC 24 |
| Peak memory | 322604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199510451 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2199510451 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.755739774 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 19537430385 ps |
| CPU time | 48.64 seconds |
| Started | Sep 24 01:03:11 PM UTC 24 |
| Finished | Sep 24 01:04:01 PM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755739774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.755739774 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.1826402004 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6319112372 ps |
| CPU time | 262.97 seconds |
| Started | Sep 24 01:04:34 PM UTC 24 |
| Finished | Sep 24 01:09:01 PM UTC 24 |
| Peak memory | 306636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826402004 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1826402004 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.1535551185 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 8019511080 ps |
| CPU time | 290.73 seconds |
| Started | Sep 24 01:04:36 PM UTC 24 |
| Finished | Sep 24 01:09:31 PM UTC 24 |
| Peak memory | 318656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1535551185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_r and_reset.1535551185 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.57698733 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 27717794 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 01:08:46 PM UTC 24 |
| Finished | Sep 24 01:08:49 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57698733 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.57698733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_app.2533622682 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 19495954244 ps |
| CPU time | 180.71 seconds |
| Started | Sep 24 01:06:28 PM UTC 24 |
| Finished | Sep 24 01:09:32 PM UTC 24 |
| Peak memory | 322580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533622682 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2533622682 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.446600404 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 883152915 ps |
| CPU time | 46.3 seconds |
| Started | Sep 24 01:06:31 PM UTC 24 |
| Finished | Sep 24 01:07:19 PM UTC 24 |
| Peak memory | 240476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446600404 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.446600404 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.2740457656 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3428138357 ps |
| CPU time | 470.69 seconds |
| Started | Sep 24 01:05:39 PM UTC 24 |
| Finished | Sep 24 01:13:36 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740457656 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2740457656 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.3784748614 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 575981968 ps |
| CPU time | 41.29 seconds |
| Started | Sep 24 01:07:46 PM UTC 24 |
| Finished | Sep 24 01:08:29 PM UTC 24 |
| Peak memory | 246472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784748614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3784748614 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3904838950 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 22719028 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 01:07:47 PM UTC 24 |
| Finished | Sep 24 01:07:49 PM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904838950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3904838950 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2803294261 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2816363962 ps |
| CPU time | 54.16 seconds |
| Started | Sep 24 01:07:50 PM UTC 24 |
| Finished | Sep 24 01:08:46 PM UTC 24 |
| Peak memory | 232740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803294261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2803294261 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.2630489378 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1251718746 ps |
| CPU time | 15.92 seconds |
| Started | Sep 24 01:06:42 PM UTC 24 |
| Finished | Sep 24 01:06:59 PM UTC 24 |
| Peak memory | 236468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630489378 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2630489378 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_error.667572655 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 17520458167 ps |
| CPU time | 169.22 seconds |
| Started | Sep 24 01:07:21 PM UTC 24 |
| Finished | Sep 24 01:10:13 PM UTC 24 |
| Peak memory | 343124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667572655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.667572655 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.611322172 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 797174894 ps |
| CPU time | 8.47 seconds |
| Started | Sep 24 01:07:36 PM UTC 24 |
| Finished | Sep 24 01:07:46 PM UTC 24 |
| Peak memory | 230656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611322172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.611322172 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.1125054921 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 62851865 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 01:08:30 PM UTC 24 |
| Finished | Sep 24 01:08:34 PM UTC 24 |
| Peak memory | 234480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125054921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1125054921 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.1245251939 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 117000031438 ps |
| CPU time | 2444.46 seconds |
| Started | Sep 24 01:05:09 PM UTC 24 |
| Finished | Sep 24 01:46:23 PM UTC 24 |
| Peak memory | 1332492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245251939 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.1245251939 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.1184644749 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5185284813 ps |
| CPU time | 173.76 seconds |
| Started | Sep 24 01:07:00 PM UTC 24 |
| Finished | Sep 24 01:09:57 PM UTC 24 |
| Peak memory | 331312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184644749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1184644749 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.3503343508 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 15621830921 ps |
| CPU time | 386.98 seconds |
| Started | Sep 24 01:05:28 PM UTC 24 |
| Finished | Sep 24 01:12:00 PM UTC 24 |
| Peak memory | 338920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503343508 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3503343508 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.1175306360 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 15770631306 ps |
| CPU time | 105.82 seconds |
| Started | Sep 24 01:04:53 PM UTC 24 |
| Finished | Sep 24 01:06:42 PM UTC 24 |
| Peak memory | 236584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175306360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1175306360 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.2072607234 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 220708924098 ps |
| CPU time | 1557.02 seconds |
| Started | Sep 24 01:08:34 PM UTC 24 |
| Finished | Sep 24 01:34:51 PM UTC 24 |
| Peak memory | 662916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072607234 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2072607234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all_with_rand_reset.1260115599 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3685563674 ps |
| CPU time | 62.83 seconds |
| Started | Sep 24 01:08:40 PM UTC 24 |
| Finished | Sep 24 01:09:45 PM UTC 24 |
| Peak memory | 246972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1260115599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_r and_reset.1260115599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest |
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