Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17291418	1			T1	69		T2	138		T12	153
all_values[1]	17291418	1			T1	69		T2	138		T12	153
all_values[2]	17291418	1			T1	69		T2	138		T12	153

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

542830

1

T1

69

T12

8

T39

296

auto[1]

51331424

1

T1

138

T2

414

T12

451

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51648945

1

T1

195

T2

405

T12

444

auto[1]

225309

1

T1

12

T2

9

T12

15

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	195712	1			T12	6		T39	139		T38	5
all_values[0]	auto[0]	auto[1]	1412	1			T12	2		T39	6		T38	6
all_values[0]	auto[1]	auto[0]	17020603	1			T1	65		T2	135		T12	142
all_values[0]	auto[1]	auto[1]	73691	1			T1	4		T2	3		T12	3
all_values[1]	auto[0]	auto[0]	172336	1			T39	4		T9	177		T45	18
all_values[1]	auto[0]	auto[1]	1031	1			T39	2		T9	1		T45	11
all_values[1]	auto[1]	auto[0]	17043979	1			T1	65		T2	135		T12	148
all_values[1]	auto[1]	auto[1]	74072	1			T1	4		T2	3		T12	5
all_values[2]	auto[0]	auto[0]	171330	1			T1	65		T39	139		T38	1
all_values[2]	auto[0]	auto[1]	1009	1			T1	4		T39	6		T38	2
all_values[2]	auto[1]	auto[0]	17044985	1			T2	135		T12	148		T38	930
all_values[2]	auto[1]	auto[1]	74094	1			T2	3		T12	5		T38	101