Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 0 3 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 0 18 100.00 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 53674 1 T1 6 T2 2 T10 2
auto[1] 59498 1 T2 4 T39 4 T46 272



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 28333 1 T1 2 T12 2 T38 35
lower_val 27829 1 T1 3 T12 3 T39 1
zero_val 914 1 T1 1 T2 1 T10 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for wait_timer_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 41640 1 T2 2 T10 2 T12 2
lower_val 41724 1 T1 6 T12 4 T39 4
zero_val 29808 1 T2 4 T39 2 T46 152



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for entropy_timer_cross

Bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 6693 1 T12 1 T38 20 T40 7
higher_val higher_val auto[1] 3748 1 T46 15 T5 14 T75 20
higher_val lower_val auto[0] 6589 1 T1 2 T12 1 T38 15
higher_val lower_val auto[1] 3800 1 T46 17 T5 10 T75 20
higher_val zero_val auto[0] 57 1 T46 1 T83 1 T13 1
higher_val zero_val auto[1] 7446 1 T46 41 T5 33 T75 47
lower_val higher_val auto[0] 6426 1 T12 1 T38 18 T40 6
lower_val higher_val auto[1] 3718 1 T46 10 T5 12 T75 27
lower_val lower_val auto[0] 6561 1 T1 3 T12 2 T38 12
lower_val lower_val auto[1] 3762 1 T39 1 T46 19 T5 11
lower_val zero_val auto[0] 68 1 T24 1 T179 1 T63 1
lower_val zero_val auto[1] 7294 1 T46 29 T5 19 T75 44
zero_val higher_val auto[0] 286 1 T2 1 T10 1 T45 1
zero_val higher_val auto[1] 73 1 T14 3 T19 1 T180 2
zero_val lower_val auto[0] 258 1 T1 1 T12 1 T39 1
zero_val lower_val auto[1] 71 1 T68 1 T51 1 T180 1
zero_val zero_val auto[0] 177 1 T46 1 T83 1 T53 1
zero_val zero_val auto[1] 49 1 T14 1 T68 1 T181 2

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