Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17291418	1			T1	69		T2	138		T12	153
all_pins[1]	17291418	1			T1	69		T2	138		T12	153
all_pins[2]	17291418	1			T1	69		T2	138		T12	153

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51404346	1			T1	203		T2	411		T12	456
values[0x1]	469908	1			T1	4		T2	3		T12	3
transitions[0x0=>0x1]	467101	1			T1	4		T2	3		T12	3
transitions[0x1=>0x0]	467124	1			T1	4		T2	3		T12	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17217727	1			T1	65		T2	135		T12	150
all_pins[0]	values[0x1]	73691	1			T1	4		T2	3		T12	3
all_pins[0]	transitions[0x0=>0x1]	73681	1			T1	4		T2	3		T12	3
all_pins[0]	transitions[0x1=>0x0]	6020	1			T39	1		T72	3		T14	11
all_pins[1]	values[0x0]	17285388	1			T1	69		T2	138		T12	153
all_pins[1]	values[0x1]	6030	1			T39	1		T72	3		T14	11
all_pins[1]	transitions[0x0=>0x1]	5562	1			T39	1		T72	3		T14	11
all_pins[1]	transitions[0x1=>0x0]	389719	1			T14	156		T23	14973		T19	1165
all_pins[2]	values[0x0]	16901231	1			T1	69		T2	138		T12	153
all_pins[2]	values[0x1]	390187	1			T14	156		T23	14973		T19	1165
all_pins[2]	transitions[0x0=>0x1]	387858	1			T14	156		T23	14876		T19	1165
all_pins[2]	transitions[0x1=>0x0]	71385	1			T1	4		T2	3		T12	3