Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16794591	1			T1	88		T2	86		T9	3
all_values[1]	16794591	1			T1	88		T2	86		T9	3
all_values[2]	16794591	1			T1	88		T2	86		T9	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

505075

1

T2

7

T38

13

T4

2

auto[1]

49878698

1

T1

264

T2

251

T9

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50165310

1

T1

255

T2

246

T9

9

auto[1]

218463

1

T1

9

T2

12

T8

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	170828	1			T38	1		T4	1		T44	3
all_values[0]	auto[0]	auto[1]	1313	1			T38	2		T44	4		T45	2
all_values[0]	auto[1]	auto[0]	16550942	1			T1	85		T2	82		T9	3
all_values[0]	auto[1]	auto[1]	71508	1			T1	3		T2	4		T8	3
all_values[1]	auto[0]	auto[0]	193140	1			T2	6		T38	1		T70	11
all_values[1]	auto[0]	auto[1]	1026	1			T2	1		T38	2		T70	3
all_values[1]	auto[1]	auto[0]	16528630	1			T1	85		T2	76		T9	3
all_values[1]	auto[1]	auto[1]	71795	1			T1	3		T2	3		T8	3
all_values[2]	auto[0]	auto[0]	137809	1			T38	4		T4	1		T41	20
all_values[2]	auto[0]	auto[1]	959	1			T38	3		T41	3		T47	5
all_values[2]	auto[1]	auto[0]	16583961	1			T1	85		T2	82		T9	3
all_values[2]	auto[1]	auto[1]	71862	1			T1	3		T2	4		T8	3