Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 0 3 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 0 18 100.00 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56628 1 T1 2 T2 2 T9 2
auto[1] 54102 1 T1 4 T2 4 T38 144



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 27658 1 T2 3 T8 4 T38 36
lower_val 27082 1 T1 4 T8 3 T38 39
zero_val 933 1 T1 1 T2 1 T9 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for wait_timer_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 41904 1 T1 4 T8 8 T38 36
lower_val 41474 1 T9 2 T8 6 T38 38
zero_val 27352 1 T1 2 T2 6 T38 72



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for entropy_timer_cross

Bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 7215 1 T8 3 T41 30 T57 19
higher_val higher_val auto[1] 3298 1 T38 6 T4 6 T57 8
higher_val lower_val auto[0] 6972 1 T8 1 T41 31 T57 13
higher_val lower_val auto[1] 3362 1 T38 9 T4 3 T57 9
higher_val zero_val auto[0] 55 1 T38 1 T83 1 T60 4
higher_val zero_val auto[1] 6756 1 T2 3 T38 20 T4 25
lower_val higher_val auto[0] 6896 1 T1 1 T8 1 T4 1
lower_val higher_val auto[1] 3396 1 T1 2 T38 12 T4 25
lower_val lower_val auto[0] 6665 1 T8 2 T41 35 T57 14
lower_val lower_val auto[1] 3359 1 T38 11 T4 11 T57 2
lower_val zero_val auto[0] 64 1 T48 1 T12 1 T13 1
lower_val zero_val auto[1] 6702 1 T1 1 T38 16 T4 37
zero_val higher_val auto[0] 273 1 T1 1 T8 1 T4 1
zero_val higher_val auto[1] 67 1 T12 3 T13 1 T26 1
zero_val lower_val auto[0] 289 1 T9 1 T41 1 T11 1
zero_val lower_val auto[1] 79 1 T5 1 T13 1 T26 1
zero_val zero_val auto[0] 161 1 T2 1 T38 1 T48 1
zero_val zero_val auto[1] 64 1 T5 1 T156 1 T198 1

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