Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16794591	1			T1	88		T2	86		T9	3
all_pins[1]	16794591	1			T1	88		T2	86		T9	3
all_pins[2]	16794591	1			T1	88		T2	86		T9	3

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50011384	1			T1	259		T2	254		T9	9
values[0x1]	372389	1			T1	5		T2	4		T8	4
transitions[0x0=>0x1]	370176	1			T1	5		T2	4		T8	4
transitions[0x1=>0x0]	370200	1			T1	5		T2	4		T8	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16723083	1			T1	85		T2	82		T9	3
all_pins[0]	values[0x1]	71508	1			T1	3		T2	4		T8	3
all_pins[0]	transitions[0x0=>0x1]	71499	1			T1	3		T2	4		T8	3
all_pins[0]	transitions[0x1=>0x0]	6083	1			T1	2		T8	1		T70	1
all_pins[1]	values[0x0]	16788499	1			T1	86		T2	86		T9	3
all_pins[1]	values[0x1]	6092	1			T1	2		T8	1		T70	1
all_pins[1]	transitions[0x0=>0x1]	5704	1			T1	2		T8	1		T70	1
all_pins[1]	transitions[0x1=>0x0]	294401	1			T15	278		T25	21043		T26	131
all_pins[2]	values[0x0]	16499802	1			T1	88		T2	86		T9	3
all_pins[2]	values[0x1]	294789	1			T15	278		T25	21085		T26	131
all_pins[2]	transitions[0x0=>0x1]	292973	1			T15	277		T25	20947		T26	130
all_pins[2]	transitions[0x1=>0x0]	69716	1			T1	3		T2	4		T8	3