Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	628	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5416	1			T45	3		T11	1		T12	2
len_601_800	12064	1			T8	1		T45	5		T11	3
len_401_600	8188	1			T45	1		T11	1		T12	3
len_201_400	4025	1			T12	3		T13	7		T15	5
len_65_200	7698	1			T8	1		T41	64		T57	48
len_min_for_xof_require_squeeze	73	1			T198	9		T23	1		T167	10
len_keccak_block_sizes[72]	84	1			T41	2		T47	2		T198	9
len_keccak_block_sizes[104]	84	1			T41	1		T199	1		T198	9
len_keccak_block_sizes[136]	77	1			T41	1		T91	1		T13	1
len_keccak_block_sizes[144]	39	1			T167	5		T171	1		T200	1
len_keccak_block_sizes[168]	39	1			T15	1		T27	1		T167	5
len_datapath_width	971	1			T38	73		T41	5		T57	7
len_2_63	14684	1			T1	3		T2	3		T8	5
len_1	64	1			T57	1		T47	1		T11	1