Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 0 8 100.00 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6245242 1 T1 24 T2 24 T8 362
auto[1] 6245233 1 T1 24 T2 24 T8 362



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 12425203 1 T1 48 T2 48 T8 720
triple_byte_access 21810 1 T41 44 T57 46 T47 48
halfword_access 21742 1 T8 2 T41 50 T57 32
byte_access 21720 1 T8 2 T41 50 T57 38



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for state_mask_share_cross

Bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 6212606 1 T1 24 T2 24 T8 360
auto[0] triple_byte_access 10905 1 T41 22 T57 23 T47 24
auto[0] halfword_access 10871 1 T8 1 T41 25 T57 16
auto[0] byte_access 10860 1 T8 1 T41 25 T57 19
auto[1] word_access 6212597 1 T1 24 T2 24 T8 360
auto[1] triple_byte_access 10905 1 T41 22 T57 23 T47 24
auto[1] halfword_access 10871 1 T8 1 T41 25 T57 16
auto[1] byte_access 10860 1 T8 1 T41 25 T57 19

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