Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T136 4 T138 4 T177 7
all_values[1] 272 1 T136 4 T138 4 T177 7
all_values[2] 272 1 T136 4 T138 4 T177 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 435 1 T136 11 T138 4 T177 15
auto[1] 381 1 T136 1 T138 8 T177 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 359 1 T136 7 T138 7 T177 7
auto[1] 457 1 T136 5 T138 5 T177 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 478 1 T136 8 T138 8 T177 9
auto[1] 338 1 T136 4 T138 4 T177 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 55 1 T136 2 T138 1 T177 3
all_values[0] auto[0] auto[0] auto[1] 33 1 T136 1 T138 1 T178 1
all_values[0] auto[0] auto[1] auto[0] 41 1 T177 1 T172 1 T179 2
all_values[0] auto[0] auto[1] auto[1] 26 1 T180 1 T181 1 T182 1
all_values[0] auto[1] auto[0] auto[1] 68 1 T136 1 T138 2 T177 2
all_values[0] auto[1] auto[1] auto[1] 49 1 T177 1 T172 1 T178 1
all_values[1] auto[0] auto[0] auto[0] 82 1 T136 2 T177 2 T178 1
all_values[1] auto[0] auto[1] auto[0] 84 1 T136 1 T138 3 T172 2
all_values[1] auto[1] auto[0] auto[1] 63 1 T136 1 T177 5 T172 2
all_values[1] auto[1] auto[1] auto[1] 43 1 T138 1 T178 1 T179 2
all_values[2] auto[0] auto[0] auto[0] 47 1 T136 2 T177 1 T172 1
all_values[2] auto[0] auto[0] auto[1] 34 1 T177 1 T172 1 T179 1
all_values[2] auto[0] auto[1] auto[0] 50 1 T138 3 T172 1 T178 2
all_values[2] auto[0] auto[1] auto[1] 26 1 T177 1 T183 1 T184 2
all_values[2] auto[1] auto[0] auto[1] 53 1 T136 2 T177 1 T172 1
all_values[2] auto[1] auto[1] auto[1] 62 1 T138 1 T177 3 T178 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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