Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99987417	1			T1	966		T2	251		T3	285
all_values[1]	99987417	1			T1	966		T2	251		T3	285
all_values[2]	99987417	1			T1	966		T2	251		T3	285

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

498724

1

T1

8

T3

12

T9

366

auto[1]

299463527

1

T1

2890

T2

753

T3

843

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298449282

1

T1

2508

T2

711

T3

819

auto[1]

1512969

1

T1

390

T2

42

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	157181	1			T3	4		T9	81		T12	1
all_values[0]	auto[0]	auto[1]	2007	1			T3	2		T9	2		T45	2
all_values[0]	auto[1]	auto[0]	99325913	1			T1	836		T2	237		T3	269
all_values[0]	auto[1]	auto[1]	502316	1			T1	130		T2	14		T3	10
all_values[1]	auto[0]	auto[0]	168391	1			T9	280		T11	4		T12	1
all_values[1]	auto[0]	auto[1]	1555	1			T9	3		T45	2		T13	2
all_values[1]	auto[1]	auto[0]	99314703	1			T1	836		T2	237		T3	273
all_values[1]	auto[1]	auto[1]	502768	1			T1	130		T2	14		T3	12
all_values[2]	auto[0]	auto[0]	168132	1			T1	7		T3	4		T10	1
all_values[2]	auto[0]	auto[1]	1458	1			T1	1		T3	2		T27	2
all_values[2]	auto[1]	auto[0]	99314962	1			T1	829		T2	237		T3	269
all_values[2]	auto[1]	auto[1]	502865	1			T1	129		T2	14		T3	10