Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16398452	1			T1	2		T2	88		T11	120
all_values[1]	16398452	1			T1	2		T2	88		T11	120
all_values[2]	16398452	1			T1	2		T2	88		T11	120

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559494

1

T2

32

T4

1

T50

14

auto[1]

48635862

1

T1

6

T2

232

T11

360

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48962085

1

T1

3

T2

252

T11

348

auto[1]

233271

1

T1

3

T2

12

T11

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180160	1			T2	6		T4	1		T12	1435
all_values[0]	auto[0]	auto[1]	1268	1			T2	2		T105	2		T75	2
all_values[0]	auto[1]	auto[0]	16140535	1			T1	1		T2	78		T11	116
all_values[0]	auto[1]	auto[1]	76489	1			T1	1		T2	2		T11	4
all_values[1]	auto[0]	auto[0]	216469	1			T2	6		T50	6		T54	64
all_values[1]	auto[0]	auto[1]	955	1			T2	2		T50	1		T54	4
all_values[1]	auto[1]	auto[0]	16104226	1			T1	1		T2	78		T11	116
all_values[1]	auto[1]	auto[1]	76802	1			T1	1		T2	2		T11	4
all_values[2]	auto[0]	auto[0]	159697	1			T2	13		T50	6		T55	5
all_values[2]	auto[0]	auto[1]	945	1			T2	3		T50	1		T55	1
all_values[2]	auto[1]	auto[0]	16160998	1			T1	1		T2	71		T11	116
all_values[2]	auto[1]	auto[1]	76812	1			T1	1		T2	1		T11	4