Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 0 3 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 0 18 100.00 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 64076 1 T1 2 T2 2 T11 2
auto[1] 54230 1 T1 12 T2 4 T11 4



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 29682 1 T1 2 T2 4 T11 1
lower_val 28977 1 T1 3 T11 2 T9 1
zero_val 941 1 T1 1 T2 1 T11 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for wait_timer_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 45566 1 T1 2 T2 4 T11 2
lower_val 45296 1 T2 2 T9 2 T7 14
zero_val 27444 1 T1 12 T11 4 T7 10



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for entropy_timer_cross

Bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 7927 1 T2 1 T50 23 T51 27
higher_val higher_val auto[1] 3414 1 T1 1 T2 1 T4 8
higher_val lower_val auto[0] 7947 1 T50 20 T51 30 T12 1
higher_val lower_val auto[1] 3413 1 T2 2 T4 6 T16 4
higher_val zero_val auto[0] 52 1 T47 1 T177 1 T178 1
higher_val zero_val auto[1] 6929 1 T1 1 T11 1 T4 20
lower_val higher_val auto[0] 7876 1 T11 1 T50 25 T51 20
lower_val higher_val auto[1] 3307 1 T7 4 T4 3 T16 2
lower_val lower_val auto[0] 7854 1 T9 1 T50 19 T54 3
lower_val lower_val auto[1] 3338 1 T7 4 T4 2 T16 3
lower_val zero_val auto[0] 68 1 T1 1 T4 1 T16 1
lower_val zero_val auto[1] 6534 1 T1 2 T11 1 T7 4
zero_val higher_val auto[0] 293 1 T2 1 T11 1 T50 1
zero_val higher_val auto[1] 62 1 T12 1 T79 1 T179 1
zero_val lower_val auto[0] 291 1 T9 1 T7 1 T54 1
zero_val lower_val auto[1] 71 1 T12 1 T79 2 T58 1
zero_val zero_val auto[0] 176 1 T1 1 T4 1 T16 1
zero_val zero_val auto[1] 48 1 T180 2 T179 1 T94 1

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