Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343490 |
1 |
|
|
T1 |
190 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
342196 |
1 |
|
|
T2 |
16 |
|
T3 |
16 |
|
T21 |
164 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171867 |
1 |
|
|
T1 |
52 |
|
T2 |
6 |
|
T3 |
11 |
lower_val |
170033 |
1 |
|
|
T1 |
42 |
|
T2 |
6 |
|
T3 |
2 |
zero_val |
1864 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
256350 |
1 |
|
|
T1 |
102 |
|
T2 |
2 |
|
T3 |
6 |
lower_val |
257626 |
1 |
|
|
T1 |
88 |
|
T2 |
4 |
|
T3 |
2 |
zero_val |
171710 |
1 |
|
|
T2 |
12 |
|
T3 |
10 |
|
T21 |
74 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42880 |
1 |
|
|
T1 |
30 |
|
T3 |
1 |
|
T9 |
9 |
higher_val |
higher_val |
auto[1] |
21511 |
1 |
|
|
T3 |
2 |
|
T21 |
10 |
|
T12 |
4 |
higher_val |
lower_val |
auto[0] |
43086 |
1 |
|
|
T1 |
22 |
|
T9 |
11 |
|
T10 |
4 |
higher_val |
lower_val |
auto[1] |
21341 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T21 |
10 |
higher_val |
zero_val |
auto[0] |
72 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T23 |
1 |
higher_val |
zero_val |
auto[1] |
42977 |
1 |
|
|
T2 |
4 |
|
T3 |
6 |
|
T21 |
12 |
lower_val |
higher_val |
auto[0] |
42213 |
1 |
|
|
T1 |
22 |
|
T9 |
6 |
|
T10 |
3 |
lower_val |
higher_val |
auto[1] |
21328 |
1 |
|
|
T2 |
2 |
|
T21 |
10 |
|
T12 |
6 |
lower_val |
lower_val |
auto[0] |
43130 |
1 |
|
|
T1 |
20 |
|
T9 |
2 |
|
T10 |
1 |
lower_val |
lower_val |
auto[1] |
20980 |
1 |
|
|
T2 |
2 |
|
T21 |
14 |
|
T12 |
3 |
lower_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T12 |
1 |
|
T45 |
1 |
|
T85 |
1 |
lower_val |
zero_val |
auto[1] |
42302 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T21 |
20 |
zero_val |
higher_val |
auto[0] |
583 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
1 |
zero_val |
higher_val |
auto[1] |
122 |
1 |
|
|
T58 |
1 |
|
T174 |
1 |
|
T49 |
1 |
zero_val |
lower_val |
auto[0] |
560 |
1 |
|
|
T10 |
1 |
|
T17 |
1 |
|
T5 |
1 |
zero_val |
lower_val |
auto[1] |
145 |
1 |
|
|
T43 |
1 |
|
T186 |
1 |
|
T187 |
1 |
zero_val |
zero_val |
auto[0] |
250 |
1 |
|
|
T2 |
1 |
|
T21 |
1 |
|
T12 |
1 |
zero_val |
zero_val |
auto[1] |
204 |
1 |
|
|
T18 |
2 |
|
T70 |
2 |
|
T58 |
1 |