Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16398452	1			T1	2		T2	88		T11	120
all_pins[1]	16398452	1			T1	2		T2	88		T11	120
all_pins[2]	16398452	1			T1	2		T2	88		T11	120

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48845966	1			T1	4		T2	262		T11	356
values[0x1]	349390	1			T1	2		T2	2		T11	4
transitions[0x0=>0x1]	347406	1			T1	1		T2	2		T11	4
transitions[0x1=>0x0]	347482	1			T1	2		T2	2		T11	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16321963	1			T1	1		T2	86		T11	116
all_pins[0]	values[0x1]	76489	1			T1	1		T2	2		T11	4
all_pins[0]	transitions[0x0=>0x1]	76479	1			T1	1		T2	2		T11	4
all_pins[0]	transitions[0x1=>0x0]	5785	1			T55	1		T13	20		T15	15
all_pins[1]	values[0x0]	16392657	1			T1	2		T2	88		T11	120
all_pins[1]	values[0x1]	5795	1			T55	1		T13	20		T15	15
all_pins[1]	transitions[0x0=>0x1]	5497	1			T55	1		T15	15		T58	2
all_pins[1]	transitions[0x1=>0x0]	266808	1			T1	1		T7	1		T17	1
all_pins[2]	values[0x0]	16131346	1			T1	1		T2	88		T11	120
all_pins[2]	values[0x1]	267106	1			T1	1		T7	1		T17	1
all_pins[2]	transitions[0x0=>0x1]	265430	1			T13	8500		T69	876		T35	8727
all_pins[2]	transitions[0x1=>0x0]	74889	1			T1	1		T2	2		T11	4