Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99987417	1			T1	966		T2	251		T3	285
all_pins[1]	99987417	1			T1	966		T2	251		T3	285
all_pins[2]	99987417	1			T1	966		T2	251		T3	285

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299193076	1			T1	2768		T2	739		T3	845
values[0x1]	769175	1			T1	130		T2	14		T3	10
transitions[0x0=>0x1]	767426	1			T1	130		T2	14		T3	10
transitions[0x1=>0x0]	767448	1			T1	130		T2	14		T3	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99485101	1			T1	836		T2	237		T3	275
all_pins[0]	values[0x1]	502316	1			T1	130		T2	14		T3	10
all_pins[0]	transitions[0x0=>0x1]	502301	1			T1	130		T2	14		T3	10
all_pins[0]	transitions[0x1=>0x0]	5929	1			T12	10		T69	2		T14	26
all_pins[1]	values[0x0]	99981473	1			T1	966		T2	251		T3	285
all_pins[1]	values[0x1]	5944	1			T12	10		T69	2		T14	26
all_pins[1]	transitions[0x0=>0x1]	5735	1			T69	2		T14	26		T24	96
all_pins[1]	transitions[0x1=>0x0]	260706	1			T10	367		T12	4432		T18	517
all_pins[2]	values[0x0]	99726502	1			T1	966		T2	251		T3	285
all_pins[2]	values[0x1]	260915	1			T10	367		T12	4442		T18	517
all_pins[2]	transitions[0x0=>0x1]	259390	1			T10	363		T12	4416		T18	517
all_pins[2]	transitions[0x1=>0x0]	500813	1			T1	130		T2	14		T3	10