Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	644	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5136	1			T9	2		T21	17		T12	3
len_601_800	12152	1			T9	6		T10	1		T21	35
len_401_600	8031	1			T9	4		T10	2		T21	16
len_201_400	16222	1			T10	1		T21	6		T12	3
len_65_200	73294	1			T1	50		T21	5		T12	1
len_min_for_xof_require_squeeze	1000	1			T46	1		T193	1		T26	1
len_keccak_block_sizes[72]	736	1			T45	1		T194	2		T195	1
len_keccak_block_sizes[104]	749	1			T1	3		T46	1		T43	2
len_keccak_block_sizes[136]	744	1			T1	4		T193	1		T133	1
len_keccak_block_sizes[144]	288	1			T26	1		T151	1		T194	1
len_keccak_block_sizes[168]	285	1			T49	1		T190	1		T194	1
len_datapath_width	13954	1			T1	2		T2	3		T3	3
len_2_63	211513	1			T1	43		T2	6		T3	6
len_1	45	1			T193	1		T144	1		T133	1