Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	630	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5501	1			T13	7		T14	7		T69	9
len_601_800	12202	1			T13	23		T14	16		T69	10
len_401_600	8249	1			T12	1		T13	10		T14	12
len_201_400	4493	1			T13	10		T14	9		T69	8
len_65_200	9070	1			T16	12		T50	48		T71	64
len_min_for_xof_require_squeeze	91	1			T16	1		T71	1		T177	9
len_keccak_block_sizes[72]	95	1			T50	1		T177	9		T185	9
len_keccak_block_sizes[104]	97	1			T139	2		T162	1		T177	9
len_keccak_block_sizes[136]	87	1			T71	2		T177	9		T185	9
len_keccak_block_sizes[144]	44	1			T50	1		T186	1		T187	5
len_keccak_block_sizes[168]	44	1			T50	2		T71	1		T186	1
len_datapath_width	1109	1			T11	3		T16	1		T50	1
len_2_63	15919	1			T1	6		T2	3		T7	8
len_1	63	1			T16	1		T186	2		T188	2