Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::state_read_mask_cg

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
share	2	0	2	100.00	100	1	1	2
state_read_mask	4	0	4	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_mask_share_cross	8	0	8	100.00	100	1	1	0

Summary for Variable share

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for share

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6428455

1

T1

286

T2

24

T11

48

auto[1]

6428416

1

T1

286

T2

24

T11

48

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Summary for Variable state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for state_read_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	12787384	1			T1	572		T2	48		T11	96
triple_byte_access	22991	1			T16	12		T50	28		T71	58
halfword_access	23306	1			T16	8		T50	50		T71	56
byte_access	23190	1			T16	16		T50	42		T12	2

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Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for state_mask_share_cross

Bins

share	state_read_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	6393711	1			T1	286		T2	24		T11	48
auto[0]	triple_byte_access	11496	1			T16	6		T50	14		T71	29
auto[0]	halfword_access	11653	1			T16	4		T50	25		T71	28
auto[0]	byte_access	11595	1			T16	8		T50	21		T12	1
auto[1]	word_access	6393673	1			T1	286		T2	24		T11	48
auto[1]	triple_byte_access	11495	1			T16	6		T50	14		T71	29
auto[1]	halfword_access	11653	1			T16	4		T50	25		T71	28
auto[1]	byte_access	11595	1			T16	8		T50	21		T12	1