KMAC/UNMASKED Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.147m	12.523ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.080s	57.285us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	107.694us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.460s	1.782ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.620s	440.049us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.460s	100.809us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	107.694us	20	20	100.00
		kmac_csr_aliasing	9.620s	440.049us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	19.102us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.390s	64.811us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.968m	652.480ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.929m	157.832ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.481m	407.824ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.417m	486.947ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.202m	282.095ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.399m	598.452ms	50	50	100.00
		kmac_test_vectors_shake_128	1.687h	3.205s	50	50	100.00
		kmac_test_vectors_shake_256	1.321h	727.030ms	50	50	100.00
		kmac_test_vectors_kmac	5.700s	1.030ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.210s	185.419us	50	50	100.00
V2	sideload	kmac_sideload	7.340m	15.173ms	50	50	100.00
V2	app	kmac_app	5.207m	64.136ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.604m	13.078ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	4.964m	23.456ms	48	50	96.00
V2	error	kmac_error	6.572m	21.313ms	50	50	100.00
V2	key_error	kmac_key_error	7.460s	5.743ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.380s	10.946ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	51.380s	13.527ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.061m	32.707ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.490s	1.083ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.695m	82.821ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	39.950us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	71.167us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.640s	151.569us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.640s	151.569us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.080s	57.285us	5	5	100.00
		kmac_csr_rw	1.230s	107.694us	20	20	100.00
		kmac_csr_aliasing	9.620s	440.049us	5	5	100.00
		kmac_same_csr_outstanding	3.040s	521.150us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.080s	57.285us	5	5	100.00
		kmac_csr_rw	1.230s	107.694us	20	20	100.00
		kmac_csr_aliasing	9.620s	440.049us	5	5	100.00
		kmac_same_csr_outstanding	3.040s	521.150us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.440s	233.601us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.440s	233.601us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.440s	233.601us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.440s	233.601us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.350s	1.378ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.210m	23.645ms	5	5	100.00
		kmac_tl_intg_err	5.520s	375.957us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.520s	375.957us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.490s	1.083ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.147m	12.523ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.340m	15.173ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.440s	233.601us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.210m	23.645ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.210m	23.645ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.210m	23.645ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.147m	12.523ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.490s	1.083ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.210m	23.645ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.273m	33.187ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.147m	12.523ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.035m	199.649ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1275	1290	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	96.65	92.55	100.00	89.77	94.67	98.82	97.16

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:

Test kmac_stress_all_with_rand_reset has 10 failures.

8.kmac_stress_all_with_rand_reset.3372820314
Line 509, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40239495784 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 40239495784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_stress_all_with_rand_reset.3164327191
Line 1309, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43873387551 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 43873387551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 2 failures.

11.kmac_entropy_refresh.2980061776
Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 10450239106 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (81 [0x51] vs 106 [0x6a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10450239106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.kmac_entropy_refresh.2472425133
Line 327, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 47359553128 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (165 [0xa5] vs 176 [0xb0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 47359553128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 0.kmac_app_with_partial_data.632335235
    Line 338, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 15.kmac_key_error.597812819
    Line 220, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 309538518 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 309538518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 40.kmac_stress_all_with_rand_reset.3226487653
    Line 592, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 108471445102 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (31 [0x1f] vs 255 [0xff]) Mismatch between exp_digest[48] and act_digest[48]
  UVM_INFO @ 108471445102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```