KMAC/UNMASKED Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.113m	16.816ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	44.360us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	110.729us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.350s	4.338ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.530s	1.863ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.060s	148.773us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	110.729us	20	20	100.00
		kmac_csr_aliasing	10.530s	1.863ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	46.155us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.410s	38.904us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	42.285m	238.573ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.704m	34.459ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.370m	1.257s	50	50	100.00
		kmac_test_vectors_sha3_256	32.556m	95.430ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.597m	995.654ms	50	50	100.00
		kmac_test_vectors_sha3_512	21.270m	976.536ms	50	50	100.00
		kmac_test_vectors_shake_128	1.604h	2.148s	50	50	100.00
		kmac_test_vectors_shake_256	1.464h	3.568s	50	50	100.00
		kmac_test_vectors_kmac	5.180s	1.248ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.360s	3.271ms	50	50	100.00
V2	sideload	kmac_sideload	6.735m	41.583ms	50	50	100.00
V2	app	kmac_app	6.245m	56.924ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.179m	6.773ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.044m	61.787ms	50	50	100.00
V2	error	kmac_error	6.256m	14.827ms	50	50	100.00
V2	key_error	kmac_key_error	8.490s	9.454ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.000s	1.959ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.320s	1.802ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.189m	51.401ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.570s	10.672ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.159m	190.576ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.840s	19.560us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	186.465us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.010s	162.477us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.010s	162.477us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	44.360us	5	5	100.00
		kmac_csr_rw	1.220s	110.729us	20	20	100.00
		kmac_csr_aliasing	10.530s	1.863ms	5	5	100.00
		kmac_same_csr_outstanding	2.630s	126.470us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	44.360us	5	5	100.00
		kmac_csr_rw	1.220s	110.729us	20	20	100.00
		kmac_csr_aliasing	10.530s	1.863ms	5	5	100.00
		kmac_same_csr_outstanding	2.630s	126.470us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.840s	69.902us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.840s	69.902us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.840s	69.902us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.840s	69.902us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.430s	896.021us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.105m	11.522ms	5	5	100.00
		kmac_tl_intg_err	5.450s	544.964us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.450s	544.964us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.570s	10.672ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.113m	16.816ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.735m	41.583ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.840s	69.902us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.105m	11.522ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.105m	11.522ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.105m	11.522ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.113m	16.816ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.570s	10.672ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.105m	11.522ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.071m	23.605ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.113m	16.816ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.471m	151.758ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			1274	1290	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	96.65	92.52	100.00	89.77	94.67	98.82	97.02

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:

Test kmac_stress_all_with_rand_reset has 7 failures.

1.kmac_stress_all_with_rand_reset.837403926
Line 236, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  19031296 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @  19031296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_stress_all_with_rand_reset.631564711
Line 536, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 95631901538 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 95631901538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

14.kmac_stress_all_with_rand_reset.1959378226
Line 1591, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 57020175854 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (11 [0xb] vs 24 [0x18]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 57020175854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 4 failures.

26.kmac_stress_all.32796286
Line 360, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest/run.log

  UVM_FATAL @ 35136531858 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (8 [0x8] vs 28 [0x1c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 35136531858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.kmac_stress_all.155103370
Line 289, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest/run.log

  UVM_FATAL @ 3533846673 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (156 [0x9c] vs 60 [0x3c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3533846673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_app has 2 failures.

29.kmac_app.939079527
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_app/latest/run.log

  UVM_FATAL @ 5053764825 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (95 [0x5f] vs 63 [0x3f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5053764825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_app.3580494224
Line 337, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_app/latest/run.log

  UVM_FATAL @ 22582172344 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (46 [0x2e] vs 144 [0x90]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 22582172344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test kmac_burst_write has 2 failures.

3.kmac_burst_write.3864464395
Line 281, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.kmac_burst_write.875291444
Line 320, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---