94eb0df12
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.095m | 25.261ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.080s | 29.183us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.250s | 105.334us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 21.640s | 1.601ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 10.700s | 560.774us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.150s | 32.301us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.250s | 105.334us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 10.700s | 560.774us | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.760s | 10.963us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.480s | 36.672us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 46.922m | 456.351ms | 50 | 50 | 100.00 |
V2 | burst_write | kmac_burst_write | 14.902m | 146.119ms | 48 | 50 | 96.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 37.088m | 1.080s | 50 | 50 | 100.00 |
kmac_test_vectors_sha3_256 | 34.992m | 612.977ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_384 | 24.637m | 337.847ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 16.822m | 50.031ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.942h | 5.000s | 49 | 50 | 98.00 | ||
kmac_test_vectors_shake_256 | 1.240h | 429.369ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac | 4.940s | 478.744us | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac_xof | 5.310s | 1.984ms | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 7.068m | 44.693ms | 50 | 50 | 100.00 |
V2 | app | kmac_app | 4.784m | 58.674ms | 50 | 50 | 100.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 5.458m | 79.323ms | 10 | 10 | 100.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 5.762m | 76.357ms | 47 | 50 | 94.00 |
V2 | error | kmac_error | 6.796m | 20.007ms | 50 | 50 | 100.00 |
V2 | key_error | kmac_key_error | 8.180s | 9.338ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 41.200s | 4.428ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 45.270s | 22.355ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.340m | 45.338ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 37.150s | 953.404us | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 30.236m | 350.846ms | 50 | 50 | 100.00 |
V2 | intr_test | kmac_intr_test | 0.860s | 50.349us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.830s | 16.967us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.530s | 138.210us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.530s | 138.210us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.080s | 29.183us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.250s | 105.334us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.700s | 560.774us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.640s | 94.990us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.080s | 29.183us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.250s | 105.334us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.700s | 560.774us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.640s | 94.990us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1044 | 1050 | 99.43 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.710s | 67.490us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.710s | 67.490us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.710s | 67.490us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.710s | 67.490us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 5.440s | 1.011ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | kmac_sec_cm | 1.273m | 22.880ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 6.000s | 4.021ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 6.000s | 4.021ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 37.150s | 953.404us | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.095m | 25.261ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 7.068m | 44.693ms | 50 | 50 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.710s | 67.490us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.273m | 22.880ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.273m | 22.880ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.273m | 22.880ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.095m | 25.261ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 37.150s | 953.404us | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.273m | 22.880ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 4.836m | 36.545ms | 9 | 10 | 90.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.095m | 25.261ms | 50 | 50 | 100.00 |
V2S | TOTAL | 74 | 75 | 98.67 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 59.615m | 549.413ms | 42 | 50 | 84.00 |
V3 | TOTAL | 42 | 50 | 84.00 | |||
TOTAL | 1275 | 1290 | 98.84 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 22 | 88.00 |
V2S | 5 | 5 | 4 | 80.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
95.64 | 96.65 | 92.52 | 100.00 | 89.77 | 94.67 | 98.82 | 97.02 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 8 failures:
3.kmac_stress_all_with_rand_reset.2975739826
Line 341, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18264628273 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 18264628273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.kmac_stress_all_with_rand_reset.720685306
Line 694, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 96833473202 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
UVM_INFO @ 96833473202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 5 failures:
Test kmac_entropy_refresh has 2 failures.
18.kmac_entropy_refresh.3211350932
Line 375, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.kmac_entropy_refresh.3168012553
Line 350, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_128 has 1 failures.
23.kmac_test_vectors_shake_128.3427976114
Line 2039, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_shake_128/latest/run.log
UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 2 failures.
28.kmac_burst_write.3331910373
Line 342, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.kmac_burst_write.1822582341
Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 2 failures:
Test kmac_mubi has 1 failures.
7.kmac_mubi.3065817719
Line 319, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_mubi/latest/run.log
UVM_FATAL @ 6379353896 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (110 [0x6e] vs 49 [0x31]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 6379353896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
38.kmac_entropy_refresh.2309188941
Line 256, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 1257835940 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (217 [0xd9] vs 205 [0xcd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1257835940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---