KMAC/UNMASKED Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	59.660s	3.779ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	104.842us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	34.213us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.960s	1.261ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.890s	569.393us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.420s	41.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	34.213us	20	20	100.00
		kmac_csr_aliasing	10.890s	569.393us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	12.031us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.410s	39.030us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.961m	142.152ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.147m	35.441ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.678m	508.449ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.053m	1.317s	50	50	100.00
		kmac_test_vectors_sha3_384	25.953m	941.618ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.238m	645.518ms	50	50	100.00
		kmac_test_vectors_shake_128	1.418h	1.175s	50	50	100.00
		kmac_test_vectors_shake_256	1.299h	2.113s	50	50	100.00
		kmac_test_vectors_kmac	5.580s	995.662us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.050s	254.145us	50	50	100.00
V2	sideload	kmac_sideload	7.378m	89.042ms	50	50	100.00
V2	app	kmac_app	4.579m	5.113ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.320m	38.586ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.961m	106.160ms	49	50	98.00
V2	error	kmac_error	6.034m	36.203ms	50	50	100.00
V2	key_error	kmac_key_error	6.900s	4.983ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.200s	35.245ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.320s	7.632ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	46.870s	14.954ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.250s	2.360ms	50	50	100.00
V2	stress_all	kmac_stress_all	28.860m	337.752ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.820s	12.555us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	56.848us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.570s	152.348us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.570s	152.348us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	104.842us	5	5	100.00
		kmac_csr_rw	1.220s	34.213us	20	20	100.00
		kmac_csr_aliasing	10.890s	569.393us	5	5	100.00
		kmac_same_csr_outstanding	2.990s	1.844ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	104.842us	5	5	100.00
		kmac_csr_rw	1.220s	34.213us	20	20	100.00
		kmac_csr_aliasing	10.890s	569.393us	5	5	100.00
		kmac_same_csr_outstanding	2.990s	1.844ms	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.150s	234.047us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.150s	234.047us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.150s	234.047us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.150s	234.047us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.350s	1.004ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.016m	19.540ms	5	5	100.00
		kmac_tl_intg_err	5.160s	351.999us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.160s	351.999us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.250s	2.360ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	59.660s	3.779ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.378m	89.042ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.150s	234.047us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.016m	19.540ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.016m	19.540ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.016m	19.540ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	59.660s	3.779ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.250s	2.360ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.016m	19.540ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.508m	13.423ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	59.660s	3.779ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.263m	1.805s	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1273	1290	98.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.46	96.65	92.55	100.00	88.64	94.67	98.82	96.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 12 failures:

Test kmac_stress_all_with_rand_reset has 12 failures.

1.kmac_stress_all_with_rand_reset.4137649163
Line 753, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25249920478 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 25249920478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_stress_all_with_rand_reset.2771421142
Line 878, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 248673818139 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 248673818139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 2 failures.

6.kmac_app.143155302
Line 267, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app/latest/run.log

  UVM_FATAL @ 13983666566 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (100 [0x64] vs 184 [0xb8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13983666566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_app.2721993150
Line 219, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_app/latest/run.log

  UVM_FATAL @ 509572192 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 116 [0x74]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 509572192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

9.kmac_app_with_partial_data.506673010
Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 4705243914 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (22 [0x16] vs 196 [0xc4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4705243914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

33.kmac_entropy_refresh.1941091048
Line 230, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1052591593 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (18 [0x12] vs 248 [0xf8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1052591593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 1.kmac_burst_write.3882470522
    Line 401, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```