KMAC/UNMASKED Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.141m	16.962ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	57.024us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	171.217us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.510s	1.639ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.740s	615.807us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.440s	112.712us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	171.217us	20	20	100.00
		kmac_csr_aliasing	8.740s	615.807us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.710s	13.969us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	37.396us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.644m	145.659ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.982m	131.682ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.684m	1.706s	50	50	100.00
		kmac_test_vectors_sha3_256	33.014m	368.145ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.646m	632.915ms	50	50	100.00
		kmac_test_vectors_sha3_512	20.740m	985.516ms	50	50	100.00
		kmac_test_vectors_shake_128	1.647h	2.854s	50	50	100.00
		kmac_test_vectors_shake_256	1.461h	3.105s	50	50	100.00
		kmac_test_vectors_kmac	5.610s	2.918ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.290s	1.556ms	50	50	100.00
V2	sideload	kmac_sideload	7.329m	31.466ms	50	50	100.00
V2	app	kmac_app	4.812m	18.995ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.916m	15.646ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.724m	14.302ms	48	50	96.00
V2	error	kmac_error	6.219m	13.980ms	50	50	100.00
V2	key_error	kmac_key_error	6.700s	6.935ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.890s	10.249ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.160s	1.419ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.125m	140.671ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	33.230s	3.720ms	50	50	100.00
V2	stress_all	kmac_stress_all	33.163m	94.116ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.790s	15.501us	50	50	100.00
V2	alert_test	kmac_alert_test	0.830s	19.415us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.390s	146.311us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.390s	146.311us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	57.024us	5	5	100.00
		kmac_csr_rw	1.180s	171.217us	20	20	100.00
		kmac_csr_aliasing	8.740s	615.807us	5	5	100.00
		kmac_same_csr_outstanding	2.490s	117.999us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	57.024us	5	5	100.00
		kmac_csr_rw	1.180s	171.217us	20	20	100.00
		kmac_csr_aliasing	8.740s	615.807us	5	5	100.00
		kmac_same_csr_outstanding	2.490s	117.999us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.910s	644.386us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.910s	644.386us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.910s	644.386us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.910s	644.386us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.950s	3.111ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	55.470s	6.654ms	5	5	100.00
		kmac_tl_intg_err	5.380s	957.905us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.380s	957.905us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	33.230s	3.720ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.141m	16.962ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.329m	31.466ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.910s	644.386us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.470s	6.654ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.470s	6.654ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.470s	6.654ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.141m	16.962ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	33.230s	3.720ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.470s	6.654ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.349m	13.242ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.141m	16.962ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	56.159m	145.639ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1270	1290	98.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	96.65	92.55	100.00	89.77	94.67	98.82	97.16

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 11 failures:

Test kmac_stress_all_with_rand_reset has 11 failures.

3.kmac_stress_all_with_rand_reset.3564690365
Line 292, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11690998846 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 11690998846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_stress_all_with_rand_reset.3990567499
Line 369, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7275973353 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7275973353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:

Test kmac_app has 2 failures.

7.kmac_app.1270794549
Line 312, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 2636424723 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (138 [0x8a] vs 205 [0xcd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2636424723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.kmac_app.158998955
Line 346, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_app/latest/run.log

  UVM_FATAL @ 9956250795 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (104 [0x68] vs 237 [0xed]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9956250795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

16.kmac_entropy_refresh.3761544645
Line 295, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7426398832 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (139 [0x8b] vs 39 [0x27]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7426398832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.kmac_entropy_refresh.2524428746
Line 224, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 553473864 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (2 [0x2] vs 145 [0x91]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 553473864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

18.kmac_stress_all.2106426143
Line 489, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_FATAL @ 18008483532 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (181 [0xb5] vs 136 [0x88]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18008483532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.kmac_stress_all.3766909524
Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6020177863 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 179 [0xb3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6020177863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

45.kmac_stress_all_with_rand_reset.3156545698
Line 233, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 767742716 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (174 [0xae] vs 232 [0xe8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 767742716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 33.kmac_burst_write.2990864724
    Line 297, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 34.kmac_stress_all_with_rand_reset.3600489346
    Line 427, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 138911305655 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (205 [0xcd] vs 60 [0x3c]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 138911305655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```