KMAC/UNMASKED Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.058m	17.119ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	135.550us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	110.069us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.690s	6.193ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.350s	558.726us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.980s	67.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	110.069us	20	20	100.00
		kmac_csr_aliasing	10.350s	558.726us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	39.128us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	41.722us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.849m	1.358s	50	50	100.00
V2	burst_write	kmac_burst_write	13.012m	133.125ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.569m	362.767ms	50	50	100.00
		kmac_test_vectors_sha3_256	31.642m	301.668ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.125m	281.251ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.265m	665.351ms	50	50	100.00
		kmac_test_vectors_shake_128	1.548h	2.343s	50	50	100.00
		kmac_test_vectors_shake_256	1.371h	2.685s	50	50	100.00
		kmac_test_vectors_kmac	6.620s	4.880ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.400s	1.176ms	50	50	100.00
V2	sideload	kmac_sideload	7.697m	22.998ms	50	50	100.00
V2	app	kmac_app	5.642m	70.932ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.552m	8.722ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.378m	36.269ms	50	50	100.00
V2	error	kmac_error	7.479m	84.153ms	50	50	100.00
V2	key_error	kmac_key_error	7.590s	4.892ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.770s	2.073ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.400s	1.624ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	54.340s	12.106ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.170s	2.080ms	50	50	100.00
V2	stress_all	kmac_stress_all	43.748m	761.123ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	44.301us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	272.188us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.670s	482.391us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.670s	482.391us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	135.550us	5	5	100.00
		kmac_csr_rw	1.280s	110.069us	20	20	100.00
		kmac_csr_aliasing	10.350s	558.726us	5	5	100.00
		kmac_same_csr_outstanding	2.820s	405.247us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	135.550us	5	5	100.00
		kmac_csr_rw	1.280s	110.069us	20	20	100.00
		kmac_csr_aliasing	10.350s	558.726us	5	5	100.00
		kmac_same_csr_outstanding	2.820s	405.247us	20	20	100.00
V2		TOTAL			1050	1050	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.380s	120.080us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.380s	120.080us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.380s	120.080us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.380s	120.080us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.200s	272.840us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.237m	94.395ms	5	5	100.00
		kmac_tl_intg_err	5.030s	771.795us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.030s	771.795us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.170s	2.080ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.058m	17.119ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.697m	22.998ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.380s	120.080us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.237m	94.395ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.237m	94.395ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.237m	94.395ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.058m	17.119ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.170s	2.080ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.237m	94.395ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.533m	27.728ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.058m	17.119ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	53.047m	580.519ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1276	1290	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	25	100.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.80	96.65	92.52	100.00	90.91	94.67	98.82	97.02

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code

has 13 failures:

Test kmac_stress_all_with_rand_reset has 13 failures.

2.kmac_stress_all_with_rand_reset.3451229000
Line 439, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7643760912 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7643760912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_stress_all_with_rand_reset.3994715373
Line 659, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 81499712184 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 81499712184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_mubi has 1 failures.
  - 5.kmac_mubi.950017731
    Line 317, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 3020217069 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (230 [0xe6] vs 153 [0x99]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3020217069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```