Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	95083700	1			T12	5		T15	5		T17	5
all_values[1]	95083700	1			T12	5		T15	5		T17	5
all_values[2]	95083700	1			T12	5		T15	5		T17	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

214480

1

T12

12

T15

12

T17

12

auto[1]

285036620

1

T12

3

T15

3

T17

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

283764570

1

T12

9

T15

9

T17

9

auto[1]

1486530

1

T12

6

T15

6

T17

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83660	1			T12	3		T15	3		T17	3
all_values[0]	auto[0]	auto[1]	1660	1			T20	10		T33	4		T35	4
all_values[0]	auto[1]	auto[0]	94504530	1			T20	52199		T21	259		T22	259
all_values[0]	auto[1]	auto[1]	493850	1			T12	2		T15	2		T17	2
all_values[1]	auto[0]	auto[0]	115680	1			T12	3		T15	3		T17	3
all_values[1]	auto[0]	auto[1]	1250	1			T12	1		T15	1		T17	1
all_values[1]	auto[1]	auto[0]	94472510	1			T20	52824		T21	259		T22	259
all_values[1]	auto[1]	auto[1]	494260	1			T12	1		T15	1		T17	1
all_values[2]	auto[0]	auto[0]	10810	1			T12	3		T15	3		T17	3
all_values[2]	auto[0]	auto[1]	1420	1			T12	2		T15	2		T17	2
all_values[2]	auto[1]	auto[0]	94577380	1			T20	53647		T21	259		T22	259
all_values[2]	auto[1]	auto[1]	494090	1			T20	423		T21	13		T22	13