Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
19060 |
1 |
|
|
T20 |
348 |
|
T21 |
2 |
|
T22 |
2 |
auto[1] |
652540 |
1 |
|
|
T20 |
290 |
|
T21 |
16 |
|
T22 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
170870 |
1 |
|
|
T20 |
176 |
|
T21 |
5 |
|
T22 |
5 |
lower_val |
163640 |
1 |
|
|
T20 |
154 |
|
T21 |
8 |
|
T22 |
8 |
zero_val |
2450 |
1 |
|
|
T20 |
10 |
|
T21 |
1 |
|
T22 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
330860 |
1 |
|
|
T20 |
328 |
|
T21 |
8 |
|
T22 |
8 |
lower_val |
340740 |
1 |
|
|
T20 |
310 |
|
T21 |
10 |
|
T22 |
10 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
2360 |
1 |
|
|
T20 |
46 |
|
T39 |
46 |
|
T40 |
46 |
higher_val |
higher_val |
auto[1] |
81490 |
1 |
|
|
T20 |
45 |
|
T21 |
1 |
|
T22 |
1 |
higher_val |
lower_val |
auto[0] |
2250 |
1 |
|
|
T20 |
45 |
|
T39 |
45 |
|
T40 |
45 |
higher_val |
lower_val |
auto[1] |
84770 |
1 |
|
|
T20 |
40 |
|
T21 |
4 |
|
T22 |
4 |
lower_val |
higher_val |
auto[0] |
2350 |
1 |
|
|
T20 |
46 |
|
T39 |
46 |
|
T40 |
46 |
lower_val |
higher_val |
auto[1] |
76150 |
1 |
|
|
T20 |
27 |
|
T21 |
5 |
|
T22 |
5 |
lower_val |
lower_val |
auto[0] |
2650 |
1 |
|
|
T20 |
51 |
|
T31 |
1 |
|
T39 |
51 |
lower_val |
lower_val |
auto[1] |
82490 |
1 |
|
|
T20 |
30 |
|
T21 |
3 |
|
T22 |
3 |
zero_val |
higher_val |
auto[0] |
470 |
1 |
|
|
T20 |
4 |
|
T29 |
1 |
|
T23 |
1 |
zero_val |
higher_val |
auto[1] |
710 |
1 |
|
|
T20 |
2 |
|
T31 |
5 |
|
T33 |
2 |
zero_val |
lower_val |
auto[0] |
660 |
1 |
|
|
T20 |
1 |
|
T21 |
1 |
|
T22 |
1 |
zero_val |
lower_val |
auto[1] |
610 |
1 |
|
|
T20 |
3 |
|
T31 |
5 |
|
T39 |
3 |