Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::error_cg

Group : kmac_env_pkg::kmac_env_cov::error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
68.97	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	7	14	66.67
Crosses	8	2	6	75.00

Variables for Group kmac_env_pkg::kmac_env_cov::error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cmd	4	2	2	50.00	100	1	1	0
kmac_err_code	9	5	4	44.44	100	1	1	0
mode	3	0	3	100.00	100	1	1	0
strength	5	0	5	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_invalid_cmd_in_app_active	1	1	0	0.00	100	1	1	0
all_invalid_mode_strength_cfgs	7	1	6	85.71	100	1	1	0

Summary for Variable cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	2	2	50.00

Automatically Generated Bins for cmd

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[CmdProcess]	0	1	1
auto[CmdManualRun]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CmdNone]	0	Excluded
ignore	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[CmdStart]

300

1

T50

6

T51

6

T52

6

auto[CmdDone]

850

1

T50

17

T51

17

T52

17

---

Summary for Variable kmac_err_code

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	9	5	4	44.44

Automatically Generated Bins for kmac_err_code

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ErrSwPushedMsgFifo]	0	1	1
auto[ErrSwIssuedCmdInAppActive]	0	1	1
auto[ErrFatalError]	0	1	1
auto[ErrPackerIntegrity]	0	1	1
auto[ErrMsgFifoIntegrity]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[ErrNone]	0	Excluded
auto[ErrWaitTimerExpired]	0	Illegal
auto[ErrIncorrectEntropyMode]	0	Illegal
auto[ErrSwHashingWithoutEntropyReady]	0	Illegal
auto[ErrShadowRegUpdate]	0	Illegal
il	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ErrKeyNotValid]	50	1			T36	1		T37	1		T38	1
auto[ErrUnexpectedModeStrength]	600	1			T50	12		T51	12		T52	12
auto[ErrIncorrectFunctionName]	200	1			T50	4		T51	4		T52	4
auto[ErrSwCmdSequence]	350	1			T50	7		T51	7		T52	7

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	300	1			T50	6		T51	6		T52	6
auto[Shake]	150	1			T50	3		T51	3		T52	3
auto[CShake]	700	1			T50	14		T51	14		T52	14

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	550	1			T50	11		T51	11		T52	11
auto[L224]	50	1			T50	1		T51	1		T52	1
auto[L256]	150	1			T36	1		T37	1		T38	1
auto[L384]	100	1			T50	2		T51	2		T52	2
auto[L512]	350	1			T50	7		T51	7		T52	7

---

Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	1	0	0.00

User Defined Cross Bins for all_invalid_cmd_in_app_active

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
invalid_cmds	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

---

Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	7	1	6	85.71

User Defined Cross Bins for all_invalid_mode_strength_cfgs

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
shake_224_invalid_cfg	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha3_128_cfgs	200	1			T50	4		T51	4		T52	4
shake_384_invalid_cfg	50	1			T50	1		T51	1		T52	1
shake_512_invalid_cfg	50	1			T50	1		T51	1		T52	1
cshake_224_invalid_cfg	50	1			T50	1		T51	1		T52	1
cshake_384_invalid_cfg	50	1			T50	1		T51	1		T52	1
cshake_512_invalid_cfg	200	1			T50	4		T51	4		T52	4