Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	95083700	1			T12	5		T15	5		T17	5
all_pins[1]	95083700	1			T12	5		T15	5		T17	5
all_pins[2]	95083700	1			T12	5		T15	5		T17	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	240060010	1			T12	13		T15	13		T17	13
values[0x1]	45191090	1			T12	2		T15	2		T17	2
transitions[0x0=>0x1]	44794820	1			T12	2		T15	2		T17	2
transitions[0x1=>0x0]	44794820	1			T12	2		T15	2		T17	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	94589850	1			T12	3		T15	3		T17	3
all_pins[0]	values[0x1]	493850	1			T12	2		T15	2		T17	2
all_pins[0]	transitions[0x0=>0x1]	216970	1			T12	2		T15	2		T17	2
all_pins[0]	transitions[0x1=>0x0]	44134830	1			T20	22992		T21	109		T22	109
all_pins[1]	values[0x0]	50671990	1			T12	5		T15	5		T17	5
all_pins[1]	values[0x1]	44411710	1			T20	23360		T21	122		T22	122
all_pins[1]	transitions[0x0=>0x1]	44294300	1			T20	21445		T21	122		T22	122
all_pins[1]	transitions[0x1=>0x0]	168120	1			T20	2484		T39	2484		T40	2484
all_pins[2]	values[0x0]	94798170	1			T12	5		T15	5		T17	5
all_pins[2]	values[0x1]	285530	1			T20	4399		T39	4399		T40	4399
all_pins[2]	transitions[0x0=>0x1]	283550	1			T20	4367		T39	4367		T40	4367
all_pins[2]	transitions[0x1=>0x0]	491870	1			T12	2		T15	2		T17	2