Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg
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Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
output_digest_len 14 0 14 100.00 100 1 1 0


Summary for Variable output_digest_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 14 0 14 100.00


User Defined Bins for output_digest_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 400 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_801_1000 3740 1 T20 22 T35 7 T44 15
len_601_800 8700 1 T20 51 T35 24 T44 20
len_401_600 5610 1 T20 36 T35 17 T44 16
len_201_400 14490 1 T20 14 T35 4 T44 2
len_65_200 73670 1 T20 62 T31 685 T35 6
len_min_for_xof_require_squeeze 950 1 T31 9 T121 9 T122 9
len_keccak_block_sizes[72] 800 1 T20 1 T31 9 T39 1
len_keccak_block_sizes[104] 750 1 T20 1 T31 9 T39 1
len_keccak_block_sizes[136] 700 1 T31 9 T121 9 T122 9
len_keccak_block_sizes[144] 300 1 T20 1 T39 1 T40 1
len_keccak_block_sizes[168] 300 1 T20 1 T39 1 T40 1
len_datapath_width 14700 1 T20 21 T21 3 T22 3
len_2_63 213590 1 T20 108 T21 6 T22 6
len_1 50 1 T20 1 T39 1 T40 1

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