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 LINE       2783
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | 
     58  (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | 
     59  (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | 
     60  (addr_hit[59] & ((|(4'b1111 & (~reg_be))))) | 
     61  (addr_hit[60] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T11,T12
61 (addr_hit[60] & ((\|(4'...	Covered	T1,T13,T16
60 (addr_hit[59] & ((\|(4'...	Covered	T1,T12,T15
59 (addr_hit[58] & ((\|(4'...	Covered	T1,T11,T13
58 (addr_hit[57] & ((\|(4'...	Covered	T1,T13,T16
57 (addr_hit[56] & ((\|(4'...	Covered	T1,T11,T13
56 (addr_hit[55] & ((\|(4'...	Covered	T1,T11,T12
55 (addr_hit[54] & ((\|(4'...	Covered	T1,T11,T13
54 (addr_hit[53] & ((\|(4'...	Covered	T1,T11,T13
53 (addr_hit[52] & ((\|(4'...	Covered	T1,T13,T16
52 (addr_hit[51] & ((\|(4'...	Covered	T1,T11,T13
51 (addr_hit[50] & ((\|(4'...	Covered	T11,T13,T14
50 (addr_hit[49] & ((\|(4'...	Covered	T1,T11,T13
49 (addr_hit[48] & ((\|(4'...	Covered	T1,T13,T92
48 (addr_hit[47] & ((\|(4'...	Covered	T1,T11,T13
47 (addr_hit[46] & ((\|(4'...	Covered	T1,T11,T13
46 (addr_hit[45] & ((\|(4'...	Covered	T1,T11,T14
45 (addr_hit[44] & ((\|(4'...	Covered	T1,T13,T16
44 (addr_hit[43] & ((\|(4'...	Covered	T1,T11,T13
43 (addr_hit[42] & ((\|(4'...	Covered	T1,T11,T13
42 (addr_hit[41] & ((\|(4'...	Covered	T1,T13,T16
41 (addr_hit[40] & ((\|(4'...	Covered	T1,T11,T13
40 (addr_hit[39] & ((\|(4'...	Covered	T1,T11,T13
39 (addr_hit[38] & ((\|(4'...	Covered	T1,T13,T16
38 (addr_hit[37] & ((\|(4'...	Covered	T1,T11,T13
37 (addr_hit[36] & ((\|(4'...	Covered	T1,T13,T16
36 (addr_hit[35] & ((\|(4'...	Covered	T1,T13,T19
35 (addr_hit[34] & ((\|(4'...	Covered	T1,T11,T13
34 (addr_hit[33] & ((\|(4'...	Covered	T1,T13,T16
33 (addr_hit[32] & ((\|(4'...	Covered	T1,T13,T16
32 (addr_hit[31] & ((\|(4'...	Covered	T1,T13,T16
31 (addr_hit[30] & ((\|(4'...	Covered	T1,T13,T16
30 (addr_hit[29] & ((\|(4'...	Covered	T1,T11,T13
29 (addr_hit[28] & ((\|(4'...	Covered	T1,T11,T13
28 (addr_hit[27] & ((\|(4'...	Covered	T1,T13,T16
27 (addr_hit[26] & ((\|(4'...	Covered	T1,T13,T16
26 (addr_hit[25] & ((\|(4'...	Covered	T1,T11,T13
25 (addr_hit[24] & ((\|(4'...	Covered	T1,T13,T16
24 (addr_hit[23] & ((\|(4'...	Covered	T1,T13,T16
23 (addr_hit[22] & ((\|(4'...	Covered	T1,T11,T13
22 (addr_hit[21] & ((\|(4'...	Covered	T1,T13,T19
21 (addr_hit[20] & ((\|(4'...	Covered	T1,T13,T16
20 (addr_hit[19] & ((\|(4'...	Covered	T1,T13,T19
19 (addr_hit[18] & ((\|(4'...	Covered	T1,T16,T92
18 (addr_hit[17] & ((\|(4'...	Covered	T1,T11,T13
17 (addr_hit[16] & ((\|(4'...	Covered	T1,T13,T16
16 (addr_hit[15] & ((\|(4'...	Covered	T1,T11,T14
15 (addr_hit[14] & ((\|(4'...	Covered	T1,T13,T92
14 (addr_hit[13] & ((\|(4'...	Covered	T1,T11,T13
13 (addr_hit[12] & ((\|(4'...	Covered	T1,T13,T16
12 (addr_hit[11] & ((\|(4'...	Covered	T1,T13,T16
11 (addr_hit[10] & ((\|(4'...	Covered	T1,T11,T13
10 (addr_hit[9] & ((\|(4'b...	Covered	T1,T13,T92
9 (addr_hit[8] & ((\|(4'b...	Covered	T1,T13,T16
8 (addr_hit[7] & ((\|(4'b...	Covered	T1,T11,T13
7 (addr_hit[6] & ((\|(4'b...	Covered	T1,T16,T19
6 (addr_hit[5] & ((\|(4'b...	Covered	T1,T11,T13
5 (addr_hit[4] & ((\|(4'b...	Covered	T11,T14,T92
4 (addr_hit[3] & ((\|(4'b...	Covered	T1,T13,T16
3 (addr_hit[2] & ((\|(4'b...	Covered	T12,T13,T15
2 (addr_hit[1] & ((\|(4'b...	Covered	T1,T13,T16
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T11,T12

 LINE       2783
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T12,T15
1	1	Covered	T1,T11,T12

 LINE       2783
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T12
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T12
1	1	Covered	T12,T13,T15

 LINE       2783
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T14
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T11,T14,T92

 LINE       2783
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T11,T13,T14
1	1	Covered	T1,T16,T19

 LINE       2783
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T92

 LINE       2783
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T92

 LINE       2783
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T14

 LINE       2783
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T16,T92

 LINE       2783
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T19

 LINE       2783
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T19

 LINE       2783
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T19

 LINE       2783
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T14

 LINE       2783
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T92

 LINE       2783
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T11,T13,T14

 LINE       2783
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T12

 LINE       2783
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2783
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T11,T13

 LINE       2783
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T12,T15

 LINE       2783
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T13,T16

 LINE       2848
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T12,T15,T17

 LINE       2855
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T12

 LINE       2862
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T11,T12,T14

 LINE       2869
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T14

 LINE       2874
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2875
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2876
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T14

 LINE       2901
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T20,T21,T22

 LINE       2908
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2909
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2914
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2915
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2918
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13