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 LINE       2921
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2924
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2927
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2930
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2933
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2936
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2939
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2942
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2945
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2948
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2951
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2954
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2957
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2960
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2963
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2966
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2969
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2972
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2975
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2978
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2981
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2984
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2987
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2990
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       2993
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2996
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       2999
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3002
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3005
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       3008
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3011
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       3014
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3017
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3020
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       3023
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3026
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3029
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3032
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3035
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3038
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3041
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3044
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3047
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T1,T11,T13

 LINE       3050
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3053
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3056
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3059
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3062
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T1,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T13

 LINE       3435
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T13,T56,T99
1	0	Not Covered
1	1	Covered	T1,T11,T12