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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.00 96.28 87.03 100.00 76.14 93.85 96.36 87.38


Total test records in report: 1240
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T1015 /workspace/coverage/default/16.kmac_entropy_mode_error.79735389371102744752756657160753620984831212748592437177613927817366109736339 Nov 22 01:53:42 PM PST 23 Nov 22 01:54:12 PM PST 23 2211297553 ps
T1016 /workspace/coverage/default/45.kmac_test_vectors_shake_256.44460750114942258214124349244803094544578792920099481720614223198786074446679 Nov 22 01:54:48 PM PST 23 Nov 22 02:58:47 PM PST 23 258047411562 ps
T1017 /workspace/coverage/default/6.kmac_lc_escalation.85654936317117197540084040155958460141616839265879442611800334532912465569578 Nov 22 01:52:47 PM PST 23 Nov 22 01:52:52 PM PST 23 58171921 ps
T1018 /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.44471205007801349960482092046214596662319873236671549985041954610311297622576 Nov 22 01:54:15 PM PST 23 Nov 22 01:54:21 PM PST 23 289902210 ps
T1019 /workspace/coverage/default/47.kmac_smoke.93826163824089139056991064949248867336799781006415804303251281991298831663816 Nov 22 01:54:37 PM PST 23 Nov 22 01:54:57 PM PST 23 1554463522 ps
T1020 /workspace/coverage/default/9.kmac_test_vectors_sha3_256.47734705967661617992982080324095665350074032996297213241500132081251619585081 Nov 22 01:53:21 PM PST 23 Nov 22 02:19:47 PM PST 23 107886220004 ps
T1021 /workspace/coverage/default/33.kmac_test_vectors_shake_256.49133631329281555273080251740567497578698053771097493096147602497236430824921 Nov 22 01:54:24 PM PST 23 Nov 22 02:56:38 PM PST 23 258047411562 ps
T1022 /workspace/coverage/default/11.kmac_entropy_mode_error.58398954737154573949244422589844168216582374710123592600951091816641640757560 Nov 22 01:53:16 PM PST 23 Nov 22 01:53:52 PM PST 23 2211297553 ps
T1023 /workspace/coverage/default/27.kmac_test_vectors_sha3_224.82692062225679520187610036675627448465288662231928774754217531532568219900636 Nov 22 01:53:45 PM PST 23 Nov 22 02:22:55 PM PST 23 115269125226 ps
T1024 /workspace/coverage/default/25.kmac_key_error.28884140562273686761567606924037310168842348617252429974010995221510375930929 Nov 22 01:53:55 PM PST 23 Nov 22 01:54:01 PM PST 23 1579963318 ps
T1025 /workspace/coverage/default/44.kmac_lc_escalation.78939193879810474911526453681292776793331559148503664132496358355914068540637 Nov 22 01:54:52 PM PST 23 Nov 22 01:54:55 PM PST 23 58171921 ps
T1026 /workspace/coverage/default/32.kmac_lc_escalation.22211946032612672943825895837115095766774066507271122142982673698238798271518 Nov 22 01:54:10 PM PST 23 Nov 22 01:54:12 PM PST 23 58171921 ps
T1027 /workspace/coverage/default/1.kmac_app_with_partial_data.26333999441025253475947196815508802941406020482716860326707441144950538787460 Nov 22 01:52:26 PM PST 23 Nov 22 01:53:54 PM PST 23 7615861459 ps
T1028 /workspace/coverage/default/47.kmac_test_vectors_sha3_256.71618449230502561076049219188590668965871113164265068724910710033889364540095 Nov 22 01:54:54 PM PST 23 Nov 22 02:21:16 PM PST 23 107886220004 ps
T1029 /workspace/coverage/default/28.kmac_entropy_refresh.108598841213929932285128345392085605031734061330950674522939034773326235658773 Nov 22 01:53:36 PM PST 23 Nov 22 01:54:50 PM PST 23 6743332725 ps
T1030 /workspace/coverage/default/7.kmac_burst_write.47228797925641868277577691699569180191712932763831148968543488689181670566858 Nov 22 01:52:39 PM PST 23 Nov 22 01:56:49 PM PST 23 14812750312 ps
T1031 /workspace/coverage/default/14.kmac_stress_all.36595836186544486284801089514258898875316239288528638334418273446208036589274 Nov 22 01:53:16 PM PST 23 Nov 22 02:03:51 PM PST 23 41434001626 ps
T1032 /workspace/coverage/default/27.kmac_test_vectors_sha3_256.68696401843042406806522330740501394319693396676725620015494002780901816952259 Nov 22 01:53:47 PM PST 23 Nov 22 02:20:43 PM PST 23 107886220004 ps
T1033 /workspace/coverage/default/11.kmac_test_vectors_shake_128.10579092381636893879320276223836919185010619036669934220262862011563858377579 Nov 22 01:53:28 PM PST 23 Nov 22 03:08:01 PM PST 23 307766781661 ps
T1034 /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.28419275912510111798739309072786711804583826931763929073842698432499525814365 Nov 22 01:55:02 PM PST 23 Nov 22 01:55:10 PM PST 23 289902210 ps
T1035 /workspace/coverage/default/36.kmac_long_msg_and_output.27230244950180607727270277209058385700705155532827264804361747592234655094707 Nov 22 01:54:11 PM PST 23 Nov 22 02:06:02 PM PST 23 45517522529 ps
T1036 /workspace/coverage/default/2.kmac_test_vectors_sha3_256.38068074464953720105612618386475209565383524028373965626114305181768896009507 Nov 22 01:52:36 PM PST 23 Nov 22 02:19:38 PM PST 23 107886220004 ps
T1037 /workspace/coverage/default/22.kmac_test_vectors_sha3_384.99795417333934523819871717139295586716094034430693819812624189671302734531917 Nov 22 01:53:35 PM PST 23 Nov 22 02:13:57 PM PST 23 83070954242 ps
T1038 /workspace/coverage/default/27.kmac_key_error.50012123555425561599709468869339606076355780298265278928354011455997266898733 Nov 22 01:53:42 PM PST 23 Nov 22 01:53:48 PM PST 23 1579963318 ps
T1039 /workspace/coverage/default/4.kmac_alert_test.75900130372302542253971875900449752208341094233863922431332074558304210740138 Nov 22 01:53:36 PM PST 23 Nov 22 01:53:38 PM PST 23 21118646 ps
T1040 /workspace/coverage/default/6.kmac_edn_timeout_error.109883267056356586854206240803149623341177902044883501391210435595679710649424 Nov 22 01:52:48 PM PST 23 Nov 22 01:53:25 PM PST 23 2342046507 ps
T1041 /workspace/coverage/default/37.kmac_burst_write.90457926874815757201644256674926998221398251400864782192491109154629508150265 Nov 22 01:54:22 PM PST 23 Nov 22 01:58:30 PM PST 23 14812750312 ps
T1042 /workspace/coverage/default/1.kmac_test_vectors_kmac.61610284026692438262368683017449259269004667458989958790305166277502115030671 Nov 22 01:52:24 PM PST 23 Nov 22 01:52:31 PM PST 23 298812853 ps
T1043 /workspace/coverage/default/48.kmac_stress_all.97188991102246294218256458976874367042669767593408686053230073355682956906065 Nov 22 01:54:48 PM PST 23 Nov 22 02:04:39 PM PST 23 41434001626 ps
T1044 /workspace/coverage/default/47.kmac_sideload.8836625782132917855009074885850781440280907533317453752843479762150106357326 Nov 22 01:54:50 PM PST 23 Nov 22 01:56:45 PM PST 23 7733092664 ps
T1045 /workspace/coverage/default/12.kmac_test_vectors_shake_256.23244660259507699079057176922377730128090392325726708344221757959359280584721 Nov 22 01:52:54 PM PST 23 Nov 22 02:51:23 PM PST 23 258047411562 ps
T1046 /workspace/coverage/default/40.kmac_app.42566120521155456583137686683022456930118530885017214675416457631782480923037 Nov 22 01:54:34 PM PST 23 Nov 22 01:55:49 PM PST 23 5659537824 ps
T1047 /workspace/coverage/default/5.kmac_test_vectors_sha3_224.41393024915740163414282640375818859544393121469183087930504968216960176841324 Nov 22 01:52:44 PM PST 23 Nov 22 02:21:00 PM PST 23 115269125226 ps
T1048 /workspace/coverage/default/17.kmac_entropy_mode_error.75571835431712284923561213539944727081318854943657114759100098173501772899506 Nov 22 01:53:46 PM PST 23 Nov 22 01:54:18 PM PST 23 2211297553 ps
T1049 /workspace/coverage/default/8.kmac_sideload.24137814532306686106831780062735777512859443536640582949854166917768113488505 Nov 22 01:52:50 PM PST 23 Nov 22 01:54:45 PM PST 23 7733092664 ps
T1050 /workspace/coverage/default/0.kmac_test_vectors_shake_128.17871937101333501473220221969449716967983296966023166697822780982680926739943 Nov 22 01:52:23 PM PST 23 Nov 22 03:10:34 PM PST 23 307766781661 ps
T1051 /workspace/coverage/default/4.kmac_edn_timeout_error.83058536111427304088746288419140758360156415653468385232153114250768579146901 Nov 22 01:52:53 PM PST 23 Nov 22 01:53:29 PM PST 23 2342046507 ps
T1052 /workspace/coverage/default/20.kmac_test_vectors_kmac.27243759331622687603584682054764193787783452287855894456991349718155416915387 Nov 22 01:53:55 PM PST 23 Nov 22 01:54:00 PM PST 23 298812853 ps
T1053 /workspace/coverage/default/32.kmac_alert_test.26717514017683507329230042804920569537495336881595505732708821264194178163500 Nov 22 01:53:53 PM PST 23 Nov 22 01:53:55 PM PST 23 21118646 ps
T1054 /workspace/coverage/default/36.kmac_test_vectors_sha3_512.41743743613480920389680096251007520297223649624857642856810660611588027349926 Nov 22 01:54:13 PM PST 23 Nov 22 02:08:41 PM PST 23 58503507926 ps
T1055 /workspace/coverage/default/26.kmac_app.47911349085330601986492777083661946184846895488847160224579384232904277586756 Nov 22 01:53:46 PM PST 23 Nov 22 01:55:06 PM PST 23 5659537824 ps
T1056 /workspace/coverage/default/7.kmac_test_vectors_shake_256.3358886882144582231029675037352095810651296196300599722650089171329054699610 Nov 22 01:52:47 PM PST 23 Nov 22 02:53:30 PM PST 23 258047411562 ps
T1057 /workspace/coverage/default/27.kmac_test_vectors_sha3_384.38564469773460366266038061650640774541240309447981517815705831003782070607828 Nov 22 01:53:41 PM PST 23 Nov 22 02:14:38 PM PST 23 83070954242 ps
T1058 /workspace/coverage/default/16.kmac_test_vectors_sha3_224.45198725003258536863210996562643007258534232527682540213871758043412078803244 Nov 22 01:53:19 PM PST 23 Nov 22 02:22:14 PM PST 23 115269125226 ps
T1059 /workspace/coverage/default/34.kmac_key_error.5873697661740951996831612338295346094085633488681833522723875895842401499036 Nov 22 01:54:12 PM PST 23 Nov 22 01:54:19 PM PST 23 1579963318 ps
T1060 /workspace/coverage/default/14.kmac_test_vectors_shake_128.1037035046229036229717152067154159799325417472254027102806444089308492131981 Nov 22 01:53:19 PM PST 23 Nov 22 03:05:53 PM PST 23 307766781661 ps
T1061 /workspace/coverage/default/12.kmac_smoke.81436252578324021516592872700861042143593378324620875257528585874239286396698 Nov 22 01:53:20 PM PST 23 Nov 22 01:53:42 PM PST 23 1554463522 ps
T1062 /workspace/coverage/default/32.kmac_long_msg_and_output.26810470157670686727766386077318510866356271836021442354822009194076978646817 Nov 22 01:53:49 PM PST 23 Nov 22 02:05:45 PM PST 23 45517522529 ps
T1063 /workspace/coverage/default/22.kmac_app.99343366321119541252350332769523866670654303710508329951168613747467418214277 Nov 22 01:53:38 PM PST 23 Nov 22 01:54:56 PM PST 23 5659537824 ps
T1064 /workspace/coverage/default/24.kmac_burst_write.107195030066964917293419132978850306292352576026679557971639348502402182904491 Nov 22 01:54:13 PM PST 23 Nov 22 01:58:15 PM PST 23 14812750312 ps
T1065 /workspace/coverage/default/9.kmac_entropy_ready_error.103547344180861297440854439796987760934476466307446933190022881854091703686317 Nov 22 01:52:53 PM PST 23 Nov 22 01:53:13 PM PST 23 2782989408 ps
T1066 /workspace/coverage/default/7.kmac_entropy_mode_error.5581590703045833531845133211605082108323473394902552114180594595034822748443 Nov 22 01:52:48 PM PST 23 Nov 22 01:53:22 PM PST 23 2211297553 ps
T1067 /workspace/coverage/default/47.kmac_test_vectors_kmac.74874023788825247751223578105777484728938569407915170421812127244888560238398 Nov 22 01:54:49 PM PST 23 Nov 22 01:54:56 PM PST 23 298812853 ps
T1068 /workspace/coverage/default/22.kmac_test_vectors_shake_128.86661388739294311060831849270015763711497310267443182411385816972540407260292 Nov 22 01:53:50 PM PST 23 Nov 22 03:07:38 PM PST 23 307766781661 ps
T1069 /workspace/coverage/default/23.kmac_test_vectors_kmac.51605701733017724603379303962603602787902048139674173958857894910270392030755 Nov 22 01:54:00 PM PST 23 Nov 22 01:54:05 PM PST 23 298812853 ps
T1070 /workspace/coverage/default/35.kmac_entropy_refresh.92176243653606363886747627498667701970001773252565120755687269444221443967506 Nov 22 01:54:19 PM PST 23 Nov 22 01:55:36 PM PST 23 6743332725 ps
T1071 /workspace/coverage/default/0.kmac_test_vectors_sha3_512.75632856362413866038974457580527248050027521458772817669613345519573132581957 Nov 22 01:52:39 PM PST 23 Nov 22 02:07:27 PM PST 23 58503507926 ps
T1072 /workspace/coverage/default/22.kmac_burst_write.112377214926778515262667030335105234826946145352199699399008565184283784879278 Nov 22 01:53:40 PM PST 23 Nov 22 01:57:45 PM PST 23 14812750312 ps
T1073 /workspace/coverage/default/26.kmac_key_error.105860344660039436482431775798857414415914377951490533130320972979676286485551 Nov 22 01:53:52 PM PST 23 Nov 22 01:54:03 PM PST 23 1579963318 ps
T1074 /workspace/coverage/default/17.kmac_smoke.87531123787050937966344897961023029888212950777349774201095508140424687927771 Nov 22 01:53:20 PM PST 23 Nov 22 01:53:42 PM PST 23 1554463522 ps
T1075 /workspace/coverage/default/48.kmac_test_vectors_sha3_512.84270325516919500058266511384742670588490591169149474049303114883042219433743 Nov 22 01:55:00 PM PST 23 Nov 22 02:09:51 PM PST 23 58503507926 ps
T1076 /workspace/coverage/default/30.kmac_burst_write.17282803111031652302845996751823307392275694186610312286596281689988195492078 Nov 22 01:53:37 PM PST 23 Nov 22 01:57:36 PM PST 23 14812750312 ps
T1077 /workspace/coverage/default/13.kmac_burst_write.49961780114682460931460810650183440714237203466228588705148317781064413597674 Nov 22 01:53:55 PM PST 23 Nov 22 01:58:01 PM PST 23 14812750312 ps
T1078 /workspace/coverage/default/44.kmac_key_error.8806917810545907393725778580007343248638011450260436926263764108378432561665 Nov 22 01:54:36 PM PST 23 Nov 22 01:54:42 PM PST 23 1579963318 ps
T1079 /workspace/coverage/default/7.kmac_app_with_partial_data.102074179514194318138075503139155549131768865358441313782530485912739982140475 Nov 22 01:52:49 PM PST 23 Nov 22 01:54:16 PM PST 23 7615861459 ps
T1080 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.22508268829177866394920353273041030629564129723218277232345633468530683550958 Nov 22 01:49:59 PM PST 23 Nov 22 01:50:02 PM PST 23 38832790 ps
T1081 /workspace/coverage/cover_reg_top/3.kmac_intr_test.80610167291956460871240771105254612793201447669722592182166820400987612842053 Nov 22 01:49:30 PM PST 23 Nov 22 01:49:35 PM PST 23 22940060 ps
T1082 /workspace/coverage/cover_reg_top/31.kmac_intr_test.79257129228716022138005491021819840328607184486425125233051050317868043005420 Nov 22 01:50:09 PM PST 23 Nov 22 01:50:16 PM PST 23 22940060 ps
T1083 /workspace/coverage/cover_reg_top/6.kmac_intr_test.52100306574866245796901778804239819422811492708424564182562557403284368114092 Nov 22 01:49:48 PM PST 23 Nov 22 01:49:50 PM PST 23 22940060 ps
T1084 /workspace/coverage/cover_reg_top/47.kmac_intr_test.77291687128356953706070132167151218178803941372320128681986979370387535959000 Nov 22 01:50:08 PM PST 23 Nov 22 01:50:15 PM PST 23 22940060 ps
T1085 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.32989413035819863523929055264289089809577542311348437206370211252436113063895 Nov 22 01:49:55 PM PST 23 Nov 22 01:49:58 PM PST 23 30368572 ps
T1086 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.31696243166037550259462961911306547213009476631929998574666072369812564318206 Nov 22 01:49:56 PM PST 23 Nov 22 01:49:59 PM PST 23 30368572 ps
T1087 /workspace/coverage/cover_reg_top/30.kmac_intr_test.104673044512941496682202726325353772489792293559903772500717105498451120491546 Nov 22 01:50:09 PM PST 23 Nov 22 01:50:16 PM PST 23 22940060 ps
T1088 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.19136017763360001533543093834774164118597677501275845615084536342489703023410 Nov 22 01:49:36 PM PST 23 Nov 22 01:49:42 PM PST 23 88046682 ps
T102 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.52594270384500821979468900484385299303411094900891887256342789102036828032306 Nov 22 01:49:31 PM PST 23 Nov 22 01:49:37 PM PST 23 46939868 ps
T1089 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.67001377758284327894003781579520681671366841038054251381663273484643213002458 Nov 22 01:49:46 PM PST 23 Nov 22 01:49:48 PM PST 23 30368572 ps
T1090 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.107156363365419058293158438905819366524942508195934044360514299360615913410855 Nov 22 01:49:56 PM PST 23 Nov 22 01:49:58 PM PST 23 38832790 ps
T1091 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.104288024949550700137525366898412355679040256310708683771145092864874600960790 Nov 22 01:49:31 PM PST 23 Nov 22 01:49:36 PM PST 23 38832790 ps
T1092 /workspace/coverage/cover_reg_top/27.kmac_intr_test.71695623168679488873665016746186106552788223637809210307321901424966147653740 Nov 22 01:50:03 PM PST 23 Nov 22 01:50:07 PM PST 23 22940060 ps
T1093 /workspace/coverage/cover_reg_top/39.kmac_intr_test.59566580772087284596330393637311756408940013850808202012194435223809656276313 Nov 22 01:50:03 PM PST 23 Nov 22 01:50:07 PM PST 23 22940060 ps
T1094 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.78848430976128640162987118575098267039257046338167440825303639165157026825784 Nov 22 01:49:34 PM PST 23 Nov 22 01:49:42 PM PST 23 193117270 ps
T1095 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.68965720248584752667693470054660431448137998288510975021853782033143519035417 Nov 22 01:49:45 PM PST 23 Nov 22 01:49:48 PM PST 23 88046682 ps
T1096 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.108099934860248406095509921094275908374029211628310485865577513311665213841357 Nov 22 01:49:35 PM PST 23 Nov 22 01:49:41 PM PST 23 30368572 ps
T103 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.60078051299387277217956379259858721394229972780860946697897808495648562612914 Nov 22 01:49:19 PM PST 23 Nov 22 01:49:22 PM PST 23 46939868 ps
T104 /workspace/coverage/cover_reg_top/38.kmac_intr_test.41907131322977519567962260524390029115118557020758384940221899938209101435446 Nov 22 01:50:05 PM PST 23 Nov 22 01:50:10 PM PST 23 22940060 ps
T105 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.72268871241636421612917277466210815715143070395613079850815862640214688176609 Nov 22 01:50:07 PM PST 23 Nov 22 01:50:14 PM PST 23 88046682 ps
T106 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.6089400978761205767602682259891769968221472838924344685703726206785025919901 Nov 22 01:49:45 PM PST 23 Nov 22 01:49:47 PM PST 23 30368572 ps
T107 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.6002559826478676304969507072059265347499848732070406067316945270061846372013 Nov 22 01:49:32 PM PST 23 Nov 22 01:49:37 PM PST 23 46939868 ps
T108 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.93698700058888751057492605006804066094305513466819911230251728360167459384997 Nov 22 01:49:27 PM PST 23 Nov 22 01:49:34 PM PST 23 403472730 ps
T109 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3898107025509151167232465044125349107832054619922668404000204471124823236269 Nov 22 01:49:29 PM PST 23 Nov 22 01:49:34 PM PST 23 88046682 ps
T110 /workspace/coverage/cover_reg_top/9.kmac_intr_test.9564002824850357602259539125898242011573794751079816952245890245301377400039 Nov 22 01:50:01 PM PST 23 Nov 22 01:50:04 PM PST 23 22940060 ps
T1097 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.48392152047682390055481083555814898361085820055173110854612025493675482671597 Nov 22 01:49:23 PM PST 23 Nov 22 01:49:28 PM PST 23 193117270 ps
T1098 /workspace/coverage/cover_reg_top/18.kmac_intr_test.97038929350986417364511469070765291118214165684300004405665882889939729537156 Nov 22 01:49:57 PM PST 23 Nov 22 01:49:59 PM PST 23 22940060 ps
T1099 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.50674621715809413494124526640242718660418932066890037935850037453695319105782 Nov 22 01:49:53 PM PST 23 Nov 22 01:49:56 PM PST 23 88046682 ps
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T1185 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.6875108310375318355133851646309905697153624911799781038885865720852374378145 Nov 22 01:49:18 PM PST 23 Nov 22 01:49:22 PM PST 23 103242989 ps
T1186 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.60219881853755170076257136427874595450451836465916410464903737644418213190334 Nov 22 01:50:00 PM PST 23 Nov 22 01:50:03 PM PST 23 32814981 ps
T1187 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2786008066908511586307905673687052107613126086020394811875351243345564719416 Nov 22 01:49:35 PM PST 23 Nov 22 01:49:41 PM PST 23 96832326 ps
T1188 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.82873054789414157297926229062482721941000539480255781089628780030710673836598 Nov 22 01:49:50 PM PST 23 Nov 22 01:49:53 PM PST 23 103242989 ps
T1189 /workspace/coverage/cover_reg_top/49.kmac_intr_test.39750706018455388200676852885597247391938886820206737710359248706284247396547 Nov 22 01:50:24 PM PST 23 Nov 22 01:50:26 PM PST 23 22940060 ps
T1190 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.77970088238060912312702770939242797683725072293769962625630453926683154356305 Nov 22 01:49:28 PM PST 23 Nov 22 01:49:40 PM PST 23 403472730 ps
T1191 /workspace/coverage/cover_reg_top/32.kmac_intr_test.107921580117730145612476441048213587673267237404600463842450613461376612668413 Nov 22 01:49:58 PM PST 23 Nov 22 01:50:00 PM PST 23 22940060 ps
T1192 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.7794043631339445293600013528368684211551570937416780328147601349025411688135 Nov 22 01:49:32 PM PST 23 Nov 22 01:49:38 PM PST 23 103242989 ps
T1193 /workspace/coverage/cover_reg_top/16.kmac_intr_test.58728256142700428481782691410717343961732995786945690881089211124220523361671 Nov 22 01:49:59 PM PST 23 Nov 22 01:50:01 PM PST 23 22940060 ps
T1194 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.114014280125098115130294221817295262856053358395680963790359163777775992948257 Nov 22 01:49:56 PM PST 23 Nov 22 01:49:59 PM PST 23 38832790 ps
T1195 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.6236651988624750406876675325089747748247394304759569042155707028307710026401 Nov 22 01:49:54 PM PST 23 Nov 22 01:49:56 PM PST 23 38832790 ps
T1196 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.83236739259299933735615749086338125559328481576954773241280128388426688961091 Nov 22 01:50:03 PM PST 23 Nov 22 01:50:07 PM PST 23 38832790 ps
T1197 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.84537608269065375058878767828525569843857876429523061747504556754502698802165 Nov 22 01:50:02 PM PST 23 Nov 22 01:50:05 PM PST 23 32814981 ps
T1198 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.47146965081887127634707803463769900878333154202754217800143461249988247045108 Nov 22 01:49:34 PM PST 23 Nov 22 01:49:40 PM PST 23 88046682 ps
T1199 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.8935196521699979172140137519123724491846293190709345796296401743941268640728 Nov 22 01:49:48 PM PST 23 Nov 22 01:49:52 PM PST 23 193117270 ps
T1200 /workspace/coverage/cover_reg_top/21.kmac_intr_test.4253281032559884032066045254941724548457640054235829875979801786137683960282 Nov 22 01:49:49 PM PST 23 Nov 22 01:49:51 PM PST 23 22940060 ps
T1201 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.53231205151945923824364636180043500825310110766055544489389436252891343766282 Nov 22 01:50:00 PM PST 23 Nov 22 01:50:05 PM PST 23 88046682 ps
T1202 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.36043480846901462952180227076120456807018756606293036560297860362464678673683 Nov 22 01:49:46 PM PST 23 Nov 22 01:49:48 PM PST 23 32814981 ps
T1203 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.67823760003801410150669529379429410127673290917926996970392900402029641798655 Nov 22 01:49:40 PM PST 23 Nov 22 01:49:48 PM PST 23 403472730 ps
T1204 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4046964244527069298068377562527821662067119397119656268003283162021909039517 Nov 22 01:49:38 PM PST 23 Nov 22 01:49:42 PM PST 23 32814981 ps
T1205 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.115569773188172082113624546472562619707988276029105226899530990627908162893756 Nov 22 01:49:32 PM PST 23 Nov 22 01:49:38 PM PST 23 29368580 ps
T1206 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.42839716268989509435525118751072733768337751187024183308032192537583155328758 Nov 22 01:49:56 PM PST 23 Nov 22 01:49:59 PM PST 23 30368572 ps
T1207 /workspace/coverage/cover_reg_top/36.kmac_intr_test.67148882857935623076375890469388480877256078143166959908742477483547731562762 Nov 22 01:50:08 PM PST 23 Nov 22 01:50:15 PM PST 23 22940060 ps
T1208 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.12410932429006685479814260478457077311591367684230102903748252947149233346151 Nov 22 01:49:23 PM PST 23 Nov 22 01:49:26 PM PST 23 32814981 ps
T1209 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.23563314129206813843993915138626260279487435678759870537935085752441953684083 Nov 22 01:49:34 PM PST 23 Nov 22 01:49:40 PM PST 23 30368572 ps
T1210 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1426252361745159442903851333058245073347440850712373023998357759846636520731 Nov 22 01:49:55 PM PST 23 Nov 22 01:49:58 PM PST 23 103242989 ps
T1211 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.44064909497655139732999715062446143096402607969814409924368207819623328872487 Nov 22 01:49:59 PM PST 23 Nov 22 01:50:04 PM PST 23 88046682 ps
T1212 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.71992410631988823849021249140094941470056255564713151376345657457757939220258 Nov 22 01:49:55 PM PST 23 Nov 22 01:49:58 PM PST 23 88046682 ps
T1213 /workspace/coverage/cover_reg_top/43.kmac_intr_test.86827849219470250761165943633613477760441146809534049145867221108841925431825 Nov 22 01:50:12 PM PST 23 Nov 22 01:50:18 PM PST 23 22940060 ps
T1214 /workspace/coverage/cover_reg_top/45.kmac_intr_test.41654843852452479153952747388818154804230831967526540579996994376788055180285 Nov 22 01:50:15 PM PST 23 Nov 22 01:50:19 PM PST 23 22940060 ps
T1215 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.113862600026031967645990856313809591027635979625554977927772045537673661492339 Nov 22 01:49:44 PM PST 23 Nov 22 01:49:48 PM PST 23 103242989 ps
T1216 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.64556421797145199955595270513584790464605232704040615283934767354751790201737 Nov 22 01:49:30 PM PST 23 Nov 22 01:49:36 PM PST 23 96832326 ps
T1217 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.104161235508609437232016333313752951425640445919779211555620156373836192789040 Nov 22 01:49:50 PM PST 23 Nov 22 01:49:52 PM PST 23 88046682 ps
T1218 /workspace/coverage/cover_reg_top/28.kmac_intr_test.88565657425446427283385838321532566777948179722278116513627152445500434632693 Nov 22 01:50:00 PM PST 23 Nov 22 01:50:04 PM PST 23 22940060 ps
T1219 /workspace/coverage/cover_reg_top/12.kmac_intr_test.7197014735271622952698232742611050496088195413325538912144259150990259824506 Nov 22 01:49:53 PM PST 23 Nov 22 01:49:54 PM PST 23 22940060 ps
T1220 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.48031617649656804315625784357312746483842996693668999292452719515863638468463 Nov 22 01:49:30 PM PST 23 Nov 22 01:49:37 PM PST 23 193117270 ps
T1221 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.48684059429637701419640973890872516964810519904064827096361555169585052619667 Nov 22 01:49:48 PM PST 23 Nov 22 01:49:52 PM PST 23 193117270 ps
T1222 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.61664093240373888605905540780110632438192962522523152496284249084617019122444 Nov 22 01:50:05 PM PST 23 Nov 22 01:50:09 PM PST 23 32814981 ps
T1223 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.34348017750492534678471767548235051209089078828886152861985942068505435640138 Nov 22 01:49:31 PM PST 23 Nov 22 01:49:37 PM PST 23 30368572 ps
T1224 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.25159917674364927070463428497625190793094911930719209963700123378610740983713 Nov 22 01:49:46 PM PST 23 Nov 22 01:49:48 PM PST 23 32814981 ps
T1225 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.14032109157251106026564814791723981182925714944595408053857760412559441446966 Nov 22 01:50:00 PM PST 23 Nov 22 01:50:04 PM PST 23 88046682 ps
T1226 /workspace/coverage/cover_reg_top/11.kmac_intr_test.109443262123477699303164142371668452422340280368083444814911227675474906413576 Nov 22 01:49:32 PM PST 23 Nov 22 01:49:37 PM PST 23 22940060 ps
T1227 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.84711468349119573499656929316389765680947234890723724201399177791171956462017 Nov 22 01:49:38 PM PST 23 Nov 22 01:49:42 PM PST 23 32814981 ps
T1228 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.95809466804225067818464006886534819147131377386671392143050205091613552952214 Nov 22 01:49:54 PM PST 23 Nov 22 01:49:58 PM PST 23 193117270 ps
T1229 /workspace/coverage/cover_reg_top/29.kmac_intr_test.28877983700123703211070974786487615980465907880610742046350426747856762665819 Nov 22 01:50:05 PM PST 23 Nov 22 01:50:09 PM PST 23 22940060 ps
T1230 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.112944150956954432491623875141802372344128124538361851312697857168858686777134 Nov 22 01:49:24 PM PST 23 Nov 22 01:49:28 PM PST 23 96832326 ps
T1231 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.111765173134503699609503638033518313407706433859210486030210106865000702137341 Nov 22 01:49:26 PM PST 23 Nov 22 01:49:28 PM PST 23 16922251 ps
T1232 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.58030150049249448087958397733516722213383441425426333791897386804427236741416 Nov 22 01:49:35 PM PST 23 Nov 22 01:49:41 PM PST 23 32814981 ps
T1233 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.29846418826442953587623421267455964449962792917380644511944788072364416190211 Nov 22 01:49:30 PM PST 23 Nov 22 01:49:35 PM PST 23 30368572 ps
T1234 /workspace/coverage/cover_reg_top/10.kmac_intr_test.95451289785710464426288382397035392533613483195746081825204719999415244266120 Nov 22 01:49:28 PM PST 23 Nov 22 01:49:31 PM PST 23 22940060 ps
T1235 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.30999751552743201061554671912403510993316762271936923635161373600726509201557 Nov 22 01:49:46 PM PST 23 Nov 22 01:49:53 PM PST 23 103242989 ps
T1236 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.77101129982502590988892395496833483472158654690800924525126568597077822066361 Nov 22 01:49:58 PM PST 23 Nov 22 01:50:01 PM PST 23 96832326 ps
T1237 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.60309624225795494990313748157279255368137276300870916694002143126785479966961 Nov 22 01:49:43 PM PST 23 Nov 22 01:49:46 PM PST 23 96832326 ps
T1238 /workspace/coverage/cover_reg_top/48.kmac_intr_test.24946127021751506606564936947257613449040174617517127029015005272562153052987 Nov 22 01:49:58 PM PST 23 Nov 22 01:50:01 PM PST 23 22940060 ps
T1239 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.110809061891202280523637405118935336174165675626209593889455558146206615283405 Nov 22 01:50:01 PM PST 23 Nov 22 01:50:05 PM PST 23 30368572 ps
T1240 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.8013723801549894815562166060033057747773843107971931342848616718103769658618 Nov 22 01:49:58 PM PST 23 Nov 22 01:50:02 PM PST 23 96832326 ps

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.49652619655224118286040619785557307485235692129097487470455449319056327918992
Short name T1
Test name
Test status
Simulation time 193117270 ps
CPU time 2.78 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 215460 kb
Host smart-de5cf14f-68b8-48c1-a0aa-abb743fc6a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49652619655224118286040619785557307485235692129097487470455449319056327918992 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.49652619655224118286040619785557307485235692129097487470455449319056327918992 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/15.kmac_stress_all.79520253655551281244732467752398333511472883467777522635940312123313143846747
Short name T20
Test name
Test status
Simulation time 41434001626 ps
CPU time 630.47 seconds
Started Nov 22 01:52:56 PM PST 23
Finished Nov 22 02:03:28 PM PST 23
Peak memory 321708 kb
Host smart-5405a19d-595d-4805-9417-4a91f4332927
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=79520253655551281244732467752398333511472883467777522635940312123313143846747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_st
ress_all.79520253655551281244732467752398333511472883467777522635940312123313143846747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.35077511881994150392363400293290615237293039476482671366119829442962318497674
Short name T2
Test name
Test status
Simulation time 103242989 ps
CPU time 1.93 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 215524 kb
Host smart-252d3e57-cf1b-4f4a-8776-86aa639be59f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077511881994150392363400293290615237293039476482671366119829442962318497674 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.35077511881994150392363400293290615237293039476482671366119829442962318497674 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.4870287782809247757483421941698939812397260311781082639572497903479805437313
Short name T26
Test name
Test status
Simulation time 4127675079 ps
CPU time 33.22 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 249068 kb
Host smart-54cdb897-a663-49fc-a4ff-2399c8241c57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4870287782809247757483421941698939812397260311781082639572497903479805437313 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.kmac_sec_cm.4870287782809247757483421941698939812397260311781082639572497903479805437313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.114690038643563065031252120720839486751233812915374721254655748396084750516325
Short name T42
Test name
Test status
Simulation time 6743332725 ps
CPU time 75.52 seconds
Started Nov 22 01:53:12 PM PST 23
Finished Nov 22 01:54:32 PM PST 23
Peak memory 227020 kb
Host smart-8e84cb71-96de-4aff-8aab-fedb71d051c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114690038643563065031252120720839486751233812915374721254655748396084750516325 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.kmac_entropy_refresh.114690038643563065031252120720839486751233812915374721254655748396084750516325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.57942624066838254877940948912767042673922026542544060531368104676423345113677
Short name T50
Test name
Test status
Simulation time 8615085608 ps
CPU time 129.65 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:54:32 PM PST 23
Peak memory 248560 kb
Host smart-908714d4-045c-4b6a-b895-8ca846aaa793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57942624066838254877940948912767042673922026542544060531368104676423345113677 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.kmac_error.57942624066838254877940948912767042673922026542544060531368104676423345113677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.36570993781525549402363843160830164505345476091878227789523175080315542585504
Short name T17
Test name
Test status
Simulation time 22940060 ps
CPU time 0.77 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:26 PM PST 23
Peak memory 207012 kb
Host smart-aa84753b-8693-4b56-bc0a-abdfe0a5a921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36570993781525549402363843160830164505345476091878227789523175080315542585504 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.36570993781525549402363843160830164505345476091878227789523175080315542585504 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.6002559826478676304969507072059265347499848732070406067316945270061846372013
Short name T107
Test name
Test status
Simulation time 46939868 ps
CPU time 1.14 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 215496 kb
Host smart-88e498b4-223a-4e20-847b-77ea45e7e70a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6002559826478676304969507072059265347499848732070406067316945270061846372013 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.60025598264786763049695070720592653474998487320704060673169452700618463
72013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.13259071814258712520885822790873746995801084115357210464492406255370136113772
Short name T13
Test name
Test status
Simulation time 96832326 ps
CPU time 1.82 seconds
Started Nov 22 01:49:51 PM PST 23
Finished Nov 22 01:49:54 PM PST 23
Peak memory 215948 kb
Host smart-dd6f2029-90e4-4736-9a73-3d5c339a51b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132590718142587125208858227908737469958010841153572104644924062553701
36113772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.132590718142587125208858227908737469958010841153
57210464492406255370136113772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.kmac_key_error.98129698707378605778803808774103100369819816961622163733840670021027194009751
Short name T58
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.65 seconds
Started Nov 22 01:52:38 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 207372 kb
Host smart-22bb3ebc-d691-4713-a7dc-09185349d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98129698707378605778803808774103100369819816961622163733840670021027194009751 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.kmac_key_error.98129698707378605778803808774103100369819816961622163733840670021027194009751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.56797868519550864933507735380502548610105833528105576728672370669423043315794
Short name T31
Test name
Test status
Simulation time 307766781661 ps
CPU time 4462.38 seconds
Started Nov 22 01:53:33 PM PST 23
Finished Nov 22 03:07:57 PM PST 23
Peak memory 653252 kb
Host smart-67c709bd-423a-4f10-9870-f9ae2b060a42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=56797868519550864933507735380502548610105833528105576728672370669423043315794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.kmac_test_vectors_shake_128.56797868519550864933507735380502548610105833528105576728672370669423043315794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_alert_test.80534804788683643151825414093298957762766614979874708915066932971176222705820
Short name T165
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:53:41 PM PST 23
Peak memory 205248 kb
Host smart-26bd3fa0-69f4-4aa6-95aa-5c2e3a3df932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80534804788683643151825414093298957762766614979874708915066932971176222705820 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.kmac_alert_test.80534804788683643151825414093298957762766614979874708915066932971176222705820 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.74301816748660479655717299189672043594826780909716287085135930105541595494487
Short name T201
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:53:15 PM PST 23
Finished Nov 22 01:53:21 PM PST 23
Peak memory 215732 kb
Host smart-dec4104e-3766-4827-a730-5fb4025532a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74301816748660479655717299189672043594826780909716287085135930105541595494487 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.kmac_lc_escalation.74301816748660479655717299189672043594826780909716287085135930105541595494487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.29048264146349358397529190007723503785358061066897416390094356566965626961193
Short name T43
Test name
Test status
Simulation time 7615861459 ps
CPU time 78.52 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:53:53 PM PST 23
Peak memory 225848 kb
Host smart-f98a39ae-5476-4534-b763-fe085eed56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29048264146349358397529190007723503785358061066897416390094356566965626961193 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_app_with_partial_data.29048264146349358397529190007723503785358061066897416390094356566965626961193 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.7452942932084553154073015884698939513207011953812977724998195291569681652207
Short name T117
Test name
Test status
Simulation time 14812750312 ps
CPU time 246.24 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 01:56:52 PM PST 23
Peak memory 225536 kb
Host smart-ced507d2-0876-4a4a-a368-3685f832d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7452942932084553154073015884698939513207011953812977724998195291569681652207 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.kmac_burst_write.7452942932084553154073015884698939513207011953812977724998195291569681652207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.97379922990104883554675569378041893957314076219319380073297778294253391742873
Short name T1111
Test name
Test status
Simulation time 403472730 ps
CPU time 5.57 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:31 PM PST 23
Peak memory 207324 kb
Host smart-79f04b61-e9d2-471a-aa85-91e3ad78a15e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97379922990104883554675569378041893957314076219319380073297778294253391742873 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.97379922990104883554675569378041893957314076219319380073297778294253391742873 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.8422045956493152606284959003962791247644239138106759523990774192561389823896
Short name T113
Test name
Test status
Simulation time 934950621 ps
CPU time 10.61 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 207244 kb
Host smart-3d4b7149-1212-4eba-9884-6c79f19d0a76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8422045956493152606284959003962791247644239138106759523990774192561389823896 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.8422045956493152606284959003962791247644239138106759523990774192561389823896 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2267720362939554676849994164791581834856300662379316057189184116682422613459
Short name T1123
Test name
Test status
Simulation time 29368580 ps
CPU time 0.91 seconds
Started Nov 22 01:49:20 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 207108 kb
Host smart-64efb23f-e037-4c7f-8b99-9b77bf239ed4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267720362939554676849994164791581834856300662379316057189184116682422613459 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2267720362939554676849994164791581834856300662379316057189184116682422613459 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.34348017750492534678471767548235051209089078828886152861985942068505435640138
Short name T1223
Test name
Test status
Simulation time 30368572 ps
CPU time 1.27 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 223648 kb
Host smart-d4ff4f97-dc6b-47ba-be67-8ba46500b8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434801775049253467847176754823505120908907
8828886152861985942068505435640138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3434801775049253467847176
7548235051209089078828886152861985942068505435640138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.90916081186080748988642010763862821799147087510500426451664841868330482853177
Short name T93
Test name
Test status
Simulation time 32814981 ps
CPU time 0.97 seconds
Started Nov 22 01:49:20 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 207196 kb
Host smart-3b8a6322-470c-4d30-a1bd-6bfea446782d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90916081186080748988642010763862821799147087510500426451664841868330482853177 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.90916081186080748988642010763862821799147087510500426451664841868330482853177 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.52594270384500821979468900484385299303411094900891887256342789102036828032306
Short name T102
Test name
Test status
Simulation time 46939868 ps
CPU time 1.22 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 215464 kb
Host smart-4cddc0dd-4322-401e-a68b-5bf14ba1289c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52594270384500821979468900484385299303411094900891887256342789102036828032306 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.5259427038450082197946890048438529930341109490089188725634278910203682
8032306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.15643498347541888159848693576787453388335994269971442969300492125832082018926
Short name T88
Test name
Test status
Simulation time 16922251 ps
CPU time 0.73 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:26 PM PST 23
Peak memory 207088 kb
Host smart-dbc6aa92-b186-4d63-8fdb-05d057471452
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643498347541888159848693576787453388335994269971442969300492125832082018926 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.15643498347541888159848693576787453388335994269971442969300492125832082018926 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.19136017763360001533543093834774164118597677501275845615084536342489703023410
Short name T1088
Test name
Test status
Simulation time 88046682 ps
CPU time 1.53 seconds
Started Nov 22 01:49:36 PM PST 23
Finished Nov 22 01:49:42 PM PST 23
Peak memory 215528 kb
Host smart-877eed12-918f-49fa-b916-77661b956460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19136017763360001533543093834774164118597677501275845615084536342489703023410
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.191360177633600015335430938347741641185976775012758456150845363424
89703023410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.17078248659069516987579401700376277929992695093029132434969149096772579658555
Short name T1178
Test name
Test status
Simulation time 38832790 ps
CPU time 0.95 seconds
Started Nov 22 01:49:34 PM PST 23
Finished Nov 22 01:49:40 PM PST 23
Peak memory 215648 kb
Host smart-0070fd6a-9cd3-43d5-884d-9036e2bfe360
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17078248659069516987579401700376277929992695093029132434969149096772579658555 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.170782486590695169875794017003762779299926950930291324349691490967725796
58555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.9932286231251421766214417156553823639184926178219130931465041312138392290346
Short name T1182
Test name
Test status
Simulation time 96832326 ps
CPU time 1.8 seconds
Started Nov 22 01:49:20 PM PST 23
Finished Nov 22 01:49:23 PM PST 23
Peak memory 215900 kb
Host smart-abe2f7f3-3936-4adf-8433-9e916738fd6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993228623125142176621441715655382363918492617821913093146504131213839
2290346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.9932286231251421766214417156553823639184926178219
130931465041312138392290346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.48392152047682390055481083555814898361085820055173110854612025493675482671597
Short name T1097
Test name
Test status
Simulation time 193117270 ps
CPU time 2.77 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 215468 kb
Host smart-7c3587f4-73e2-49a1-9730-d7259a053b40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48392152047682390055481083555814898361085820055173110854612025493675482671597 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.48392152047682390055481083555814898361085820055173110854612025493675482671597 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.93698700058888751057492605006804066094305513466819911230251728360167459384997
Short name T108
Test name
Test status
Simulation time 403472730 ps
CPU time 5.33 seconds
Started Nov 22 01:49:27 PM PST 23
Finished Nov 22 01:49:34 PM PST 23
Peak memory 207304 kb
Host smart-354298ef-deaf-4b64-928b-d574b613f079
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93698700058888751057492605006804066094305513466819911230251728360167459384997 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.93698700058888751057492605006804066094305513466819911230251728360167459384997 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.54918657925153012297664819419975322888286883814242949845625326718272204795735
Short name T92
Test name
Test status
Simulation time 934950621 ps
CPU time 9.76 seconds
Started Nov 22 01:49:25 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 207208 kb
Host smart-dd4de7d2-c825-4ab3-b4c2-2a5813f9fa12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54918657925153012297664819419975322888286883814242949845625326718272204795735 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.54918657925153012297664819419975322888286883814242949845625326718272204795735 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.70056193295656441044025378189102194208040373556410599890823258241022158594111
Short name T11
Test name
Test status
Simulation time 29368580 ps
CPU time 0.92 seconds
Started Nov 22 01:49:25 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 207096 kb
Host smart-c9a8c174-c846-41db-9c2f-b666c6cf5859
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70056193295656441044025378189102194208040373556410599890823258241022158594111 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.70056193295656441044025378189102194208040373556410599890823258241022158594111 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.29846418826442953587623421267455964449962792917380644511944788072364416190211
Short name T1233
Test name
Test status
Simulation time 30368572 ps
CPU time 1.22 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:35 PM PST 23
Peak memory 223528 kb
Host smart-ba980360-4b58-4f35-aec4-e1faa3742861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984641882644295358762342126745596444996279
2917380644511944788072364416190211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2984641882644295358762342
1267455964449962792917380644511944788072364416190211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.12410932429006685479814260478457077311591367684230102903748252947149233346151
Short name T1208
Test name
Test status
Simulation time 32814981 ps
CPU time 0.94 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:26 PM PST 23
Peak memory 207064 kb
Host smart-2026f238-c260-49ec-8a04-87376bac959f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12410932429006685479814260478457077311591367684230102903748252947149233346151 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.12410932429006685479814260478457077311591367684230102903748252947149233346151 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.10040152908404991338333907616273633696994187778863306757449261575012969085655
Short name T12
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:24 PM PST 23
Peak memory 207068 kb
Host smart-3a08701e-f8c9-4f4c-ad51-95a21e31a995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10040152908404991338333907616273633696994187778863306757449261575012969085655 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.10040152908404991338333907616273633696994187778863306757449261575012969085655 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.21497565870554100104818591821614030258724761183059571032039049068928135404755
Short name T111
Test name
Test status
Simulation time 46939868 ps
CPU time 1.16 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 215488 kb
Host smart-c5d0113b-754a-4f0d-81ec-24fc07d29cd5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21497565870554100104818591821614030258724761183059571032039049068928135404755 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2149756587055410010481859182161403025872476118305957103203904906892813
5404755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.14597317999792122482435933037386555526469875565477061597273144425138921505427
Short name T1161
Test name
Test status
Simulation time 16922251 ps
CPU time 0.71 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 207064 kb
Host smart-9d2b18ae-1182-4a80-b04e-f9d94a72e5e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14597317999792122482435933037386555526469875565477061597273144425138921505427 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.14597317999792122482435933037386555526469875565477061597273144425138921505427 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.27611123659770932272491377322690811513813489062039135076938540321879006897382
Short name T1181
Test name
Test status
Simulation time 88046682 ps
CPU time 1.54 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 215472 kb
Host smart-9187217c-8727-40ff-8861-0dbea0aae77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27611123659770932272491377322690811513813489062039135076938540321879006897382
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.276111236597709322724913773226908115138134890620391350769385403218
79006897382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.62456509195956889875216134343854667996690447682176797769946492565268296475077
Short name T1127
Test name
Test status
Simulation time 38832790 ps
CPU time 0.96 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 215692 kb
Host smart-ee1876ff-5979-4e74-905d-e92a5a859e8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62456509195956889875216134343854667996690447682176797769946492565268296475077 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.624565091959568898752161343438546679966904476821767977699464925652682964
75077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.60309624225795494990313748157279255368137276300870916694002143126785479966961
Short name T1237
Test name
Test status
Simulation time 96832326 ps
CPU time 1.73 seconds
Started Nov 22 01:49:43 PM PST 23
Finished Nov 22 01:49:46 PM PST 23
Peak memory 215888 kb
Host smart-eba8462f-69fb-46a3-bbdf-557de04693ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603096242257954949903137481572792553681372763008709166940021431267854
79966961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.603096242257954949903137481572792553681372763008
70916694002143126785479966961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.6875108310375318355133851646309905697153624911799781038885865720852374378145
Short name T1185
Test name
Test status
Simulation time 103242989 ps
CPU time 2.02 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 215544 kb
Host smart-24a33b7d-16e9-4da2-a63e-1e8d721741ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6875108310375318355133851646309905697153624911799781038885865720852374378145 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.kmac_tl_errors.6875108310375318355133851646309905697153624911799781038885865720852374378145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.48031617649656804315625784357312746483842996693668999292452719515863638468463
Short name T1220
Test name
Test status
Simulation time 193117270 ps
CPU time 2.81 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 215460 kb
Host smart-33604857-20f0-4d8d-b425-e1fb71206bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48031617649656804315625784357312746483842996693668999292452719515863638468463 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.48031617649656804315625784357312746483842996693668999292452719515863638468463 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.60368359678174185430629468488268091406431516004097337588208286945569162825959
Short name T1107
Test name
Test status
Simulation time 30368572 ps
CPU time 1.22 seconds
Started Nov 22 01:49:42 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 223628 kb
Host smart-d123fa5f-5315-4d98-95e7-0f9ecf35993c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6036835967817418543062946848826809140643151
6004097337588208286945569162825959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.603683596781741854306294
68488268091406431516004097337588208286945569162825959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.85536565569815481729475176716944610921248940723115707542839929139378640071419
Short name T1151
Test name
Test status
Simulation time 32814981 ps
CPU time 0.93 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:27 PM PST 23
Peak memory 207100 kb
Host smart-32d2f367-a5f1-4b44-99dc-0dd8974ff2f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85536565569815481729475176716944610921248940723115707542839929139378640071419 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.85536565569815481729475176716944610921248940723115707542839929139378640071419 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.95451289785710464426288382397035392533613483195746081825204719999415244266120
Short name T1234
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:31 PM PST 23
Peak memory 207172 kb
Host smart-72e121c3-470f-4525-8866-cde93ee4e11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95451289785710464426288382397035392533613483195746081825204719999415244266120 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.95451289785710464426288382397035392533613483195746081825204719999415244266120 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.50674621715809413494124526640242718660418932066890037935850037453695319105782
Short name T1099
Test name
Test status
Simulation time 88046682 ps
CPU time 1.59 seconds
Started Nov 22 01:49:53 PM PST 23
Finished Nov 22 01:49:56 PM PST 23
Peak memory 215596 kb
Host smart-cc231fc1-61f0-49a5-bd8c-7a6821d051f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50674621715809413494124526640242718660418932066890037935850037453695319105782
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.50674621715809413494124526640242718660418932066890037935850037453
695319105782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.79613428919191356995413805754827606075694049321873226024560929432871950418730
Short name T1150
Test name
Test status
Simulation time 38832790 ps
CPU time 0.94 seconds
Started Nov 22 01:49:45 PM PST 23
Finished Nov 22 01:49:47 PM PST 23
Peak memory 215720 kb
Host smart-216c9529-26cd-4ce9-9553-84aa18c9af77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79613428919191356995413805754827606075694049321873226024560929432871950418730 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.79613428919191356995413805754827606075694049321873226024560929432871950
418730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.19261575848120020042402903331108092596992788727850192981821822030944413669632
Short name T1158
Test name
Test status
Simulation time 96832326 ps
CPU time 1.75 seconds
Started Nov 22 01:49:47 PM PST 23
Finished Nov 22 01:49:50 PM PST 23
Peak memory 215876 kb
Host smart-b59c615c-983c-4223-ae86-fef29926fa1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192615758481200200424029033311080925969927887278501929818218220309444
13669632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.19261575848120020042402903331108092596992788727
850192981821822030944413669632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.96590180694988032258788880252633296040961885866253656753272973057825780127597
Short name T96
Test name
Test status
Simulation time 103242989 ps
CPU time 1.92 seconds
Started Nov 22 01:49:53 PM PST 23
Finished Nov 22 01:49:56 PM PST 23
Peak memory 215536 kb
Host smart-903d2c27-a173-48ec-a386-38a6ef7fd917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96590180694988032258788880252633296040961885866253656753272973057825780127597 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.96590180694988032258788880252633296040961885866253656753272973057825780127597 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2072351299243596064612745119591998023816817369356142019662423558010457787369
Short name T1155
Test name
Test status
Simulation time 193117270 ps
CPU time 2.93 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215452 kb
Host smart-453c0f47-d1ee-49f6-83d3-8510b22e4b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072351299243596064612745119591998023816817369356142019662423558010457787369 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2072351299243596064612745119591998023816817369356142019662423558010457787369 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.6089400978761205767602682259891769968221472838924344685703726206785025919901
Short name T106
Test name
Test status
Simulation time 30368572 ps
CPU time 1.24 seconds
Started Nov 22 01:49:45 PM PST 23
Finished Nov 22 01:49:47 PM PST 23
Peak memory 223628 kb
Host smart-40fa0978-a040-4b69-a50d-0bd2fa8f3280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6089400978761205767602682259891769968221472
838924344685703726206785025919901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.6089400978761205767602682
259891769968221472838924344685703726206785025919901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.61664093240373888605905540780110632438192962522523152496284249084617019122444
Short name T1222
Test name
Test status
Simulation time 32814981 ps
CPU time 0.95 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:09 PM PST 23
Peak memory 207116 kb
Host smart-55de2a55-ed27-4946-aed2-3d2addb218fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61664093240373888605905540780110632438192962522523152496284249084617019122444 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.61664093240373888605905540780110632438192962522523152496284249084617019122444 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.109443262123477699303164142371668452422340280368083444814911227675474906413576
Short name T1226
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 207024 kb
Host smart-120f2da6-ca53-49f6-8c81-14059df5c209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109443262123477699303164142371668452422340280368083444814911227675474906413576 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.109443262123477699303164142371668452422340280368083444814911227675474906413576 +enable_masking=0
+sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.68965720248584752667693470054660431448137998288510975021853782033143519035417
Short name T1095
Test name
Test status
Simulation time 88046682 ps
CPU time 1.61 seconds
Started Nov 22 01:49:45 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 215612 kb
Host smart-d331ba44-ec67-4b2d-9be5-307a08363daa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68965720248584752667693470054660431448137998288510975021853782033143519035417
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.68965720248584752667693470054660431448137998288510975021853782033
143519035417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.114014280125098115130294221817295262856053358395680963790359163777775992948257
Short name T1194
Test name
Test status
Simulation time 38832790 ps
CPU time 0.97 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 215664 kb
Host smart-f13003c2-7202-49ea-92a9-f4f7d7b96bcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114014280125098115130294221817295262856053358395680963790359163777775992948257 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1140142801250981151302942218172952628560533583956809637903591637777759
92948257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.32556705095041911839024204835839777887230953312689713749253417688092854264168
Short name T1165
Test name
Test status
Simulation time 96832326 ps
CPU time 1.7 seconds
Started Nov 22 01:49:37 PM PST 23
Finished Nov 22 01:49:43 PM PST 23
Peak memory 215880 kb
Host smart-f2a1069c-a0e7-474c-96b0-896d7aa059dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325567050950419118390242048358397778872309533126897137492534176880928
54264168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.32556705095041911839024204835839777887230953312
689713749253417688092854264168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.115481457885994488762994777454761087157666843052728174168331020100169969027184
Short name T94
Test name
Test status
Simulation time 103242989 ps
CPU time 1.95 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 215428 kb
Host smart-0082f4fd-be41-4963-b5a2-9efa8de458e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115481457885994488762994777454761087157666843052728174168331020100169969027184 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.115481457885994488762994777454761087157666843052728174168331020100169969027184 +enable_masking=0
+sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.100840535059793904765480374916703506152010952721226085242885250114000268482279
Short name T1159
Test name
Test status
Simulation time 193117270 ps
CPU time 2.81 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 215488 kb
Host smart-3e9f7af0-b174-4fb5-b588-cdf3a4ffba7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100840535059793904765480374916703506152010952721226085242885250114000268482279 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.100840535059793904765480374916703506152010952721226085242885250114000268482279 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.97064179553467664191692044348469086884625872381402357217632109462684862516822
Short name T1132
Test name
Test status
Simulation time 30368572 ps
CPU time 1.21 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 223656 kb
Host smart-e5b3dc2c-876a-42b8-83ba-1156eb84182e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9706417955346766419169204434846908688462587
2381402357217632109462684862516822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.970641795534676641916920
44348469086884625872381402357217632109462684862516822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.84711468349119573499656929316389765680947234890723724201399177791171956462017
Short name T1227
Test name
Test status
Simulation time 32814981 ps
CPU time 0.9 seconds
Started Nov 22 01:49:38 PM PST 23
Finished Nov 22 01:49:42 PM PST 23
Peak memory 207052 kb
Host smart-ea31db93-b5a8-491f-a582-b8e608a69b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84711468349119573499656929316389765680947234890723724201399177791171956462017 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.84711468349119573499656929316389765680947234890723724201399177791171956462017 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.7197014735271622952698232742611050496088195413325538912144259150990259824506
Short name T1219
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:49:53 PM PST 23
Finished Nov 22 01:49:54 PM PST 23
Peak memory 207132 kb
Host smart-5698dbf9-b798-4e17-a7ee-2dcade68ae93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7197014735271622952698232742611050496088195413325538912144259150990259824506 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.kmac_intr_test.7197014735271622952698232742611050496088195413325538912144259150990259824506 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.32142388147154938539820393012898356268523182756988810913404773056450258289403
Short name T1106
Test name
Test status
Simulation time 88046682 ps
CPU time 1.57 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 215360 kb
Host smart-950a5923-297a-4510-9a88-ebc79065c9c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32142388147154938539820393012898356268523182756988810913404773056450258289403
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.32142388147154938539820393012898356268523182756988810913404773056
450258289403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2955722262003898062882890708743387362618594555950920790393426685467121211047
Short name T1148
Test name
Test status
Simulation time 38832790 ps
CPU time 0.94 seconds
Started Nov 22 01:49:52 PM PST 23
Finished Nov 22 01:49:54 PM PST 23
Peak memory 215628 kb
Host smart-63d5b77e-33fc-4f83-acc2-fb78352e187e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955722262003898062882890708743387362618594555950920790393426685467121211047 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.295572226200389806288289070874338736261859455595092079039342668546712121
1047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.77101129982502590988892395496833483472158654690800924525126568597077822066361
Short name T1236
Test name
Test status
Simulation time 96832326 ps
CPU time 1.72 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 215876 kb
Host smart-08b94009-e550-42d9-86c3-b25de571adb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771011299825025909888923954968334834721586546908009245251265685970778
22066361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.77101129982502590988892395496833483472158654690
800924525126568597077822066361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.45375838554038700313517419224487948829272365801249515102937976357545688315621
Short name T7
Test name
Test status
Simulation time 103242989 ps
CPU time 1.93 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 215692 kb
Host smart-9dd358ee-dcba-4b64-90d1-f2484a74a027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45375838554038700313517419224487948829272365801249515102937976357545688315621 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.45375838554038700313517419224487948829272365801249515102937976357545688315621 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.80749107815471086230861382008342652416477441823314299768776456127463184367002
Short name T1119
Test name
Test status
Simulation time 193117270 ps
CPU time 2.87 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 215448 kb
Host smart-a513716f-c4cf-4d5d-a003-676bf2484f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80749107815471086230861382008342652416477441823314299768776456127463184367002 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.80749107815471086230861382008342652416477441823314299768776456127463184367002 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.77506546258123630819070402761077954380090394125381260452333629500749483089128
Short name T1126
Test name
Test status
Simulation time 30368572 ps
CPU time 1.21 seconds
Started Nov 22 01:49:54 PM PST 23
Finished Nov 22 01:49:56 PM PST 23
Peak memory 223668 kb
Host smart-68128bd1-0af7-40b8-97da-406374d8365e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7750654625812363081907040276107795438009039
4125381260452333629500749483089128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.775065462581236308190704
02761077954380090394125381260452333629500749483089128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.36043480846901462952180227076120456807018756606293036560297860362464678673683
Short name T1202
Test name
Test status
Simulation time 32814981 ps
CPU time 0.9 seconds
Started Nov 22 01:49:46 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 207064 kb
Host smart-4797f13f-7499-4a78-a9f8-fd5a7eb69a35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36043480846901462952180227076120456807018756606293036560297860362464678673683 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.36043480846901462952180227076120456807018756606293036560297860362464678673683 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.65839562872961894049581795471197509695517304904711418483293178466625485774475
Short name T1139
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:49:42 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 207116 kb
Host smart-441042fd-ed3e-4247-88ae-58278ac69afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65839562872961894049581795471197509695517304904711418483293178466625485774475 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.65839562872961894049581795471197509695517304904711418483293178466625485774475 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.23559447564629660975908085573803560675536684059575097731100651759639251423558
Short name T1133
Test name
Test status
Simulation time 88046682 ps
CPU time 1.54 seconds
Started Nov 22 01:49:42 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 215484 kb
Host smart-e8cf7931-bd28-468a-bacf-601118c531f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23559447564629660975908085573803560675536684059575097731100651759639251423558
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.23559447564629660975908085573803560675536684059575097731100651759
639251423558 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1181191540067302624421141888295222169452299388821962406479805638019282329517
Short name T1172
Test name
Test status
Simulation time 38832790 ps
CPU time 0.97 seconds
Started Nov 22 01:49:52 PM PST 23
Finished Nov 22 01:49:53 PM PST 23
Peak memory 215628 kb
Host smart-6fa0ce51-3b8f-40f0-9073-01698fe0e044
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181191540067302624421141888295222169452299388821962406479805638019282329517 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.118119154006730262442114188829522216945229938882196240647980563801928232
9517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.101387850728784882021775671806860144531249595130856477579677776049217233884571
Short name T1145
Test name
Test status
Simulation time 96832326 ps
CPU time 1.73 seconds
Started Nov 22 01:49:41 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 215896 kb
Host smart-676cd00a-f821-4a56-b185-f7546089bfe2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101387850728784882021775671806860144531249595130856477579677776049217
233884571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.1013878507287848820217756718068601445312495951
30856477579677776049217233884571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1426252361745159442903851333058245073347440850712373023998357759846636520731
Short name T1210
Test name
Test status
Simulation time 103242989 ps
CPU time 1.88 seconds
Started Nov 22 01:49:55 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 215536 kb
Host smart-18162c90-54aa-4f10-bb90-ece3c1de794e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426252361745159442903851333058245073347440850712373023998357759846636520731 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.kmac_tl_errors.1426252361745159442903851333058245073347440850712373023998357759846636520731 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.28800893875063884444097636547344438123910883571503827638184615730188962441181
Short name T1157
Test name
Test status
Simulation time 193117270 ps
CPU time 2.78 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:50:00 PM PST 23
Peak memory 215504 kb
Host smart-244f3f41-2382-4763-88f6-7c11b2cbd100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28800893875063884444097636547344438123910883571503827638184615730188962441181 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.28800893875063884444097636547344438123910883571503827638184615730188962441181 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.42839716268989509435525118751072733768337751187024183308032192537583155328758
Short name T1206
Test name
Test status
Simulation time 30368572 ps
CPU time 1.22 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 223432 kb
Host smart-de2edcf1-f505-4394-9383-1bcf1bc2d091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283971626898950943552511875107273376833775
1187024183308032192537583155328758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.428397162689895094355251
18751072733768337751187024183308032192537583155328758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.78252655393102441363278091827417624634851086338499995837620097954746058880101
Short name T19
Test name
Test status
Simulation time 32814981 ps
CPU time 0.9 seconds
Started Nov 22 01:49:44 PM PST 23
Finished Nov 22 01:49:46 PM PST 23
Peak memory 206892 kb
Host smart-0c3b9c77-a9a9-49a6-a200-98c48c733228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78252655393102441363278091827417624634851086338499995837620097954746058880101 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.78252655393102441363278091827417624634851086338499995837620097954746058880101 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.32914706173572461748294821250886100211896037634170027103550299263781900056405
Short name T1170
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:49:42 PM PST 23
Finished Nov 22 01:49:44 PM PST 23
Peak memory 207020 kb
Host smart-e9b9a994-4ae7-4fcc-8bab-f9a35498d550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914706173572461748294821250886100211896037634170027103550299263781900056405 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.32914706173572461748294821250886100211896037634170027103550299263781900056405 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.44064909497655139732999715062446143096402607969814409924368207819623328872487
Short name T1211
Test name
Test status
Simulation time 88046682 ps
CPU time 1.61 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 215504 kb
Host smart-cc94808c-4658-4ec6-a6f1-35b7414a4b99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44064909497655139732999715062446143096402607969814409924368207819623328872487
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.44064909497655139732999715062446143096402607969814409924368207819
623328872487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.6236651988624750406876675325089747748247394304759569042155707028307710026401
Short name T1195
Test name
Test status
Simulation time 38832790 ps
CPU time 0.97 seconds
Started Nov 22 01:49:54 PM PST 23
Finished Nov 22 01:49:56 PM PST 23
Peak memory 215676 kb
Host smart-ac04907e-03c3-4205-bc70-86fd88f134d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6236651988624750406876675325089747748247394304759569042155707028307710026401 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.623665198862475040687667532508974774824739430475956904215570702830771002
6401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.10031911208155612512744840543263469604132323440106608427532678722583412756605
Short name T123
Test name
Test status
Simulation time 96832326 ps
CPU time 1.74 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 215932 kb
Host smart-f0109031-84ea-47b0-a652-8665fee9628e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100319112081556125127448405432634696041323234401066084275326787225834
12756605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.10031911208155612512744840543263469604132323440
106608427532678722583412756605 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.43679516830782382158611173918122183303450822562562878096030747273077451038345
Short name T95
Test name
Test status
Simulation time 103242989 ps
CPU time 1.94 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 215472 kb
Host smart-f7bb9a30-125c-49bb-babb-e0f3980f51f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43679516830782382158611173918122183303450822562562878096030747273077451038345 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.43679516830782382158611173918122183303450822562562878096030747273077451038345 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.49467174771562790213988050134874819922520687312890357342295830619014120887070
Short name T1138
Test name
Test status
Simulation time 193117270 ps
CPU time 3 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215448 kb
Host smart-5b2c4150-1fcd-49de-ac30-0d19628b8657
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49467174771562790213988050134874819922520687312890357342295830619014120887070 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.49467174771562790213988050134874819922520687312890357342295830619014120887070 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.47983352560141534992454048308314882510748742507664577650627148100537851329906
Short name T1156
Test name
Test status
Simulation time 30368572 ps
CPU time 1.2 seconds
Started Nov 22 01:49:43 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 223688 kb
Host smart-3473c8f2-ba47-43f2-b641-d13a83fabfc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4798335256014153499245404830831488251074874
2507664577650627148100537851329906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.479833525601415349924540
48308314882510748742507664577650627148100537851329906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.84537608269065375058878767828525569843857876429523061747504556754502698802165
Short name T1197
Test name
Test status
Simulation time 32814981 ps
CPU time 0.92 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:05 PM PST 23
Peak memory 206892 kb
Host smart-de7630b2-8df7-4090-8f59-3a37ef73d157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84537608269065375058878767828525569843857876429523061747504556754502698802165 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.84537608269065375058878767828525569843857876429523061747504556754502698802165 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.59329782701112171842495516661176462934565059819449481175664821683571098652763
Short name T1130
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:49:52 PM PST 23
Finished Nov 22 01:49:53 PM PST 23
Peak memory 207032 kb
Host smart-c5aaf8fc-304e-41a1-aec4-10f5176ff532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59329782701112171842495516661176462934565059819449481175664821683571098652763 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.59329782701112171842495516661176462934565059819449481175664821683571098652763 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.72268871241636421612917277466210815715143070395613079850815862640214688176609
Short name T105
Test name
Test status
Simulation time 88046682 ps
CPU time 1.54 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:14 PM PST 23
Peak memory 215520 kb
Host smart-8fb0c76d-b25a-4061-846b-7f1f7f2cde6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72268871241636421612917277466210815715143070395613079850815862640214688176609
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.72268871241636421612917277466210815715143070395613079850815862640
214688176609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2700166237260764500764677981804207302024481752193447852975534942069392943767
Short name T1120
Test name
Test status
Simulation time 38832790 ps
CPU time 0.96 seconds
Started Nov 22 01:49:51 PM PST 23
Finished Nov 22 01:49:52 PM PST 23
Peak memory 215704 kb
Host smart-42d29527-46ee-4caa-a60c-5d5f5065fa3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700166237260764500764677981804207302024481752193447852975534942069392943767 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.270016623726076450076467798180420730202448175219344785297553494206939294
3767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.96701229981473396078472049006384652875885779011466175066531243673218020502885
Short name T1160
Test name
Test status
Simulation time 96832326 ps
CPU time 1.67 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 215716 kb
Host smart-3acc50ac-a16e-433d-91a7-805e16951a8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967012299814733960784720490063846528758857790114661750665312436732180
20502885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.96701229981473396078472049006384652875885779011
466175066531243673218020502885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.28346012722081743183324039638479801881691973651062609151707669369135236190919
Short name T1171
Test name
Test status
Simulation time 103242989 ps
CPU time 2 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:03 PM PST 23
Peak memory 215576 kb
Host smart-b34f11c7-a980-4a09-b328-8dc5e1e865eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28346012722081743183324039638479801881691973651062609151707669369135236190919 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.28346012722081743183324039638479801881691973651062609151707669369135236190919 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.32989413035819863523929055264289089809577542311348437206370211252436113063895
Short name T1085
Test name
Test status
Simulation time 30368572 ps
CPU time 1.27 seconds
Started Nov 22 01:49:55 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 223668 kb
Host smart-b7e5af5a-6714-4783-9d20-92146306f853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298941303581986352392905526428908980957754
2311348437206370211252436113063895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.329894130358198635239290
55264289089809577542311348437206370211252436113063895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.92109362016466869418373975562884087954039232975832072815986095302049832600643
Short name T98
Test name
Test status
Simulation time 32814981 ps
CPU time 0.94 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 207052 kb
Host smart-dac12937-285c-435a-86c2-39283d9adfa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92109362016466869418373975562884087954039232975832072815986095302049832600643 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.92109362016466869418373975562884087954039232975832072815986095302049832600643 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.58728256142700428481782691410717343961732995786945690881089211124220523361671
Short name T1193
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 207064 kb
Host smart-f43efec3-d2cf-479c-82a5-69ba29c85ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58728256142700428481782691410717343961732995786945690881089211124220523361671 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.58728256142700428481782691410717343961732995786945690881089211124220523361671 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.53231205151945923824364636180043500825310110766055544489389436252891343766282
Short name T1201
Test name
Test status
Simulation time 88046682 ps
CPU time 1.59 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:05 PM PST 23
Peak memory 215340 kb
Host smart-e99ce4a6-bf33-4747-a734-07ae3e25005a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53231205151945923824364636180043500825310110766055544489389436252891343766282
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.53231205151945923824364636180043500825310110766055544489389436252
891343766282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.38105303934830271486763098125795914383052210150390179602905215961458576293603
Short name T1144
Test name
Test status
Simulation time 38832790 ps
CPU time 0.94 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 215456 kb
Host smart-2ac093fd-12d5-4023-8ae4-f1b1d487c97e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38105303934830271486763098125795914383052210150390179602905215961458576293603 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.38105303934830271486763098125795914383052210150390179602905215961458576
293603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.30467669499349465534949685581926827653036023648231624802319204665854402141977
Short name T114
Test name
Test status
Simulation time 96832326 ps
CPU time 1.73 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215716 kb
Host smart-32d85a7c-0056-4201-8845-245593372f5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304676694993494655349496855819268276530360236482316248023192046658544
02141977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.30467669499349465534949685581926827653036023648
231624802319204665854402141977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.32673493736581160194539131000668922606388850629577088390632154886143744739976
Short name T1183
Test name
Test status
Simulation time 103242989 ps
CPU time 2.01 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215376 kb
Host smart-a8e03915-dfda-4150-8933-5606bf52256e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32673493736581160194539131000668922606388850629577088390632154886143744739976 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.32673493736581160194539131000668922606388850629577088390632154886143744739976 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.71840546733423387650685229779754687462022014457454508812985254318418020180730
Short name T1110
Test name
Test status
Simulation time 193117270 ps
CPU time 2.95 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:06 PM PST 23
Peak memory 215448 kb
Host smart-0d820287-add3-402c-971e-66fa29b32601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71840546733423387650685229779754687462022014457454508812985254318418020180730 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.71840546733423387650685229779754687462022014457454508812985254318418020180730 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.100499642183463223233793817619984524607818924055228631979446815743294456825566
Short name T1134
Test name
Test status
Simulation time 30368572 ps
CPU time 1.23 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 223608 kb
Host smart-1c435b35-58bc-4d49-a707-7b780daa7a7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004996421834632232337938176199845246078189
24055228631979446815743294456825566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.10049964218346322323379
3817619984524607818924055228631979446815743294456825566 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.25159917674364927070463428497625190793094911930719209963700123378610740983713
Short name T1224
Test name
Test status
Simulation time 32814981 ps
CPU time 0.9 seconds
Started Nov 22 01:49:46 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 207080 kb
Host smart-460f6986-63fa-496f-a440-aa5785401256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25159917674364927070463428497625190793094911930719209963700123378610740983713 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.25159917674364927070463428497625190793094911930719209963700123378610740983713 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.103507481281631344012945074049745534583331260343125126683996242957916253918483
Short name T1163
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:10 PM PST 23
Peak memory 207036 kb
Host smart-7600713c-f425-4c71-a218-1ce59793fb44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103507481281631344012945074049745534583331260343125126683996242957916253918483 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.103507481281631344012945074049745534583331260343125126683996242957916253918483 +enable_masking=0
+sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.6283781162589217702134614821274663738027253115847082819203839653180423278310
Short name T1141
Test name
Test status
Simulation time 88046682 ps
CPU time 1.57 seconds
Started Nov 22 01:50:06 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 215536 kb
Host smart-ab6305dc-8e8c-4a2c-b39d-87d1a0e9e90a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6283781162589217702134614821274663738027253115847082819203839653180423278310 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.628378116258921770213461482127466373802725311584708281920383965318
0423278310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.83236739259299933735615749086338125559328481576954773241280128388426688961091
Short name T1196
Test name
Test status
Simulation time 38832790 ps
CPU time 0.99 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215456 kb
Host smart-522b64b0-d0bc-4082-91d9-a9d7ef26ee0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83236739259299933735615749086338125559328481576954773241280128388426688961091 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.83236739259299933735615749086338125559328481576954773241280128388426688
961091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.8013723801549894815562166060033057747773843107971931342848616718103769658618
Short name T1240
Test name
Test status
Simulation time 96832326 ps
CPU time 1.69 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 215708 kb
Host smart-f3dcdcae-5951-4b71-86e9-32a4ff46866d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801372380154989481556216606003305774777384310797193134284861671810376
9658618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.801372380154989481556216606003305774777384310797
1931342848616718103769658618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.30843388028810848335865141011934987058920702730558554169938677479118626371925
Short name T8
Test name
Test status
Simulation time 103242989 ps
CPU time 1.95 seconds
Started Nov 22 01:49:55 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 215536 kb
Host smart-a41844b1-14fe-4bc1-bb72-d12adda594f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30843388028810848335865141011934987058920702730558554169938677479118626371925 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.30843388028810848335865141011934987058920702730558554169938677479118626371925 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.95809466804225067818464006886534819147131377386671392143050205091613552952214
Short name T1228
Test name
Test status
Simulation time 193117270 ps
CPU time 2.78 seconds
Started Nov 22 01:49:54 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 215460 kb
Host smart-6245880d-544e-41d6-809d-18184a7fa0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95809466804225067818464006886534819147131377386671392143050205091613552952214 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.95809466804225067818464006886534819147131377386671392143050205091613552952214 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.110809061891202280523637405118935336174165675626209593889455558146206615283405
Short name T1239
Test name
Test status
Simulation time 30368572 ps
CPU time 1.22 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:05 PM PST 23
Peak memory 223656 kb
Host smart-b6896b13-bccc-4fde-84ab-d16a07d8c1a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108090618912022805236374051189353361741656
75626209593889455558146206615283405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.11080906189120228052363
7405118935336174165675626209593889455558146206615283405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.71268765605591096671775592416735459363160591521071310661451355960451864790279
Short name T1135
Test name
Test status
Simulation time 32814981 ps
CPU time 0.98 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 207048 kb
Host smart-46b5257e-6a14-40f7-8f01-627fd7e7d7fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71268765605591096671775592416735459363160591521071310661451355960451864790279 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.71268765605591096671775592416735459363160591521071310661451355960451864790279 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.97038929350986417364511469070765291118214165684300004405665882889939729537156
Short name T1098
Test name
Test status
Simulation time 22940060 ps
CPU time 0.76 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 207056 kb
Host smart-745a8ffe-f832-4ddd-b882-b25efed95df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97038929350986417364511469070765291118214165684300004405665882889939729537156 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.97038929350986417364511469070765291118214165684300004405665882889939729537156 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.53810985492772604209649693094017725352752821162888075679730245947655836158765
Short name T1103
Test name
Test status
Simulation time 88046682 ps
CPU time 1.57 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 215500 kb
Host smart-5426a509-d62c-40e8-a914-0e27b26c40f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53810985492772604209649693094017725352752821162888075679730245947655836158765
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.53810985492772604209649693094017725352752821162888075679730245947
655836158765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.17895382927936179044978365459515723675604297802306536680425234221269150665995
Short name T1102
Test name
Test status
Simulation time 38832790 ps
CPU time 0.98 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 215676 kb
Host smart-57402695-7f86-470e-8d57-7a8eb731aa3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17895382927936179044978365459515723675604297802306536680425234221269150665995 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.17895382927936179044978365459515723675604297802306536680425234221269150
665995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.25310471662155194433748225656796056104376179042149399188814265354680214094787
Short name T1101
Test name
Test status
Simulation time 96832326 ps
CPU time 1.76 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:03 PM PST 23
Peak memory 215920 kb
Host smart-2f747a8c-d263-45c7-9f7b-24920b9de9fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253104716621551944337482256567960561043761790421493991888142653546802
14094787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.25310471662155194433748225656796056104376179042
149399188814265354680214094787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1166713290984052384632805330676352701968291229637414299978162240981055492236
Short name T1149
Test name
Test status
Simulation time 103242989 ps
CPU time 1.93 seconds
Started Nov 22 01:49:55 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 215524 kb
Host smart-3ccaea0a-3c50-480a-9adc-4d1b9e167d82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166713290984052384632805330676352701968291229637414299978162240981055492236 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.kmac_tl_errors.1166713290984052384632805330676352701968291229637414299978162240981055492236 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.111569184158046893622096827040928602853117123731188848192814206825577894107636
Short name T1175
Test name
Test status
Simulation time 193117270 ps
CPU time 2.99 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215452 kb
Host smart-53790142-9e85-40a9-9504-ee884fc11949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111569184158046893622096827040928602853117123731188848192814206825577894107636 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.111569184158046893622096827040928602853117123731188848192814206825577894107636 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.61704597534937014077283320199292398923465279565500996884009645408803404072096
Short name T90
Test name
Test status
Simulation time 30368572 ps
CPU time 1.2 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 223656 kb
Host smart-611f7674-57d1-4948-8c9e-c935458783d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6170459753493701407728332019929239892346527
9565500996884009645408803404072096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.617045975349370140772833
20199292398923465279565500996884009645408803404072096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.23264079039493723442829171145321178042013006088815328443936795669842350136827
Short name T1147
Test name
Test status
Simulation time 32814981 ps
CPU time 0.93 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:03 PM PST 23
Peak memory 207068 kb
Host smart-03ead2cd-d733-42fa-ad4f-e9192782c703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23264079039493723442829171145321178042013006088815328443936795669842350136827 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.23264079039493723442829171145321178042013006088815328443936795669842350136827 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.27019539434882928342064522801318858191274544851006101153243110093112845151380
Short name T18
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:06 PM PST 23
Peak memory 207076 kb
Host smart-9d42de09-e485-4faf-befd-6308a1add894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019539434882928342064522801318858191274544851006101153243110093112845151380 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.27019539434882928342064522801318858191274544851006101153243110093112845151380 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.15772828277938101745107771308360841573836993785634815089753202683388206066402
Short name T1167
Test name
Test status
Simulation time 88046682 ps
CPU time 1.59 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:08 PM PST 23
Peak memory 215516 kb
Host smart-b1c1dcef-9fe2-4db6-9278-35893a9b0e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15772828277938101745107771308360841573836993785634815089753202683388206066402
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.15772828277938101745107771308360841573836993785634815089753202683
388206066402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.101070908371461794420523645533134632457523129033101585581080372409689329701946
Short name T1142
Test name
Test status
Simulation time 38832790 ps
CPU time 0.98 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 215760 kb
Host smart-c54e6f17-a404-4616-b0f8-42b7321d9256
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101070908371461794420523645533134632457523129033101585581080372409689329701946 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.1010709083714617944205236455331346324575231290331015855810803724096893
29701946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.112978943195450595472836479658088034910001913260475711054993238699881425835789
Short name T1116
Test name
Test status
Simulation time 96832326 ps
CPU time 1.69 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 215800 kb
Host smart-f65bceaf-ccb8-479c-b928-59a6ec6c00b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112978943195450595472836479658088034910001913260475711054993238699881
425835789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.1129789431954505954728364796580880349100019132
60475711054993238699881425835789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.110280819131322523663236237822574829301645806973337207205911754094329989730687
Short name T1174
Test name
Test status
Simulation time 103242989 ps
CPU time 1.94 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 215556 kb
Host smart-1838b9f7-7479-4788-8c8e-a7abd6078107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110280819131322523663236237822574829301645806973337207205911754094329989730687 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.110280819131322523663236237822574829301645806973337207205911754094329989730687 +enable_masking=0
+sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.106313874733822653499990860727383040755388013215144816961795696168484787752386
Short name T1115
Test name
Test status
Simulation time 193117270 ps
CPU time 2.89 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:12 PM PST 23
Peak memory 215472 kb
Host smart-04aa1559-b7b4-4f9b-8c27-2d09ea4795a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106313874733822653499990860727383040755388013215144816961795696168484787752386 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.106313874733822653499990860727383040755388013215144816961795696168484787752386 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.77970088238060912312702770939242797683725072293769962625630453926683154356305
Short name T1190
Test name
Test status
Simulation time 403472730 ps
CPU time 5.32 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:40 PM PST 23
Peak memory 207284 kb
Host smart-7f52b443-3c22-45d1-9015-b28ee68c00bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77970088238060912312702770939242797683725072293769962625630453926683154356305 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.77970088238060912312702770939242797683725072293769962625630453926683154356305 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.7876785092235824700543516181808235451892448677194214432392447360040952266963
Short name T118
Test name
Test status
Simulation time 934950621 ps
CPU time 10.02 seconds
Started Nov 22 01:49:37 PM PST 23
Finished Nov 22 01:49:51 PM PST 23
Peak memory 207244 kb
Host smart-7e2375e6-0626-4abb-b150-7c84c9f4d166
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7876785092235824700543516181808235451892448677194214432392447360040952266963 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.7876785092235824700543516181808235451892448677194214432392447360040952266963 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.66144526676562141848019282138307825880126591176381183518400710534377644130069
Short name T1131
Test name
Test status
Simulation time 29368580 ps
CPU time 0.89 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 207096 kb
Host smart-6caa635f-b30b-4e27-8037-61ed6c1bbe33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66144526676562141848019282138307825880126591176381183518400710534377644130069 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.66144526676562141848019282138307825880126591176381183518400710534377644130069 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.23563314129206813843993915138626260279487435678759870537935085752441953684083
Short name T1209
Test name
Test status
Simulation time 30368572 ps
CPU time 1.25 seconds
Started Nov 22 01:49:34 PM PST 23
Finished Nov 22 01:49:40 PM PST 23
Peak memory 223656 kb
Host smart-5c8a60e4-ec23-41ed-97af-b756e17de061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356331412920681384399391513862626027948743
5678759870537935085752441953684083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2356331412920681384399391
5138626260279487435678759870537935085752441953684083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.39804637214097509954561659497190287796061120057298221562542481632178462440350
Short name T1129
Test name
Test status
Simulation time 32814981 ps
CPU time 0.91 seconds
Started Nov 22 01:49:40 PM PST 23
Finished Nov 22 01:49:43 PM PST 23
Peak memory 207020 kb
Host smart-66120706-15e3-4c24-b4ca-811b26d370e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804637214097509954561659497190287796061120057298221562542481632178462440350 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.39804637214097509954561659497190287796061120057298221562542481632178462440350 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.96466215180924130451244053813153237906161655587532424703273274305807521460795
Short name T85
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 206996 kb
Host smart-70d3cf81-21f6-4432-b764-cb2b3be3c499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96466215180924130451244053813153237906161655587532424703273274305807521460795 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.96466215180924130451244053813153237906161655587532424703273274305807521460795 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.111765173134503699609503638033518313407706433859210486030210106865000702137341
Short name T1231
Test name
Test status
Simulation time 16922251 ps
CPU time 0.69 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 207164 kb
Host smart-1308d4b4-23d9-4432-8482-3a529cc02be1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111765173134503699609503638033518313407706433859210486030210106865000702137341 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.111765173134503699609503638033518313407706433859210486030210106865000702137341 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3898107025509151167232465044125349107832054619922668404000204471124823236269
Short name T109
Test name
Test status
Simulation time 88046682 ps
CPU time 1.54 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:34 PM PST 23
Peak memory 215476 kb
Host smart-3b741237-f088-460b-9fe2-a1d0f37a64bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898107025509151167232465044125349107832054619922668404000204471124823236269 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3898107025509151167232465044125349107832054619922668404000204471124
823236269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.107627136720447470291962615248436607986704097369425614609725502402957869461644
Short name T1100
Test name
Test status
Simulation time 38832790 ps
CPU time 0.99 seconds
Started Nov 22 01:49:40 PM PST 23
Finished Nov 22 01:49:43 PM PST 23
Peak memory 215596 kb
Host smart-8d5a139c-ed9d-4145-bfe4-95e9f5dc7cde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107627136720447470291962615248436607986704097369425614609725502402957869461644 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.10762713672044747029196261524843660798670409736942561460972550240295786
9461644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.112944150956954432491623875141802372344128124538361851312697857168858686777134
Short name T1230
Test name
Test status
Simulation time 96832326 ps
CPU time 1.69 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 215896 kb
Host smart-25d3ed8a-f1e6-4dc4-9c54-10b9f77cfb6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112944150956954432491623875141802372344128124538361851312697857168858
686777134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.11294415095695443249162387514180237234412812453
8361851312697857168858686777134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.20486399892112338922471241297365984270579077370560581930992329720349996933268
Short name T6
Test name
Test status
Simulation time 103242989 ps
CPU time 1.92 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:34 PM PST 23
Peak memory 215652 kb
Host smart-dd128140-13c5-4c43-be9a-6ccfde62c992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486399892112338922471241297365984270579077370560581930992329720349996933268 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.20486399892112338922471241297365984270579077370560581930992329720349996933268 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.32625497947022309376205288694404488956955660308521262568882206754669044686509
Short name T10
Test name
Test status
Simulation time 193117270 ps
CPU time 2.78 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:39 PM PST 23
Peak memory 215384 kb
Host smart-d2620670-8a24-459d-9c32-4daa155c2671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32625497947022309376205288694404488956955660308521262568882206754669044686509 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.32625497947022309376205288694404488956955660308521262568882206754669044686509 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.56369133577548955341242257255368255881543109386038791232044408533547698250795
Short name T15
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 207088 kb
Host smart-28f9ce1b-973a-4e83-b619-0e6b88e7bf74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56369133577548955341242257255368255881543109386038791232044408533547698250795 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.56369133577548955341242257255368255881543109386038791232044408533547698250795 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.4253281032559884032066045254941724548457640054235829875979801786137683960282
Short name T1200
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:49:49 PM PST 23
Finished Nov 22 01:49:51 PM PST 23
Peak memory 207056 kb
Host smart-8131bbd9-29eb-4c84-a935-b22a778ccbfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253281032559884032066045254941724548457640054235829875979801786137683960282 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 21.kmac_intr_test.4253281032559884032066045254941724548457640054235829875979801786137683960282 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.60187247345092411571603379883716577647927008988586795374139228041596300973271
Short name T1105
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:14 PM PST 23
Peak memory 207076 kb
Host smart-8d60335f-eb8a-4894-b7e3-988bde92ae9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60187247345092411571603379883716577647927008988586795374139228041596300973271 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.60187247345092411571603379883716577647927008988586795374139228041596300973271 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.74249438155084050043979816223144202781949385021038546884821434715232596735553
Short name T1137
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:03 PM PST 23
Peak memory 207096 kb
Host smart-ecb17197-766b-4955-8eb9-590f736d9855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74249438155084050043979816223144202781949385021038546884821434715232596735553 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.74249438155084050043979816223144202781949385021038546884821434715232596735553 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.51744830231464873886433755832947824069430977661642163163463088448711316500176
Short name T1154
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 206996 kb
Host smart-2aa17b0b-2f63-45bd-80e6-122f3e12e9a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51744830231464873886433755832947824069430977661642163163463088448711316500176 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.51744830231464873886433755832947824069430977661642163163463088448711316500176 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.38064627485830728428193100315599751283215779789442292863802374641668746892017
Short name T83
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:10 PM PST 23
Finished Nov 22 01:50:18 PM PST 23
Peak memory 207056 kb
Host smart-21760605-dd45-4ff4-ae28-1e24f7150ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38064627485830728428193100315599751283215779789442292863802374641668746892017 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.38064627485830728428193100315599751283215779789442292863802374641668746892017 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.44381890889941909846164110133879884725442801004655929448742741841308591244774
Short name T1112
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:08 PM PST 23
Peak memory 207048 kb
Host smart-b9f2ae11-0c73-477b-95dd-7b0d319bb3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44381890889941909846164110133879884725442801004655929448742741841308591244774 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.44381890889941909846164110133879884725442801004655929448742741841308591244774 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.71695623168679488873665016746186106552788223637809210307321901424966147653740
Short name T1092
Test name
Test status
Simulation time 22940060 ps
CPU time 0.8 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 207064 kb
Host smart-993dad93-4e0c-44c8-ba01-b5f99ec044ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71695623168679488873665016746186106552788223637809210307321901424966147653740 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.71695623168679488873665016746186106552788223637809210307321901424966147653740 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.88565657425446427283385838321532566777948179722278116513627152445500434632693
Short name T1218
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 207076 kb
Host smart-9511ce14-092c-45ed-8ae0-b2bfdfa10e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88565657425446427283385838321532566777948179722278116513627152445500434632693 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.88565657425446427283385838321532566777948179722278116513627152445500434632693 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.28877983700123703211070974786487615980465907880610742046350426747856762665819
Short name T1229
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:09 PM PST 23
Peak memory 207048 kb
Host smart-383a04fe-259c-40cf-8d72-dcadf46c1587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28877983700123703211070974786487615980465907880610742046350426747856762665819 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.28877983700123703211070974786487615980465907880610742046350426747856762665819 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.25765678819904764647077870916181337153285103721033445626527061205212706820154
Short name T1108
Test name
Test status
Simulation time 403472730 ps
CPU time 5.38 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 207324 kb
Host smart-d279e5d2-0983-4818-9dd3-b36264c639c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25765678819904764647077870916181337153285103721033445626527061205212706820154 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.25765678819904764647077870916181337153285103721033445626527061205212706820154 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.79519420946638529507035804335763928863495257112487716003365373092183431690507
Short name T1166
Test name
Test status
Simulation time 934950621 ps
CPU time 9.91 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 207248 kb
Host smart-ed2b2a30-c612-446c-ac49-995ff85ad89d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79519420946638529507035804335763928863495257112487716003365373092183431690507 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.79519420946638529507035804335763928863495257112487716003365373092183431690507 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.115569773188172082113624546472562619707988276029105226899530990627908162893756
Short name T1205
Test name
Test status
Simulation time 29368580 ps
CPU time 0.9 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:38 PM PST 23
Peak memory 207092 kb
Host smart-ebb97c40-67e3-4366-a3bc-7575029522f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115569773188172082113624546472562619707988276029105226899530990627908162893756 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.115569773188172082113624546472562619707988276029105226899530990627908162893756 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.58369518983211067739566461763556843433240054143404867371457216035968976272506
Short name T86
Test name
Test status
Simulation time 30368572 ps
CPU time 1.23 seconds
Started Nov 22 01:49:42 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 223608 kb
Host smart-2f10141c-0b3d-4681-8504-8f072f5a6c7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5836951898321106773956646176355684343324005
4143404867371457216035968976272506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.5836951898321106773956646
1763556843433240054143404867371457216035968976272506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.33039816911913327233373259680985372119177006584822979510087484082677347359894
Short name T1180
Test name
Test status
Simulation time 32814981 ps
CPU time 0.94 seconds
Started Nov 22 01:49:44 PM PST 23
Finished Nov 22 01:49:47 PM PST 23
Peak memory 207076 kb
Host smart-15fbab0a-e651-4612-9eed-33b0416ca98b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33039816911913327233373259680985372119177006584822979510087484082677347359894 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.33039816911913327233373259680985372119177006584822979510087484082677347359894 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.80610167291956460871240771105254612793201447669722592182166820400987612842053
Short name T1081
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:35 PM PST 23
Peak memory 207016 kb
Host smart-7b772a64-d1b4-47eb-a2ac-c30cf77ebd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80610167291956460871240771105254612793201447669722592182166820400987612842053 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.80610167291956460871240771105254612793201447669722592182166820400987612842053 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.60078051299387277217956379259858721394229972780860946697897808495648562612914
Short name T103
Test name
Test status
Simulation time 46939868 ps
CPU time 1.16 seconds
Started Nov 22 01:49:19 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 215552 kb
Host smart-504ce72d-bc84-4485-a3fc-9b470358b056
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60078051299387277217956379259858721394229972780860946697897808495648562612914 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.6007805129938727721795637925985872139422997278086094669789780849564856
2612914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.17605276407509651070349993524885468193926889351492255557293110054904743016126
Short name T84
Test name
Test status
Simulation time 16922251 ps
CPU time 0.69 seconds
Started Nov 22 01:49:33 PM PST 23
Finished Nov 22 01:49:39 PM PST 23
Peak memory 207084 kb
Host smart-9c27a8f3-36ba-47ae-b587-68b284afe1e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17605276407509651070349993524885468193926889351492255557293110054904743016126 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.17605276407509651070349993524885468193926889351492255557293110054904743016126 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.14032109157251106026564814791723981182925714944595408053857760412559441446966
Short name T1225
Test name
Test status
Simulation time 88046682 ps
CPU time 1.62 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 215556 kb
Host smart-1b10da61-4220-43b1-859c-1f50fb44dc4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032109157251106026564814791723981182925714944595408053857760412559441446966
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.140321091572511060265648147917239811829257149445954080538577604125
59441446966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.87586550688896041240523327018530003182277908424690546141055847902823181708632
Short name T1125
Test name
Test status
Simulation time 38832790 ps
CPU time 0.96 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:26 PM PST 23
Peak memory 215692 kb
Host smart-ad1cd0d8-cd49-487b-a1a6-bc6620d9500e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87586550688896041240523327018530003182277908424690546141055847902823181708632 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.875865506888960412405233270185300031822779084246905461410558479028231817
08632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.97373988011090859004139424450757466651672186682586285315456471012281442218863
Short name T1184
Test name
Test status
Simulation time 96832326 ps
CPU time 1.7 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 215968 kb
Host smart-9cee29aa-70e4-4467-87f4-d1611e9700d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973739880110908590041394244507574666516721866825862853154564710122814
42218863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.973739880110908590041394244507574666516721866825
86285315456471012281442218863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.7794043631339445293600013528368684211551570937416780328147601349025411688135
Short name T1192
Test name
Test status
Simulation time 103242989 ps
CPU time 1.87 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:38 PM PST 23
Peak memory 215504 kb
Host smart-35c119af-10c2-4d50-ab39-cd66954b402b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7794043631339445293600013528368684211551570937416780328147601349025411688135 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.kmac_tl_errors.7794043631339445293600013528368684211551570937416780328147601349025411688135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.78848430976128640162987118575098267039257046338167440825303639165157026825784
Short name T1094
Test name
Test status
Simulation time 193117270 ps
CPU time 2.79 seconds
Started Nov 22 01:49:34 PM PST 23
Finished Nov 22 01:49:42 PM PST 23
Peak memory 215544 kb
Host smart-90d163d7-1cd5-4060-8658-66183559815d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78848430976128640162987118575098267039257046338167440825303639165157026825784 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.78848430976128640162987118575098267039257046338167440825303639165157026825784 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.104673044512941496682202726325353772489792293559903772500717105498451120491546
Short name T1087
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:50:09 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 206976 kb
Host smart-92c8bf45-8489-408b-8a17-62322fbc5e6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104673044512941496682202726325353772489792293559903772500717105498451120491546 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.104673044512941496682202726325353772489792293559903772500717105498451120491546 +enable_masking=0
+sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.79257129228716022138005491021819840328607184486425125233051050317868043005420
Short name T1082
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:50:09 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 207088 kb
Host smart-ea6d3852-dca2-420f-bf7d-da0a037c0efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79257129228716022138005491021819840328607184486425125233051050317868043005420 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.79257129228716022138005491021819840328607184486425125233051050317868043005420 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.107921580117730145612476441048213587673267237404600463842450613461376612668413
Short name T1191
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:00 PM PST 23
Peak memory 207024 kb
Host smart-703355bd-0f81-4eee-b259-16b2d2c62308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107921580117730145612476441048213587673267237404600463842450613461376612668413 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.107921580117730145612476441048213587673267237404600463842450613461376612668413 +enable_masking=0
+sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.54629069985911633144854284796503013456712290709398665161043253874917960601451
Short name T1114
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:13 PM PST 23
Peak memory 207056 kb
Host smart-4d5e9f7c-a489-4843-9b4f-e4f796565e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54629069985911633144854284796503013456712290709398665161043253874917960601451 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.54629069985911633144854284796503013456712290709398665161043253874917960601451 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.34569727555641236483706930823274319267077356284899049105231111504440064186910
Short name T1118
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:50:09 PM PST 23
Finished Nov 22 01:50:16 PM PST 23
Peak memory 207044 kb
Host smart-891ea25b-2a33-4d43-b85f-9c2125807888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569727555641236483706930823274319267077356284899049105231111504440064186910 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.34569727555641236483706930823274319267077356284899049105231111504440064186910 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.53390490914067891754217077527005977255166183600615183101037195610933787603393
Short name T1122
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 206972 kb
Host smart-00c12f48-2b5b-4db6-80d0-514a857b95b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53390490914067891754217077527005977255166183600615183101037195610933787603393 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.53390490914067891754217077527005977255166183600615183101037195610933787603393 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.67148882857935623076375890469388480877256078143166959908742477483547731562762
Short name T1207
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 207096 kb
Host smart-e099b711-1d76-4c38-93a1-a1a069a0095e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67148882857935623076375890469388480877256078143166959908742477483547731562762 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.67148882857935623076375890469388480877256078143166959908742477483547731562762 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.11235499599606449674831663240063428600776309745552807392425823543309098358832
Short name T112
Test name
Test status
Simulation time 22940060 ps
CPU time 0.71 seconds
Started Nov 22 01:50:07 PM PST 23
Finished Nov 22 01:50:14 PM PST 23
Peak memory 207100 kb
Host smart-f28def18-a821-4274-ac31-9d4d99cbd107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235499599606449674831663240063428600776309745552807392425823543309098358832 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.11235499599606449674831663240063428600776309745552807392425823543309098358832 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.41907131322977519567962260524390029115118557020758384940221899938209101435446
Short name T104
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:10 PM PST 23
Peak memory 207076 kb
Host smart-1a68fbcd-b8c1-465d-bbd7-514ed2f7dd47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41907131322977519567962260524390029115118557020758384940221899938209101435446 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.41907131322977519567962260524390029115118557020758384940221899938209101435446 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.59566580772087284596330393637311756408940013850808202012194435223809656276313
Short name T1093
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:50:03 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 207080 kb
Host smart-ef968775-de84-4036-b7e4-388f7f7abca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59566580772087284596330393637311756408940013850808202012194435223809656276313 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.59566580772087284596330393637311756408940013850808202012194435223809656276313 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.67823760003801410150669529379429410127673290917926996970392900402029641798655
Short name T1203
Test name
Test status
Simulation time 403472730 ps
CPU time 5.57 seconds
Started Nov 22 01:49:40 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 207376 kb
Host smart-239c0b35-8142-4677-8e50-bb3360495402
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67823760003801410150669529379429410127673290917926996970392900402029641798655 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.67823760003801410150669529379429410127673290917926996970392900402029641798655 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.107827881948413557103642746344767834924067568743268514682933692033282094209676
Short name T1113
Test name
Test status
Simulation time 934950621 ps
CPU time 10.04 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:43 PM PST 23
Peak memory 207180 kb
Host smart-042f2a59-5650-4c5c-8e85-12494374d5d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107827881948413557103642746344767834924067568743268514682933692033282094209676 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.107827881948413557103642746344767834924067568743268514682933692033282094209676 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.90200556285832581627231445461033572257920764566376294871100574763847077172937
Short name T14
Test name
Test status
Simulation time 29368580 ps
CPU time 0.92 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:38 PM PST 23
Peak memory 207224 kb
Host smart-74240dce-6827-40b0-94cf-374a519a201d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90200556285832581627231445461033572257920764566376294871100574763847077172937 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.90200556285832581627231445461033572257920764566376294871100574763847077172937 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.107411605474793522158194082159272904180814965593345240900645045539345933479190
Short name T1173
Test name
Test status
Simulation time 30368572 ps
CPU time 1.24 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:31 PM PST 23
Peak memory 223648 kb
Host smart-d2a64e50-37f7-4c05-892f-4a6f0e54cc15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074116054747935221581940821592729041808149
65593345240900645045539345933479190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.107411605474793522158194
082159272904180814965593345240900645045539345933479190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4046964244527069298068377562527821662067119397119656268003283162021909039517
Short name T1204
Test name
Test status
Simulation time 32814981 ps
CPU time 0.92 seconds
Started Nov 22 01:49:38 PM PST 23
Finished Nov 22 01:49:42 PM PST 23
Peak memory 207096 kb
Host smart-be0715d9-5af7-46a9-ba37-9b9e5f52dfc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046964244527069298068377562527821662067119397119656268003283162021909039517 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4046964244527069298068377562527821662067119397119656268003283162021909039517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.45908806682769341060431168212434699946991091917171944131439119924116509979790
Short name T1164
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:38 PM PST 23
Peak memory 207068 kb
Host smart-89fdb82a-432f-4ea7-99bb-faa266f9213a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45908806682769341060431168212434699946991091917171944131439119924116509979790 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.45908806682769341060431168212434699946991091917171944131439119924116509979790 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.37364855580912396881143325149888659062176079535424485852858205589570704482308
Short name T91
Test name
Test status
Simulation time 46939868 ps
CPU time 1.16 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:26 PM PST 23
Peak memory 215500 kb
Host smart-76c7af08-5472-4339-9a12-876dc1151775
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37364855580912396881143325149888659062176079535424485852858205589570704482308 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.3736485558091239688114332514988865906217607953542448585285820558957070
4482308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.72552442233919681361461700089487756518245365132496285812368505673085821943184
Short name T1169
Test name
Test status
Simulation time 16922251 ps
CPU time 0.68 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 207032 kb
Host smart-7d301566-32be-4209-933a-7034cb9263d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72552442233919681361461700089487756518245365132496285812368505673085821943184 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.72552442233919681361461700089487756518245365132496285812368505673085821943184 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.12719021217998311125054004075934023505704440783380115568930828624197236038547
Short name T1179
Test name
Test status
Simulation time 88046682 ps
CPU time 1.58 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:34 PM PST 23
Peak memory 215548 kb
Host smart-1f4597fa-ed0f-4fb0-88cf-223e87152201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12719021217998311125054004075934023505704440783380115568930828624197236038547
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.127190212179983111250540040759340235057044407833801155689308286241
97236038547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.104288024949550700137525366898412355679040256310708683771145092864874600960790
Short name T1091
Test name
Test status
Simulation time 38832790 ps
CPU time 0.99 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 215808 kb
Host smart-e01a1976-8545-48d3-9b87-d082b62f700e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104288024949550700137525366898412355679040256310708683771145092864874600960790 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.10428802494955070013752536689841235567904025631070868377114509286487460
0960790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.61404702350757081688418706762160992566336992884039489353560233887789821949700
Short name T1153
Test name
Test status
Simulation time 96832326 ps
CPU time 1.68 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 215996 kb
Host smart-ec1b358e-ae9d-461a-93a4-6bac622d599a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614047023507570816884187067621609925663369928840394893535602338877898
21949700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.614047023507570816884187067621609925663369928840
39489353560233887789821949700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.90466442707397955261586532461695483165690487577350263009259271772268793027381
Short name T97
Test name
Test status
Simulation time 103242989 ps
CPU time 1.94 seconds
Started Nov 22 01:49:53 PM PST 23
Finished Nov 22 01:49:56 PM PST 23
Peak memory 215568 kb
Host smart-a5f626f5-f1b2-4c80-a692-fb630242575f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90466442707397955261586532461695483165690487577350263009259271772268793027381 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.90466442707397955261586532461695483165690487577350263009259271772268793027381 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.48684059429637701419640973890872516964810519904064827096361555169585052619667
Short name T1221
Test name
Test status
Simulation time 193117270 ps
CPU time 2.8 seconds
Started Nov 22 01:49:48 PM PST 23
Finished Nov 22 01:49:52 PM PST 23
Peak memory 215440 kb
Host smart-a450b01d-83c7-4bb2-8d48-38b99e92fe18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48684059429637701419640973890872516964810519904064827096361555169585052619667 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.48684059429637701419640973890872516964810519904064827096361555169585052619667 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.79587888500949262825008953721247122360875369696100747168581257789016179760106
Short name T1109
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 207056 kb
Host smart-eee2f448-4eee-4c3e-9fba-06be6327f390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79587888500949262825008953721247122360875369696100747168581257789016179760106 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.79587888500949262825008953721247122360875369696100747168581257789016179760106 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.15726328165176472406585685299685031614459347559591353233281393077114320549840
Short name T1104
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:50:04 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 207076 kb
Host smart-6f6e6f98-e7a9-41ae-8b3c-560481fe4554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15726328165176472406585685299685031614459347559591353233281393077114320549840 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.15726328165176472406585685299685031614459347559591353233281393077114320549840 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.67396497262309690733978041735768656206763269250121056578153170817310320163793
Short name T1176
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:05 PM PST 23
Finished Nov 22 01:50:09 PM PST 23
Peak memory 207096 kb
Host smart-22bfcfd9-deb4-40a4-b517-4210e92e6fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67396497262309690733978041735768656206763269250121056578153170817310320163793 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.67396497262309690733978041735768656206763269250121056578153170817310320163793 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.86827849219470250761165943633613477760441146809534049145867221108841925431825
Short name T1213
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:12 PM PST 23
Finished Nov 22 01:50:18 PM PST 23
Peak memory 207080 kb
Host smart-e4071dd1-5834-4f32-a848-988fb915c293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86827849219470250761165943633613477760441146809534049145867221108841925431825 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.86827849219470250761165943633613477760441146809534049145867221108841925431825 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.86185915050463554723652023176854909317601294921917938970872527654829963911292
Short name T1117
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 207088 kb
Host smart-012b117e-17ee-4185-9ed6-00b92b5cda39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86185915050463554723652023176854909317601294921917938970872527654829963911292 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.86185915050463554723652023176854909317601294921917938970872527654829963911292 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.41654843852452479153952747388818154804230831967526540579996994376788055180285
Short name T1214
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:15 PM PST 23
Finished Nov 22 01:50:19 PM PST 23
Peak memory 207032 kb
Host smart-ab967584-edd8-45e4-852a-5f37a31ae38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41654843852452479153952747388818154804230831967526540579996994376788055180285 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.41654843852452479153952747388818154804230831967526540579996994376788055180285 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.111157997576048588616994378802398856193930448137888339379660974038745484557921
Short name T1128
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:15 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 207076 kb
Host smart-9385c1db-8855-4070-bce9-b20aeb7a8836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111157997576048588616994378802398856193930448137888339379660974038745484557921 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.111157997576048588616994378802398856193930448137888339379660974038745484557921 +enable_masking=0
+sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.77291687128356953706070132167151218178803941372320128681986979370387535959000
Short name T1084
Test name
Test status
Simulation time 22940060 ps
CPU time 0.75 seconds
Started Nov 22 01:50:08 PM PST 23
Finished Nov 22 01:50:15 PM PST 23
Peak memory 207076 kb
Host smart-bdab1724-350f-40ba-b288-b20eac2a1f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77291687128356953706070132167151218178803941372320128681986979370387535959000 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.77291687128356953706070132167151218178803941372320128681986979370387535959000 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.24946127021751506606564936947257613449040174617517127029015005272562153052987
Short name T1238
Test name
Test status
Simulation time 22940060 ps
CPU time 0.74 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 207076 kb
Host smart-b18444d6-f96a-4bc4-8930-4fad6d77cd23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946127021751506606564936947257613449040174617517127029015005272562153052987 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.24946127021751506606564936947257613449040174617517127029015005272562153052987 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.39750706018455388200676852885597247391938886820206737710359248706284247396547
Short name T1189
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:50:24 PM PST 23
Finished Nov 22 01:50:26 PM PST 23
Peak memory 207096 kb
Host smart-c693260e-8879-4629-be83-6d056130aaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39750706018455388200676852885597247391938886820206737710359248706284247396547 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.39750706018455388200676852885597247391938886820206737710359248706284247396547 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.38409431157405257493340634449651096872562499523118692377785133798499265308802
Short name T1136
Test name
Test status
Simulation time 30368572 ps
CPU time 1.27 seconds
Started Nov 22 01:49:49 PM PST 23
Finished Nov 22 01:49:51 PM PST 23
Peak memory 223624 kb
Host smart-290378cb-780c-44dd-acca-2758b48ec6e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840943115740525749334063444965109687256249
9523118692377785133798499265308802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3840943115740525749334063
4449651096872562499523118692377785133798499265308802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.58030150049249448087958397733516722213383441425426333791897386804427236741416
Short name T1232
Test name
Test status
Simulation time 32814981 ps
CPU time 0.98 seconds
Started Nov 22 01:49:35 PM PST 23
Finished Nov 22 01:49:41 PM PST 23
Peak memory 207112 kb
Host smart-4b10a7b8-ad60-44de-85c3-e0ac2b0160e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58030150049249448087958397733516722213383441425426333791897386804427236741416 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.58030150049249448087958397733516722213383441425426333791897386804427236741416 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.113956216397601209767971230325086479739957634537090322399941084434012758758993
Short name T89
Test name
Test status
Simulation time 22940060 ps
CPU time 0.76 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 207068 kb
Host smart-988e3c60-3920-4da4-b6a6-493066155541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113956216397601209767971230325086479739957634537090322399941084434012758758993 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.113956216397601209767971230325086479739957634537090322399941084434012758758993 +enable_masking=0
+sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.52856114348477328142009290368992630191537354679742967820404332228105121568377
Short name T1140
Test name
Test status
Simulation time 88046682 ps
CPU time 1.57 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:37 PM PST 23
Peak memory 215544 kb
Host smart-c438df9b-20cf-48aa-b2a2-b57f526bb8bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52856114348477328142009290368992630191537354679742967820404332228105121568377
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.528561143484773281420092903689926301915373546797429678204043322281
05121568377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.42304826401765563769648472648123444697422190617387264225087281447269049865393
Short name T1121
Test name
Test status
Simulation time 38832790 ps
CPU time 1.01 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 215720 kb
Host smart-37abde62-4fd3-432b-a2a8-e3d5624beb2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42304826401765563769648472648123444697422190617387264225087281447269049865393 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.423048264017655637696484726481234446974221906173872642250872814472690498
65393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2786008066908511586307905673687052107613126086020394811875351243345564719416
Short name T1187
Test name
Test status
Simulation time 96832326 ps
CPU time 1.72 seconds
Started Nov 22 01:49:35 PM PST 23
Finished Nov 22 01:49:41 PM PST 23
Peak memory 215948 kb
Host smart-c704e357-da69-4ce1-8f7f-44418faf4be9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278600806690851158630790567368705210761312608602039481187535124334556
4719416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.2786008066908511586307905673687052107613126086020
394811875351243345564719416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.113862600026031967645990856313809591027635979625554977927772045537673661492339
Short name T1215
Test name
Test status
Simulation time 103242989 ps
CPU time 1.91 seconds
Started Nov 22 01:49:44 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 215592 kb
Host smart-707df17e-47c7-467e-bed3-cd0b419734a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113862600026031967645990856313809591027635979625554977927772045537673661492339 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.113862600026031967645990856313809591027635979625554977927772045537673661492339 +enable_masking=0
+sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.71380171367784970818358156352624679486163750320986975693752765051565505477389
Short name T1177
Test name
Test status
Simulation time 193117270 ps
CPU time 2.78 seconds
Started Nov 22 01:49:33 PM PST 23
Finished Nov 22 01:49:41 PM PST 23
Peak memory 215544 kb
Host smart-c21a1709-bee0-469a-9265-fed45699f480
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71380171367784970818358156352624679486163750320986975693752765051565505477389 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.71380171367784970818358156352624679486163750320986975693752765051565505477389 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.108099934860248406095509921094275908374029211628310485865577513311665213841357
Short name T1096
Test name
Test status
Simulation time 30368572 ps
CPU time 1.27 seconds
Started Nov 22 01:49:35 PM PST 23
Finished Nov 22 01:49:41 PM PST 23
Peak memory 223628 kb
Host smart-3b9d9e4b-0041-48b6-881e-ef19238752b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080999348602484060955099210942759083740292
11628310485865577513311665213841357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.108099934860248406095509
921094275908374029211628310485865577513311665213841357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.15337774964724178423949943191346230934168237097651727073454067390450042329359
Short name T1124
Test name
Test status
Simulation time 32814981 ps
CPU time 0.92 seconds
Started Nov 22 01:49:37 PM PST 23
Finished Nov 22 01:49:42 PM PST 23
Peak memory 207044 kb
Host smart-83d33a43-f22a-4c15-a88f-24cecb1f6b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15337774964724178423949943191346230934168237097651727073454067390450042329359 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.15337774964724178423949943191346230934168237097651727073454067390450042329359 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.52100306574866245796901778804239819422811492708424564182562557403284368114092
Short name T1083
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:49:48 PM PST 23
Finished Nov 22 01:49:50 PM PST 23
Peak memory 206976 kb
Host smart-1aeb03b2-2fd0-42c9-8813-547adb1b2f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52100306574866245796901778804239819422811492708424564182562557403284368114092 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.52100306574866245796901778804239819422811492708424564182562557403284368114092 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.47146965081887127634707803463769900878333154202754217800143461249988247045108
Short name T1198
Test name
Test status
Simulation time 88046682 ps
CPU time 1.52 seconds
Started Nov 22 01:49:34 PM PST 23
Finished Nov 22 01:49:40 PM PST 23
Peak memory 215544 kb
Host smart-2b85beee-0d96-4520-aec2-bbd0f0660449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47146965081887127634707803463769900878333154202754217800143461249988247045108
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.471469650818871276347078034637699008783331542027542178001434612499
88247045108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.37951039699159083771181792951575752295543395271102034796406366210669916410298
Short name T99
Test name
Test status
Simulation time 38832790 ps
CPU time 0.99 seconds
Started Nov 22 01:49:52 PM PST 23
Finished Nov 22 01:49:54 PM PST 23
Peak memory 215596 kb
Host smart-19b12129-f3b3-4e9e-9dbd-7010102eb1e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37951039699159083771181792951575752295543395271102034796406366210669916410298 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.379510396991590837711817929515757522955433952711020347964063662106699164
10298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.64556421797145199955595270513584790464605232704040615283934767354751790201737
Short name T1216
Test name
Test status
Simulation time 96832326 ps
CPU time 1.7 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 215904 kb
Host smart-a03330d0-5dad-49a7-beca-e5d272985310
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645564217971451999555952705135847904646052327040406152839347673547517
90201737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.645564217971451999555952705135847904646052327040
40615283934767354751790201737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.30999751552743201061554671912403510993316762271936923635161373600726509201557
Short name T1235
Test name
Test status
Simulation time 103242989 ps
CPU time 1.97 seconds
Started Nov 22 01:49:46 PM PST 23
Finished Nov 22 01:49:53 PM PST 23
Peak memory 215564 kb
Host smart-c1c97f64-2ef0-47a2-ba24-14857da32108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30999751552743201061554671912403510993316762271936923635161373600726509201557 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.30999751552743201061554671912403510993316762271936923635161373600726509201557 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.55272104417585219121127157969434569974453924359821567646061697320446711614270
Short name T9
Test name
Test status
Simulation time 193117270 ps
CPU time 2.76 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:35 PM PST 23
Peak memory 215536 kb
Host smart-2a50d328-79f8-4978-afda-6471d9c32373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55272104417585219121127157969434569974453924359821567646061697320446711614270 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.55272104417585219121127157969434569974453924359821567646061697320446711614270 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.13478025545258715726775052037654816877707602338883251762155246916134785955572
Short name T16
Test name
Test status
Simulation time 30368572 ps
CPU time 1.26 seconds
Started Nov 22 01:49:42 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 223668 kb
Host smart-5b8ecbbe-865f-487e-b371-b30d5b6b6e0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347802554525871572677505203765481687770760
2338883251762155246916134785955572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1347802554525871572677505
2037654816877707602338883251762155246916134785955572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.60219881853755170076257136427874595450451836465916410464903737644418213190334
Short name T1186
Test name
Test status
Simulation time 32814981 ps
CPU time 0.94 seconds
Started Nov 22 01:50:00 PM PST 23
Finished Nov 22 01:50:03 PM PST 23
Peak memory 207072 kb
Host smart-aedd5968-723a-49eb-a025-cc130f4ab14a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60219881853755170076257136427874595450451836465916410464903737644418213190334 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.60219881853755170076257136427874595450451836465916410464903737644418213190334 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.32741131950296314854333264357874757214080866314030779609058549707443878210587
Short name T87
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:49:58 PM PST 23
Finished Nov 22 01:50:00 PM PST 23
Peak memory 207040 kb
Host smart-e9f60fc9-7546-42ba-a916-6b8d66d7fb49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32741131950296314854333264357874757214080866314030779609058549707443878210587 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.32741131950296314854333264357874757214080866314030779609058549707443878210587 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.112848248883957101235556997990590419747964168191864661618913787852113880896027
Short name T100
Test name
Test status
Simulation time 88046682 ps
CPU time 1.56 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 215472 kb
Host smart-e95e4e15-c5af-4cfc-9a89-dbdae3d16ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112848248883957101235556997990590419747964168191864661618913787852113880896027
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.11284824888395710123555699799059041974796416819186466161891378785
2113880896027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.41797675941339501857439107452987486393947828554354254199328003732863613840680
Short name T56
Test name
Test status
Simulation time 38832790 ps
CPU time 0.92 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:35 PM PST 23
Peak memory 215572 kb
Host smart-9adb3d7b-456b-40a7-a7d6-b83cfcea944e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41797675941339501857439107452987486393947828554354254199328003732863613840680 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.417976759413395018574391074529874863939478285543542541993280037328636138
40680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.85563251760430819534338981343547013338209167570006713194755056289713453018950
Short name T101
Test name
Test status
Simulation time 96832326 ps
CPU time 1.73 seconds
Started Nov 22 01:49:57 PM PST 23
Finished Nov 22 01:50:01 PM PST 23
Peak memory 215752 kb
Host smart-d996db78-b66f-4804-978d-6eb047d46683
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855632517604308195343389813435470133382091675700067131947550562897134
53018950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.855632517604308195343389813435470133382091675700
06713194755056289713453018950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.14839244763561481104138433247919472913657553187329431359365509708082469271141
Short name T4
Test name
Test status
Simulation time 103242989 ps
CPU time 1.97 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 215508 kb
Host smart-aad64cbd-cf8d-415a-b83e-20c46587d23f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14839244763561481104138433247919472913657553187329431359365509708082469271141 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.14839244763561481104138433247919472913657553187329431359365509708082469271141 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.8935196521699979172140137519123724491846293190709345796296401743941268640728
Short name T1199
Test name
Test status
Simulation time 193117270 ps
CPU time 2.79 seconds
Started Nov 22 01:49:48 PM PST 23
Finished Nov 22 01:49:52 PM PST 23
Peak memory 215504 kb
Host smart-e3997fe7-0753-40ef-9a10-bde64c1ebd7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8935196521699979172140137519123724491846293190709345796296401743941268640728 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.8935196521699979172140137519123724491846293190709345796296401743941268640728 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.31696243166037550259462961911306547213009476631929998574666072369812564318206
Short name T1086
Test name
Test status
Simulation time 30368572 ps
CPU time 1.26 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:59 PM PST 23
Peak memory 223616 kb
Host smart-36903d07-42ee-42ff-9b2c-759edd13d6f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169624316603755025946296191130654721300947
6631929998574666072369812564318206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3169624316603755025946296
1911306547213009476631929998574666072369812564318206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.114863873475768693353882763592839019749595304315791870897865416437648675874999
Short name T1168
Test name
Test status
Simulation time 32814981 ps
CPU time 0.93 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:38 PM PST 23
Peak memory 207104 kb
Host smart-cdd486b0-119b-41e1-8d15-feb4ff6c0ddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114863873475768693353882763592839019749595304315791870897865416437648675874999 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.114863873475768693353882763592839019749595304315791870897865416437648675874999 +enable_masking=0
+sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.59100081941093417619767722652828283015191768557533265927617163765995604842956
Short name T1143
Test name
Test status
Simulation time 22940060 ps
CPU time 0.72 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 207048 kb
Host smart-eb55e101-a9ab-4461-8c03-3490413c15a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59100081941093417619767722652828283015191768557533265927617163765995604842956 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.59100081941093417619767722652828283015191768557533265927617163765995604842956 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.71992410631988823849021249140094941470056255564713151376345657457757939220258
Short name T1212
Test name
Test status
Simulation time 88046682 ps
CPU time 1.57 seconds
Started Nov 22 01:49:55 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 215536 kb
Host smart-15f9ff92-5d6c-4064-8ef4-dd93a255a6bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71992410631988823849021249140094941470056255564713151376345657457757939220258
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.719924106319888238490212491400949414700562555647131513763456574577
57939220258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.22508268829177866394920353273041030629564129723218277232345633468530683550958
Short name T1080
Test name
Test status
Simulation time 38832790 ps
CPU time 0.97 seconds
Started Nov 22 01:49:59 PM PST 23
Finished Nov 22 01:50:02 PM PST 23
Peak memory 215576 kb
Host smart-f7ebcbc4-6ae3-4ac2-bf50-6025da02f463
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22508268829177866394920353273041030629564129723218277232345633468530683550958 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.225082688291778663949203532730410306295641297232182772323456334685306835
50958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.46367353529907045680389057192987990598294226804110378999145862571470343103615
Short name T1162
Test name
Test status
Simulation time 96832326 ps
CPU time 1.75 seconds
Started Nov 22 01:50:02 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215900 kb
Host smart-57c47a62-88f7-4f6b-8edd-756569b8d6fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463673535299070456803890571929879905982942268041103789991458625714703
43103615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.463673535299070456803890571929879905982942268041
10378999145862571470343103615 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.82873054789414157297926229062482721941000539480255781089628780030710673836598
Short name T1188
Test name
Test status
Simulation time 103242989 ps
CPU time 1.95 seconds
Started Nov 22 01:49:50 PM PST 23
Finished Nov 22 01:49:53 PM PST 23
Peak memory 215472 kb
Host smart-9068dda4-7f32-47a0-a6df-a0ce2ead4681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82873054789414157297926229062482721941000539480255781089628780030710673836598 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.82873054789414157297926229062482721941000539480255781089628780030710673836598 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.37538458643038181827384459654712187202523483240883713880352139933215085891940
Short name T3
Test name
Test status
Simulation time 193117270 ps
CPU time 2.91 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:07 PM PST 23
Peak memory 215604 kb
Host smart-effb8e6c-1fea-4e73-9d6b-d29e2f212759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37538458643038181827384459654712187202523483240883713880352139933215085891940 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.37538458643038181827384459654712187202523483240883713880352139933215085891940 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.67001377758284327894003781579520681671366841038054251381663273484643213002458
Short name T1089
Test name
Test status
Simulation time 30368572 ps
CPU time 1.17 seconds
Started Nov 22 01:49:46 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 223668 kb
Host smart-0a05c2a9-b198-44aa-8ed5-5875f7793093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6700137775828432789400378157952068167136684
1038054251381663273484643213002458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.6700137775828432789400378
1579520681671366841038054251381663273484643213002458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.15475066004251051504585975586345128178190988935100843292653595558630340521660
Short name T1146
Test name
Test status
Simulation time 32814981 ps
CPU time 0.9 seconds
Started Nov 22 01:49:47 PM PST 23
Finished Nov 22 01:49:49 PM PST 23
Peak memory 207060 kb
Host smart-c1667a60-9d38-4576-bc06-9d03238fae7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475066004251051504585975586345128178190988935100843292653595558630340521660 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.15475066004251051504585975586345128178190988935100843292653595558630340521660 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.9564002824850357602259539125898242011573794751079816952245890245301377400039
Short name T110
Test name
Test status
Simulation time 22940060 ps
CPU time 0.73 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:04 PM PST 23
Peak memory 207000 kb
Host smart-100f1944-3387-4a3b-9b3e-23761280d56d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9564002824850357602259539125898242011573794751079816952245890245301377400039 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.kmac_intr_test.9564002824850357602259539125898242011573794751079816952245890245301377400039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.104161235508609437232016333313752951425640445919779211555620156373836192789040
Short name T1217
Test name
Test status
Simulation time 88046682 ps
CPU time 1.52 seconds
Started Nov 22 01:49:50 PM PST 23
Finished Nov 22 01:49:52 PM PST 23
Peak memory 215480 kb
Host smart-92e301d2-532f-4c64-b3c2-72f126d2fad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104161235508609437232016333313752951425640445919779211555620156373836192789040
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.10416123550860943723201633331375295142564044591977921155562015637
3836192789040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.107156363365419058293158438905819366524942508195934044360514299360615913410855
Short name T1090
Test name
Test status
Simulation time 38832790 ps
CPU time 0.97 seconds
Started Nov 22 01:49:56 PM PST 23
Finished Nov 22 01:49:58 PM PST 23
Peak memory 215628 kb
Host smart-fc3d5dcd-aa70-4867-a714-a9b407f93080
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107156363365419058293158438905819366524942508195934044360514299360615913410855 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.10715636336541905829315843890581936652494250819593404436051429936061591
3410855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.32215105132877909690007522422671729847580996592989739614361328476353393404283
Short name T5
Test name
Test status
Simulation time 103242989 ps
CPU time 1.94 seconds
Started Nov 22 01:49:53 PM PST 23
Finished Nov 22 01:49:56 PM PST 23
Peak memory 215564 kb
Host smart-eff606a5-6c24-4b0e-aeaf-86c0968f99e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32215105132877909690007522422671729847580996592989739614361328476353393404283 -assert nopostproc +U
VM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.32215105132877909690007522422671729847580996592989739614361328476353393404283 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.69218112320662664960213486465779571746771439395858378739305309213952018804938
Short name T1152
Test name
Test status
Simulation time 193117270 ps
CPU time 2.86 seconds
Started Nov 22 01:49:48 PM PST 23
Finished Nov 22 01:49:52 PM PST 23
Peak memory 215460 kb
Host smart-ead48d05-a34f-46f4-aa31-9007c2c637d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69218112320662664960213486465779571746771439395858378739305309213952018804938 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.69218112320662664960213486465779571746771439395858378739305309213952018804938 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.58591086543856416328951677522265109539406882001671725585344858302413252511651
Short name T998
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:52:37 PM PST 23
Peak memory 205220 kb
Host smart-e604d2ea-6a53-422e-b876-fcf6c88ab37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58591086543856416328951677522265109539406882001671725585344858302413252511651 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.kmac_alert_test.58591086543856416328951677522265109539406882001671725585344858302413252511651 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.2156103871926653227631028259074089816357315300120618300001459524963212120249
Short name T973
Test name
Test status
Simulation time 5659537824 ps
CPU time 75.83 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:53:55 PM PST 23
Peak memory 227280 kb
Host smart-f4634b90-9c74-4c52-b44e-ee49176561c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156103871926653227631028259074089816357315300120618300001459524963212120249 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.kmac_app.2156103871926653227631028259074089816357315300120618300001459524963212120249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_burst_write.102352750791889973298564676271137036727425700071427109736022159474566941634795
Short name T767
Test name
Test status
Simulation time 14812750312 ps
CPU time 245.11 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 01:56:48 PM PST 23
Peak memory 225452 kb
Host smart-1c597b71-d6e5-4c57-a155-9b773aa31b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102352750791889973298564676271137036727425700071427109736022159474566941634795 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.kmac_burst_write.102352750791889973298564676271137036727425700071427109736022159474566941634795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.342407063806428862460208848421373892141481554947052588705898835200065756225
Short name T300
Test name
Test status
Simulation time 2342046507 ps
CPU time 33.32 seconds
Started Nov 22 01:52:20 PM PST 23
Finished Nov 22 01:52:56 PM PST 23
Peak memory 223856 kb
Host smart-69416006-3b51-484c-9b3d-b0d0a522eac3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=342407063806428862460208848421373892141481554947052588705898835200065756225 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.kmac_edn_timeout_error.342407063806428862460208848421373892141481554947052588705898835200065756225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.43393416927696275044752049383635733645957931013061863900650454252853022031901
Short name T703
Test name
Test status
Simulation time 2211297553 ps
CPU time 28.97 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:53:15 PM PST 23
Peak memory 223812 kb
Host smart-eadc7db0-efc6-45a0-9c77-87954d42f442
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=43393416927696275044752049383635733645957931013061863900650454252853022031901 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.43393416927696275044752049383635733645957931013061863900650454252853022031901 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.57187824289445659759811786317435828219942422093584094024379012440141179760460
Short name T840
Test name
Test status
Simulation time 2782989408 ps
CPU time 17.9 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:52:40 PM PST 23
Peak memory 216888 kb
Host smart-390dbcb6-e228-4d63-ba01-90d22849ae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57187824289445659759811786317435828219942422093584094024379012440141179760460 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.kmac_entropy_ready_error.57187824289445659759811786317435828219942422093584094024379012440141179760460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.34144682559862245256146417206932740010618932415626749621862829259497705084544
Short name T987
Test name
Test status
Simulation time 6743332725 ps
CPU time 71.67 seconds
Started Nov 22 01:52:26 PM PST 23
Finished Nov 22 01:53:44 PM PST 23
Peak memory 227000 kb
Host smart-4d6ac207-3cee-4cfb-a166-09c805f0f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34144682559862245256146417206932740010618932415626749621862829259497705084544 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.kmac_entropy_refresh.34144682559862245256146417206932740010618932415626749621862829259497705084544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.42828657018949007220272650659001214067438326027365642140587949883142327946841
Short name T424
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 01:52:47 PM PST 23
Peak memory 215740 kb
Host smart-1c8ad673-0216-413f-8725-20e8bb0a3bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42828657018949007220272650659001214067438326027365642140587949883142327946841 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.kmac_lc_escalation.42828657018949007220272650659001214067438326027365642140587949883142327946841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.84138963801129327878189594485630221208593305874304455998969370424404000691515
Short name T556
Test name
Test status
Simulation time 45517522529 ps
CPU time 698.89 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 02:04:04 PM PST 23
Peak memory 288284 kb
Host smart-b5eb2151-07b0-429b-a9ae-3a931cb75649
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84138963801129327878189594485630221208593305874304455998969370424404000691515 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.8413896380112932787818959448563022120859330587430445599896937042440400
0691515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.111075784667623329715486138647647474546033791925898419852146181095809206438578
Short name T535
Test name
Test status
Simulation time 5640716546 ps
CPU time 73.67 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 01:53:31 PM PST 23
Peak memory 227736 kb
Host smart-3b141273-14eb-4d0b-926d-6476e8772074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111075784667623329715486138647647474546033791925898419852146181095809206438578 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.kmac_mubi.111075784667623329715486138647647474546033791925898419852146181095809206438578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.70578573142271916360590524248017321313151869760085372477410887364538711436858
Short name T69
Test name
Test status
Simulation time 4127675079 ps
CPU time 32.61 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 01:52:58 PM PST 23
Peak memory 249024 kb
Host smart-5cb1e315-daf1-4ab2-9f3c-27d2910e69bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70578573142271916360590524248017321313151869760085372477410887364538711436858 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.kmac_sec_cm.70578573142271916360590524248017321313151869760085372477410887364538711436858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.55195913814531525461307521829049017225254229245145584674064669359458562471079
Short name T237
Test name
Test status
Simulation time 7733092664 ps
CPU time 115.22 seconds
Started Nov 22 01:52:26 PM PST 23
Finished Nov 22 01:54:27 PM PST 23
Peak memory 228128 kb
Host smart-30809c9a-d68f-421c-9e36-334f36fda63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55195913814531525461307521829049017225254229245145584674064669359458562471079 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.kmac_sideload.55195913814531525461307521829049017225254229245145584674064669359458562471079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.44978801068539676837422863606073898373975079014884565064467908699749663470524
Short name T235
Test name
Test status
Simulation time 1554463522 ps
CPU time 19.22 seconds
Started Nov 22 01:52:31 PM PST 23
Finished Nov 22 01:52:54 PM PST 23
Peak memory 215896 kb
Host smart-93d30720-da56-4a90-9bd3-5ab855dec2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44978801068539676837422863606073898373975079014884565064467908699749663470524 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.kmac_smoke.44978801068539676837422863606073898373975079014884565064467908699749663470524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.49007203967901366231200534692311072930046148212637449194076006530571708741903
Short name T420
Test name
Test status
Simulation time 41434001626 ps
CPU time 618.02 seconds
Started Nov 22 01:52:21 PM PST 23
Finished Nov 22 02:02:41 PM PST 23
Peak memory 321720 kb
Host smart-7b310952-9d42-4b58-a03e-b3f6252647f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=49007203967901366231200534692311072930046148212637449194076006530571708741903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_str
ess_all.49007203967901366231200534692311072930046148212637449194076006530571708741903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.106354318620007691557380094931129552814637475416546959116795540231056580308254
Short name T568
Test name
Test status
Simulation time 298812853 ps
CPU time 4.36 seconds
Started Nov 22 01:52:21 PM PST 23
Finished Nov 22 01:52:27 PM PST 23
Peak memory 215824 kb
Host smart-f22ea696-c020-4f5b-acf6-1d8cb083d2dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10635431862000769155738009493112955281463747541654695
9116795540231056580308254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.10635431862000769155738009493112955281
4637475416546959116795540231056580308254 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.92972458327987794612245691480482818717768678586974901857377177993765084832848
Short name T586
Test name
Test status
Simulation time 289902210 ps
CPU time 4.16 seconds
Started Nov 22 01:52:18 PM PST 23
Finished Nov 22 01:52:26 PM PST 23
Peak memory 215808 kb
Host smart-fdeb41e2-f939-4b4c-8a09-bf2cd721ac53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92972458327987794612245691480482818717768678586974901
857377177993765084832848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.9297245832798779461224569148048
2818717768678586974901857377177993765084832848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.38755416008205026017730131374779796556932905847125267693073859827111693788353
Short name T70
Test name
Test status
Simulation time 115269125226 ps
CPU time 1749.36 seconds
Started Nov 22 01:52:12 PM PST 23
Finished Nov 22 02:21:24 PM PST 23
Peak memory 390448 kb
Host smart-3bd9c220-241f-4bb2-8b1f-519295765beb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38755416008205026017730131374779796556932905847125267693073859827111693788353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
kmac_test_vectors_sha3_224.38755416008205026017730131374779796556932905847125267693073859827111693788353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.38468004523174505345383533497611086778364734374087012786269091352590870602916
Short name T208
Test name
Test status
Simulation time 107886220004 ps
CPU time 1631.6 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 02:19:33 PM PST 23
Peak memory 370100 kb
Host smart-2e7cc429-2d10-4bde-80af-bc0f4e6764a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38468004523174505345383533497611086778364734374087012786269091352590870602916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
kmac_test_vectors_sha3_256.38468004523174505345383533497611086778364734374087012786269091352590870602916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.30647465290751273590519832243763081838680276851968604169214312159402729890756
Short name T528
Test name
Test status
Simulation time 83070954242 ps
CPU time 1247.6 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 02:13:33 PM PST 23
Peak memory 332904 kb
Host smart-a4c9017b-eb23-4bf4-a09f-d6b5c78cc197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30647465290751273590519832243763081838680276851968604169214312159402729890756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
kmac_test_vectors_sha3_384.30647465290751273590519832243763081838680276851968604169214312159402729890756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.75632856362413866038974457580527248050027521458772817669613345519573132581957
Short name T1071
Test name
Test status
Simulation time 58503507926 ps
CPU time 882.27 seconds
Started Nov 22 01:52:39 PM PST 23
Finished Nov 22 02:07:27 PM PST 23
Peak memory 295892 kb
Host smart-1b47a888-2260-4cd7-88c8-e0470f1ee929
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=75632856362413866038974457580527248050027521458772817669613345519573132581957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
kmac_test_vectors_sha3_512.75632856362413866038974457580527248050027521458772817669613345519573132581957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.17871937101333501473220221969449716967983296966023166697822780982680926739943
Short name T1050
Test name
Test status
Simulation time 307766781661 ps
CPU time 4687.38 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 03:10:34 PM PST 23
Peak memory 653236 kb
Host smart-6b594cce-7f0c-4f43-8822-e6fce0e6b0fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=17871937101333501473220221969449716967983296966023166697822780982680926739943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.kmac_test_vectors_shake_128.17871937101333501473220221969449716967983296966023166697822780982680926739943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.102188571400320920922079368669291257333276652822800724473270136392457556493846
Short name T545
Test name
Test status
Simulation time 258047411562 ps
CPU time 3829.55 seconds
Started Nov 22 01:52:38 PM PST 23
Finished Nov 22 02:56:34 PM PST 23
Peak memory 556160 kb
Host smart-a4148b9a-aab8-40f9-81a9-3a54b70734b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=102188571400320920922079368669291257333276652822800724473270136392457556493846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.kmac_test_vectors_shake_256.102188571400320920922079368669291257333276652822800724473270136392457556493846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.20306239163968911955892930115805876799050633567356796698121904453093264196820
Short name T357
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 01:52:44 PM PST 23
Peak memory 205332 kb
Host smart-3bc19de5-bf10-4443-974f-0594760c83a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306239163968911955892930115805876799050633567356796698121904453093264196820 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.kmac_alert_test.20306239163968911955892930115805876799050633567356796698121904453093264196820 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.94566680281532865777253403701959819609674338856432440390799429269925007986226
Short name T643
Test name
Test status
Simulation time 5659537824 ps
CPU time 78.59 seconds
Started Nov 22 01:52:14 PM PST 23
Finished Nov 22 01:53:35 PM PST 23
Peak memory 227372 kb
Host smart-e4a8afa5-2b1d-4efd-80bd-faa459f9a9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94566680281532865777253403701959819609674338856432440390799429269925007986226 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.kmac_app.94566680281532865777253403701959819609674338856432440390799429269925007986226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.26333999441025253475947196815508802941406020482716860326707441144950538787460
Short name T1027
Test name
Test status
Simulation time 7615861459 ps
CPU time 82.82 seconds
Started Nov 22 01:52:26 PM PST 23
Finished Nov 22 01:53:54 PM PST 23
Peak memory 225940 kb
Host smart-387d6c89-a428-46c0-8ba4-b744195a503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26333999441025253475947196815508802941406020482716860326707441144950538787460 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_app_with_partial_data.26333999441025253475947196815508802941406020482716860326707441144950538787460 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.4891609749561316442178170258702041471949729218586848474061033088564659642956
Short name T205
Test name
Test status
Simulation time 2342046507 ps
CPU time 35.24 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 01:53:09 PM PST 23
Peak memory 223884 kb
Host smart-aaf8f3c5-9e5f-47fd-847a-1b16fb87ba3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4891609749561316442178170258702041471949729218586848474061033088564659642956 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.kmac_edn_timeout_error.4891609749561316442178170258702041471949729218586848474061033088564659642956 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.86095467260696378707448841625989626640264430398186947498166039942936853130571
Short name T306
Test name
Test status
Simulation time 2211297553 ps
CPU time 29.93 seconds
Started Nov 22 01:52:17 PM PST 23
Finished Nov 22 01:52:51 PM PST 23
Peak memory 223872 kb
Host smart-45264558-5782-4259-8892-a8baadf42782
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=86095467260696378707448841625989626640264430398186947498166039942936853130571 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.86095467260696378707448841625989626640264430398186947498166039942936853130571 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.24917796635670578258622428973362416564471998152744471201998564310835534232073
Short name T724
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.09 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 01:52:52 PM PST 23
Peak memory 216828 kb
Host smart-77a499ae-61b4-4ba2-ba1f-a61e89145267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24917796635670578258622428973362416564471998152744471201998564310835534232073 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.kmac_entropy_ready_error.24917796635670578258622428973362416564471998152744471201998564310835534232073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.103521383088157921274289134874120024227999989728804034355820438864608727044083
Short name T471
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.99 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 01:53:47 PM PST 23
Peak memory 227020 kb
Host smart-fced0fd9-e4c8-4189-8678-014589ee1e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103521383088157921274289134874120024227999989728804034355820438864608727044083 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_entropy_refresh.103521383088157921274289134874120024227999989728804034355820438864608727044083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.23950072971134770999079759119268753926158124980556191835580771044882037821829
Short name T725
Test name
Test status
Simulation time 8615085608 ps
CPU time 123.58 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 01:54:18 PM PST 23
Peak memory 248524 kb
Host smart-44e5ec7c-d60e-4cac-8088-597b10345061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23950072971134770999079759119268753926158124980556191835580771044882037821829 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.kmac_error.23950072971134770999079759119268753926158124980556191835580771044882037821829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.51957005925196443953024748736456255748412162995489115928743111778766427263719
Short name T469
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.23 seconds
Started Nov 22 01:52:32 PM PST 23
Finished Nov 22 01:52:40 PM PST 23
Peak memory 207548 kb
Host smart-35a2a184-2e06-4fa3-8cd0-35dc0e2697b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51957005925196443953024748736456255748412162995489115928743111778766427263719 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.kmac_key_error.51957005925196443953024748736456255748412162995489115928743111778766427263719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.90826467077349950122172702152264630561574143455648866980690572076811449481513
Short name T807
Test name
Test status
Simulation time 58171921 ps
CPU time 1.22 seconds
Started Nov 22 01:52:39 PM PST 23
Finished Nov 22 01:52:46 PM PST 23
Peak memory 215624 kb
Host smart-00320141-62c2-4dfa-9d25-e4b772400e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90826467077349950122172702152264630561574143455648866980690572076811449481513 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.kmac_lc_escalation.90826467077349950122172702152264630561574143455648866980690572076811449481513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.47040237528901601919138622728253293888087479009427729678040062646597935556391
Short name T687
Test name
Test status
Simulation time 45517522529 ps
CPU time 691.36 seconds
Started Nov 22 01:52:28 PM PST 23
Finished Nov 22 02:04:06 PM PST 23
Peak memory 288312 kb
Host smart-c94fb0b8-9361-47d1-8016-98815b0c3e56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47040237528901601919138622728253293888087479009427729678040062646597935556391 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.4704023752890160191913862272825329388808747900942772967804006264659793
5556391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.20951676044434750575912511630074233223938709127574155347103376216280964909150
Short name T48
Test name
Test status
Simulation time 5640716546 ps
CPU time 75 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 227524 kb
Host smart-95395c84-7596-4df6-93e7-7f39b76d9508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20951676044434750575912511630074233223938709127574155347103376216280964909150 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.kmac_mubi.20951676044434750575912511630074233223938709127574155347103376216280964909150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.3671308095544615086666407047056150509771620452280529058794589000502042725029
Short name T27
Test name
Test status
Simulation time 4127675079 ps
CPU time 32.05 seconds
Started Nov 22 01:52:23 PM PST 23
Finished Nov 22 01:52:56 PM PST 23
Peak memory 248916 kb
Host smart-4d31f136-4b57-4e6f-8c8e-3e0b37fbe6bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671308095544615086666407047056150509771620452280529058794589000502042725029 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.kmac_sec_cm.3671308095544615086666407047056150509771620452280529058794589000502042725029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.59563172594770676702164175158373120785865378072240586492562351998068656007765
Short name T866
Test name
Test status
Simulation time 7733092664 ps
CPU time 112.1 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 01:54:28 PM PST 23
Peak memory 228100 kb
Host smart-823bed5a-a470-484a-baf4-7449f3b8f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59563172594770676702164175158373120785865378072240586492562351998068656007765 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.kmac_sideload.59563172594770676702164175158373120785865378072240586492562351998068656007765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.21304954291626622224603507549184769224487435945155199331905102106365227152855
Short name T450
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.25 seconds
Started Nov 22 01:52:24 PM PST 23
Finished Nov 22 01:52:45 PM PST 23
Peak memory 215964 kb
Host smart-ab807e57-35c4-4b9e-8a90-fc6da83226b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21304954291626622224603507549184769224487435945155199331905102106365227152855 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.kmac_smoke.21304954291626622224603507549184769224487435945155199331905102106365227152855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.18937459398425885158963287524193761145823426717729841490630883061284450833517
Short name T902
Test name
Test status
Simulation time 41434001626 ps
CPU time 581.17 seconds
Started Nov 22 01:52:35 PM PST 23
Finished Nov 22 02:02:22 PM PST 23
Peak memory 321580 kb
Host smart-77b8a5ce-ae8e-40d6-a2c8-85425c92ac2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=18937459398425885158963287524193761145823426717729841490630883061284450833517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_str
ess_all.18937459398425885158963287524193761145823426717729841490630883061284450833517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.61610284026692438262368683017449259269004667458989958790305166277502115030671
Short name T1042
Test name
Test status
Simulation time 298812853 ps
CPU time 4.3 seconds
Started Nov 22 01:52:24 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 215788 kb
Host smart-f22cbd14-a03f-4051-87c0-55050a8eefc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61610284026692438262368683017449259269004667458989958
790305166277502115030671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.616102840266924382623686830174492592690
04667458989958790305166277502115030671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.51681926356449481567820755701929671739384638248445114688882968204282453214227
Short name T549
Test name
Test status
Simulation time 289902210 ps
CPU time 4.07 seconds
Started Nov 22 01:52:38 PM PST 23
Finished Nov 22 01:52:48 PM PST 23
Peak memory 215828 kb
Host smart-29004f76-15f9-4edf-84c9-d092753700bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51681926356449481567820755701929671739384638248445114
688882968204282453214227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.5168192635644948156782075570192
9671739384638248445114688882968204282453214227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.95115275850116527524348289402002306179005750012078743424125932191628009747899
Short name T718
Test name
Test status
Simulation time 115269125226 ps
CPU time 1746.94 seconds
Started Nov 22 01:52:11 PM PST 23
Finished Nov 22 02:21:21 PM PST 23
Peak memory 390320 kb
Host smart-43efc023-cf62-45a6-8fdf-10b08ffa27a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=95115275850116527524348289402002306179005750012078743424125932191628009747899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
kmac_test_vectors_sha3_224.95115275850116527524348289402002306179005750012078743424125932191628009747899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.57669226556599697310494519099602714014826868166744507101522173542145653829366
Short name T766
Test name
Test status
Simulation time 107886220004 ps
CPU time 1594.82 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 02:19:09 PM PST 23
Peak memory 370156 kb
Host smart-ad5c4e9e-a09d-4a1d-855c-4cadd8919fc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57669226556599697310494519099602714014826868166744507101522173542145653829366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
kmac_test_vectors_sha3_256.57669226556599697310494519099602714014826868166744507101522173542145653829366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.87063031192402831709234366793180359384191288634896243299118001420580128575757
Short name T190
Test name
Test status
Simulation time 83070954242 ps
CPU time 1283.61 seconds
Started Nov 22 01:52:29 PM PST 23
Finished Nov 22 02:13:58 PM PST 23
Peak memory 332896 kb
Host smart-77b724e6-02a5-42f4-ba95-0b62a465bfca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=87063031192402831709234366793180359384191288634896243299118001420580128575757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
kmac_test_vectors_sha3_384.87063031192402831709234366793180359384191288634896243299118001420580128575757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.61615875968634043827035596759133356146164611796821340395498186753975400629996
Short name T562
Test name
Test status
Simulation time 58503507926 ps
CPU time 898.38 seconds
Started Nov 22 01:52:29 PM PST 23
Finished Nov 22 02:07:33 PM PST 23
Peak memory 295912 kb
Host smart-d55b7a71-932a-49e9-9605-f503ad200b09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61615875968634043827035596759133356146164611796821340395498186753975400629996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
kmac_test_vectors_sha3_512.61615875968634043827035596759133356146164611796821340395498186753975400629996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.104441573306014629325966364753623619406779972859331498594245259303984188136607
Short name T994
Test name
Test status
Simulation time 307766781661 ps
CPU time 4492.76 seconds
Started Nov 22 01:52:13 PM PST 23
Finished Nov 22 03:07:09 PM PST 23
Peak memory 653268 kb
Host smart-b0ffedf0-9b31-4a23-af89-d34e2fee0e3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=104441573306014629325966364753623619406779972859331498594245259303984188136607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.kmac_test_vectors_shake_128.104441573306014629325966364753623619406779972859331498594245259303984188136607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.16744011533068627314452428215335117903318363850552305092914046406756579053262
Short name T592
Test name
Test status
Simulation time 258047411562 ps
CPU time 3731.51 seconds
Started Nov 22 01:52:15 PM PST 23
Finished Nov 22 02:54:30 PM PST 23
Peak memory 556320 kb
Host smart-2cea9fd5-19e3-491f-aa9e-65ba5b79fa59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=16744011533068627314452428215335117903318363850552305092914046406756579053262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.kmac_test_vectors_shake_256.16744011533068627314452428215335117903318363850552305092914046406756579053262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.42635684501724199797659278975127446637172728331761907642056278427330311855644
Short name T995
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 01:53:34 PM PST 23
Peak memory 205060 kb
Host smart-4e03058e-a1a9-4e23-8451-df97a1e2e658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42635684501724199797659278975127446637172728331761907642056278427330311855644 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.kmac_alert_test.42635684501724199797659278975127446637172728331761907642056278427330311855644 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.81522158931666180179567139657109229796887480734995314777235596481878826752051
Short name T338
Test name
Test status
Simulation time 5659537824 ps
CPU time 73.74 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 01:54:56 PM PST 23
Peak memory 227332 kb
Host smart-05993e9c-85aa-4a5f-b3e0-14aa24ac9e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81522158931666180179567139657109229796887480734995314777235596481878826752051 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.kmac_app.81522158931666180179567139657109229796887480734995314777235596481878826752051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.107595441786024737764833698968412270545925815000846482364399478310177769090768
Short name T821
Test name
Test status
Simulation time 14812750312 ps
CPU time 248.95 seconds
Started Nov 22 01:53:17 PM PST 23
Finished Nov 22 01:57:32 PM PST 23
Peak memory 225572 kb
Host smart-8d8b41a1-bd87-4e27-a820-defa7fd98777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107595441786024737764833698968412270545925815000846482364399478310177769090768 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.kmac_burst_write.107595441786024737764833698968412270545925815000846482364399478310177769090768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.78123730446580042218732490123832472339747567909980046453635099108026067458234
Short name T179
Test name
Test status
Simulation time 2342046507 ps
CPU time 32.79 seconds
Started Nov 22 01:53:17 PM PST 23
Finished Nov 22 01:53:56 PM PST 23
Peak memory 223856 kb
Host smart-bf5ab528-57c1-44e3-aac9-e818bb8c200f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78123730446580042218732490123832472339747567909980046453635099108026067458234 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.kmac_edn_timeout_error.78123730446580042218732490123832472339747567909980046453635099108026067458234 +enable_masking=0
+sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.48961649300767544103667941040453419366985196327949576886518767453459232856919
Short name T404
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.2 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 01:53:27 PM PST 23
Peak memory 223932 kb
Host smart-eb2611c6-a656-409e-bc92-2ae723f328ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48961649300767544103667941040453419366985196327949576886518767453459232856919 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.48961649300767544103667941040453419366985196327949576886518767453459232856919 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.8679132058719366883838752319440203358270189492380850212921950809820630189315
Short name T794
Test name
Test status
Simulation time 6743332725 ps
CPU time 71.82 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 01:54:45 PM PST 23
Peak memory 227028 kb
Host smart-4d028718-2381-4a1c-8ff5-84d997a1a9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8679132058719366883838752319440203358270189492380850212921950809820630189315 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.kmac_entropy_refresh.8679132058719366883838752319440203358270189492380850212921950809820630189315 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.12345440229072463048749297906837168132303208207334044525385010861524186564275
Short name T778
Test name
Test status
Simulation time 8615085608 ps
CPU time 133.37 seconds
Started Nov 22 01:53:26 PM PST 23
Finished Nov 22 01:55:41 PM PST 23
Peak memory 248704 kb
Host smart-41e88334-f839-4690-b554-67437c660301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12345440229072463048749297906837168132303208207334044525385010861524186564275 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.kmac_error.12345440229072463048749297906837168132303208207334044525385010861524186564275 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.44900380414451223009423334171023551477972454135023822840716830525352501051524
Short name T664
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.24 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 01:53:00 PM PST 23
Peak memory 207556 kb
Host smart-f7dcf803-1d81-4492-8b26-ac489c82f788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44900380414451223009423334171023551477972454135023822840716830525352501051524 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.kmac_key_error.44900380414451223009423334171023551477972454135023822840716830525352501051524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.102099930193952908224152373563332138644614844778535734591274831818527599666078
Short name T298
Test name
Test status
Simulation time 45517522529 ps
CPU time 735.15 seconds
Started Nov 22 01:53:23 PM PST 23
Finished Nov 22 02:05:40 PM PST 23
Peak memory 288348 kb
Host smart-502f6d26-bf47-48fd-85eb-a64f4a40258a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102099930193952908224152373563332138644614844778535734591274831818527599666078 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.10209993019395290822415237356333213864461484477853573459127483181852
7599666078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.54256834864100837522964257347140954150325201537698638027728291206872518966373
Short name T313
Test name
Test status
Simulation time 7733092664 ps
CPU time 107.98 seconds
Started Nov 22 01:53:11 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 228172 kb
Host smart-9c69ebdd-66a2-4f24-a732-6af1cb81d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54256834864100837522964257347140954150325201537698638027728291206872518966373 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.kmac_sideload.54256834864100837522964257347140954150325201537698638027728291206872518966373 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.40118636266772023405991960899417921367332704657460338048212263933171811958988
Short name T253
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.32 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 215932 kb
Host smart-fdf0ab1b-5939-4523-9004-67bfdf1eb156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40118636266772023405991960899417921367332704657460338048212263933171811958988 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.kmac_smoke.40118636266772023405991960899417921367332704657460338048212263933171811958988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.89144176545668696024855118226340680883000654343895135756080465538767575544390
Short name T737
Test name
Test status
Simulation time 41434001626 ps
CPU time 602.28 seconds
Started Nov 22 01:53:18 PM PST 23
Finished Nov 22 02:03:25 PM PST 23
Peak memory 321700 kb
Host smart-c14dd05b-c53f-41ab-a32e-3d2fbca5630a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=89144176545668696024855118226340680883000654343895135756080465538767575544390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_st
ress_all.89144176545668696024855118226340680883000654343895135756080465538767575544390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.34870639236085540591633135458849053623761708756843012570307579507437427467992
Short name T64
Test name
Test status
Simulation time 298812853 ps
CPU time 4.36 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:53:28 PM PST 23
Peak memory 215788 kb
Host smart-24d8f5af-6d61-444e-a02d-e16f9f009fbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34870639236085540591633135458849053623761708756843012
570307579507437427467992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac.34870639236085540591633135458849053623
761708756843012570307579507437427467992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.16979019323574511080496426123816752077044338211675273388202244085202888093688
Short name T984
Test name
Test status
Simulation time 289902210 ps
CPU time 4.18 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:53:26 PM PST 23
Peak memory 215656 kb
Host smart-435c241e-08b4-4eab-b5ee-b5e4de033432
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16979019323574511080496426123816752077044338211675273
388202244085202888093688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.169790193235745110804964261238
16752077044338211675273388202244085202888093688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.100978215989839888242381259648698413624209951518958324524274657778613959114428
Short name T644
Test name
Test status
Simulation time 115269125226 ps
CPU time 1662.96 seconds
Started Nov 22 01:52:58 PM PST 23
Finished Nov 22 02:20:42 PM PST 23
Peak memory 390544 kb
Host smart-68b34c4c-c08b-4bf8-89e1-42488949255a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=100978215989839888242381259648698413624209951518958324524274657778613959114428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.kmac_test_vectors_sha3_224.100978215989839888242381259648698413624209951518958324524274657778613959114428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.98527357811697347491256222512925659390370728517067606104097692614852280128089
Short name T765
Test name
Test status
Simulation time 107886220004 ps
CPU time 1555.1 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 02:19:28 PM PST 23
Peak memory 370120 kb
Host smart-dbc4cfc5-53a7-4ebb-aa23-ab572ef3b775
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=98527357811697347491256222512925659390370728517067606104097692614852280128089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.kmac_test_vectors_sha3_256.98527357811697347491256222512925659390370728517067606104097692614852280128089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.63873832610764058089344849848127949245085465972038381871259907599128153705428
Short name T925
Test name
Test status
Simulation time 83070954242 ps
CPU time 1248.77 seconds
Started Nov 22 01:53:02 PM PST 23
Finished Nov 22 02:13:51 PM PST 23
Peak memory 332904 kb
Host smart-4f6f3080-4959-4b54-bcb5-4794b6a0d0d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=63873832610764058089344849848127949245085465972038381871259907599128153705428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.kmac_test_vectors_sha3_384.63873832610764058089344849848127949245085465972038381871259907599128153705428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.25596728486466622605565311867741737339315059581035518077642044943063702614181
Short name T337
Test name
Test status
Simulation time 58503507926 ps
CPU time 897.57 seconds
Started Nov 22 01:53:15 PM PST 23
Finished Nov 22 02:08:18 PM PST 23
Peak memory 295896 kb
Host smart-db719fc1-ff9d-4f00-818c-192c738dd843
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25596728486466622605565311867741737339315059581035518077642044943063702614181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.kmac_test_vectors_sha3_512.25596728486466622605565311867741737339315059581035518077642044943063702614181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.9637107576809892614529478761374378050114294010781964219284614189320328581020
Short name T927
Test name
Test status
Simulation time 307766781661 ps
CPU time 4521.96 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 03:08:45 PM PST 23
Peak memory 653264 kb
Host smart-dccaa84b-37f0-4f6a-bd6e-e40645eaaa62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=9637107576809892614529478761374378050114294010781964219284614189320328581020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.kmac_test_vectors_shake_128.9637107576809892614529478761374378050114294010781964219284614189320328581020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.48453008747366968571139152965217116956223005012620000744834847707358592757978
Short name T271
Test name
Test status
Simulation time 258047411562 ps
CPU time 3660.79 seconds
Started Nov 22 01:53:23 PM PST 23
Finished Nov 22 02:54:26 PM PST 23
Peak memory 556292 kb
Host smart-68e9c2cf-c0f0-4b9a-82de-7820a1b67081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=48453008747366968571139152965217116956223005012620000744834847707358592757978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.kmac_test_vectors_shake_256.48453008747366968571139152965217116956223005012620000744834847707358592757978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.44890862059074189388283554351855506381063768545596179356100617985360369554823
Short name T872
Test name
Test status
Simulation time 21118646 ps
CPU time 0.77 seconds
Started Nov 22 01:52:56 PM PST 23
Finished Nov 22 01:52:58 PM PST 23
Peak memory 205248 kb
Host smart-100f929e-619b-4353-8214-d54a591fb15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44890862059074189388283554351855506381063768545596179356100617985360369554823 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.kmac_alert_test.44890862059074189388283554351855506381063768545596179356100617985360369554823 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.4263871204056251757803499256029627946579124585614783379532685196268488697412
Short name T234
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.16 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 01:54:48 PM PST 23
Peak memory 227368 kb
Host smart-41f14dc1-e72a-411a-885a-f73aa80bd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263871204056251757803499256029627946579124585614783379532685196268488697412 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.kmac_app.4263871204056251757803499256029627946579124585614783379532685196268488697412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.14735240964536977092078945044395664042848269610711251583147169039689967593151
Short name T442
Test name
Test status
Simulation time 14812750312 ps
CPU time 236.34 seconds
Started Nov 22 01:52:58 PM PST 23
Finished Nov 22 01:56:55 PM PST 23
Peak memory 225456 kb
Host smart-8c56a527-51c9-48db-8794-bf1d24941c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14735240964536977092078945044395664042848269610711251583147169039689967593151 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.kmac_burst_write.14735240964536977092078945044395664042848269610711251583147169039689967593151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.70561776160985125193173469123502506146800686901714243299259117719658431708688
Short name T142
Test name
Test status
Simulation time 2342046507 ps
CPU time 34.47 seconds
Started Nov 22 01:52:58 PM PST 23
Finished Nov 22 01:53:33 PM PST 23
Peak memory 223856 kb
Host smart-6c8ba1f6-60d6-490d-a70b-12efb39449c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=70561776160985125193173469123502506146800686901714243299259117719658431708688 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.kmac_edn_timeout_error.70561776160985125193173469123502506146800686901714243299259117719658431708688 +enable_masking=0
+sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.58398954737154573949244422589844168216582374710123592600951091816641640757560
Short name T1022
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.63 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:53:52 PM PST 23
Peak memory 223896 kb
Host smart-978cbd80-06c2-4bd3-94a0-a425be3c51eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58398954737154573949244422589844168216582374710123592600951091816641640757560 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.58398954737154573949244422589844168216582374710123592600951091816641640757560 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.31114276894455003788266861637498124533942898862600627759853046032840220994937
Short name T626
Test name
Test status
Simulation time 6743332725 ps
CPU time 77.55 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 01:54:35 PM PST 23
Peak memory 226996 kb
Host smart-798b39b3-0091-4403-bc0b-04e6b4f4058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31114276894455003788266861637498124533942898862600627759853046032840220994937 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.kmac_entropy_refresh.31114276894455003788266861637498124533942898862600627759853046032840220994937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.20425425895874673361758724318483939209128302912892550334280626313732835301477
Short name T157
Test name
Test status
Simulation time 8615085608 ps
CPU time 127.5 seconds
Started Nov 22 01:53:17 PM PST 23
Finished Nov 22 01:55:30 PM PST 23
Peak memory 248660 kb
Host smart-a3bb5152-3365-48ef-8ad4-c5c9e437336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20425425895874673361758724318483939209128302912892550334280626313732835301477 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.kmac_error.20425425895874673361758724318483939209128302912892550334280626313732835301477 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.106796716640509994978660929899097925427582831744061273307673381054525940242012
Short name T37
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.16 seconds
Started Nov 22 01:53:13 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 207548 kb
Host smart-1bf9d646-3287-4093-8ce6-101c9430cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106796716640509994978660929899097925427582831744061273307673381054525940242012 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.kmac_key_error.106796716640509994978660929899097925427582831744061273307673381054525940242012 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.35346360344803466702490854727240873133400951847538172433007380609353347906364
Short name T383
Test name
Test status
Simulation time 58171921 ps
CPU time 1.23 seconds
Started Nov 22 01:53:27 PM PST 23
Finished Nov 22 01:53:29 PM PST 23
Peak memory 215736 kb
Host smart-641bb4bd-fd95-41da-b697-cbfb74d7a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35346360344803466702490854727240873133400951847538172433007380609353347906364 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.kmac_lc_escalation.35346360344803466702490854727240873133400951847538172433007380609353347906364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.8192162738817977815413265691165031517891092343174382681453335246263040421068
Short name T419
Test name
Test status
Simulation time 45517522529 ps
CPU time 741.87 seconds
Started Nov 22 01:53:21 PM PST 23
Finished Nov 22 02:05:46 PM PST 23
Peak memory 288256 kb
Host smart-cc316e63-51e7-4d17-98f0-8b51b65ede51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8192162738817977815413265691165031517891092343174382681453335246263040421068 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.8192162738817977815413265691165031517891092343174382681453335246263040
421068 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.103817914785400874726932786521253704831333551659800760964988358228151817463556
Short name T558
Test name
Test status
Simulation time 7733092664 ps
CPU time 111.55 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 01:55:28 PM PST 23
Peak memory 228108 kb
Host smart-398bf094-8f67-4b22-ab4e-05b13bf326eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103817914785400874726932786521253704831333551659800760964988358228151817463556 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.kmac_sideload.103817914785400874726932786521253704831333551659800760964988358228151817463556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.41110481221431482896034075521544920797041451469551320865965079949807385865850
Short name T715
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.37 seconds
Started Nov 22 01:53:13 PM PST 23
Finished Nov 22 01:53:35 PM PST 23
Peak memory 215952 kb
Host smart-dc4faa38-ec26-4499-a9bd-d21d565d6d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41110481221431482896034075521544920797041451469551320865965079949807385865850 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.kmac_smoke.41110481221431482896034075521544920797041451469551320865965079949807385865850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.96760679106101266413501422594472612610460292213422266218712636253997922829055
Short name T982
Test name
Test status
Simulation time 41434001626 ps
CPU time 624.17 seconds
Started Nov 22 01:53:33 PM PST 23
Finished Nov 22 02:03:58 PM PST 23
Peak memory 321700 kb
Host smart-20a1b927-fd07-4707-aaf4-0a400233c84b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=96760679106101266413501422594472612610460292213422266218712636253997922829055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_st
ress_all.96760679106101266413501422594472612610460292213422266218712636253997922829055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.73789999606209776672974785591231729282014805638126733111426363126958421291719
Short name T837
Test name
Test status
Simulation time 298812853 ps
CPU time 4.42 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:53:26 PM PST 23
Peak memory 215844 kb
Host smart-b6bd6dbc-6e67-47a1-a429-e69adb467cac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73789999606209776672974785591231729282014805638126733
111426363126958421291719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac.73789999606209776672974785591231729282
014805638126733111426363126958421291719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.40465860426805530414148253443295441810274438829736453504336189902677546796314
Short name T315
Test name
Test status
Simulation time 289902210 ps
CPU time 4.29 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:53:28 PM PST 23
Peak memory 215904 kb
Host smart-6ef9a405-dfc3-4652-a2c2-5e4289c1530e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40465860426805530414148253443295441810274438829736453
504336189902677546796314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac_xof.404658604268055304141482534432
95441810274438829736453504336189902677546796314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.20229202368570736486015058848991278455242341719111110356060828197002635714216
Short name T791
Test name
Test status
Simulation time 115269125226 ps
CPU time 1701.84 seconds
Started Nov 22 01:53:37 PM PST 23
Finished Nov 22 02:22:01 PM PST 23
Peak memory 390548 kb
Host smart-21ed2767-9a12-4d2c-9ad5-fae2480b6d4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=20229202368570736486015058848991278455242341719111110356060828197002635714216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.kmac_test_vectors_sha3_224.20229202368570736486015058848991278455242341719111110356060828197002635714216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.109454748514080902574784738319585115531111407909212713451555118666355562256407
Short name T510
Test name
Test status
Simulation time 107886220004 ps
CPU time 1624.97 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 02:20:29 PM PST 23
Peak memory 370264 kb
Host smart-e06dc97d-8972-4d24-be3b-36166d62cdd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=109454748514080902574784738319585115531111407909212713451555118666355562256407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.kmac_test_vectors_sha3_256.109454748514080902574784738319585115531111407909212713451555118666355562256407 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.102270489737749577851592722695892366323709029817396753902501309539957809907174
Short name T279
Test name
Test status
Simulation time 83070954242 ps
CPU time 1174.28 seconds
Started Nov 22 01:53:04 PM PST 23
Finished Nov 22 02:12:39 PM PST 23
Peak memory 332864 kb
Host smart-ea56e179-3363-455c-b426-502220252aea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=102270489737749577851592722695892366323709029817396753902501309539957809907174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.kmac_test_vectors_sha3_384.102270489737749577851592722695892366323709029817396753902501309539957809907174 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.98996235983183170002629981170878699354288527795802316207882514609649144715894
Short name T136
Test name
Test status
Simulation time 58503507926 ps
CPU time 863.6 seconds
Started Nov 22 01:53:27 PM PST 23
Finished Nov 22 02:07:52 PM PST 23
Peak memory 295892 kb
Host smart-3815e884-5f1b-4c6f-a340-4c7023430cf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=98996235983183170002629981170878699354288527795802316207882514609649144715894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.kmac_test_vectors_sha3_512.98996235983183170002629981170878699354288527795802316207882514609649144715894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.10579092381636893879320276223836919185010619036669934220262862011563858377579
Short name T1033
Test name
Test status
Simulation time 307766781661 ps
CPU time 4471.26 seconds
Started Nov 22 01:53:28 PM PST 23
Finished Nov 22 03:08:01 PM PST 23
Peak memory 653236 kb
Host smart-ce95a6c8-5d77-44a2-8733-b194091c0d63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=10579092381636893879320276223836919185010619036669934220262862011563858377579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.kmac_test_vectors_shake_128.10579092381636893879320276223836919185010619036669934220262862011563858377579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.79427986892699488899968437912951159543871309531978047164827939071985305036066
Short name T781
Test name
Test status
Simulation time 258047411562 ps
CPU time 3789.32 seconds
Started Nov 22 01:53:01 PM PST 23
Finished Nov 22 02:56:11 PM PST 23
Peak memory 556272 kb
Host smart-a8931131-b43d-49ec-97fc-5cd6876443d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=79427986892699488899968437912951159543871309531978047164827939071985305036066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.kmac_test_vectors_shake_256.79427986892699488899968437912951159543871309531978047164827939071985305036066 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_app.29475082002981624744949324630018071310525464825384434411161901927559469646663
Short name T684
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.55 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 01:54:51 PM PST 23
Peak memory 227368 kb
Host smart-49620a51-9b1d-41f9-9ecc-070dbba9f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29475082002981624744949324630018071310525464825384434411161901927559469646663 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.kmac_app.29475082002981624744949324630018071310525464825384434411161901927559469646663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.76348692221709158294154424364777454368008324228542659919568183452159464943267
Short name T167
Test name
Test status
Simulation time 14812750312 ps
CPU time 232.91 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 01:57:26 PM PST 23
Peak memory 225528 kb
Host smart-33e6bcf7-e9d8-4b34-88a9-0daa81187be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76348692221709158294154424364777454368008324228542659919568183452159464943267 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.kmac_burst_write.76348692221709158294154424364777454368008324228542659919568183452159464943267 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.66373171172365201456322037066753879667227004596133000160378859911830413166441
Short name T34
Test name
Test status
Simulation time 2342046507 ps
CPU time 32.77 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 223888 kb
Host smart-a23b1d6b-1b16-4bd6-941d-8d603bfed31a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66373171172365201456322037066753879667227004596133000160378859911830413166441 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.kmac_edn_timeout_error.66373171172365201456322037066753879667227004596133000160378859911830413166441 +enable_masking=0
+sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.72617827862205325370434954802132370105007249997630103326888354133069942985758
Short name T660
Test name
Test status
Simulation time 2211297553 ps
CPU time 31.05 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 01:54:08 PM PST 23
Peak memory 223872 kb
Host smart-2b2b131b-e866-40bb-8bd4-c71dc36a3b6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=72617827862205325370434954802132370105007249997630103326888354133069942985758 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.72617827862205325370434954802132370105007249997630103326888354133069942985758 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.89551626467932577058154625093673657740447549614326294735743569213340191546777
Short name T252
Test name
Test status
Simulation time 6743332725 ps
CPU time 74.57 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 01:54:54 PM PST 23
Peak memory 227024 kb
Host smart-425e16af-d4d1-4bcd-8116-8dc96ea1f51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89551626467932577058154625093673657740447549614326294735743569213340191546777 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.kmac_entropy_refresh.89551626467932577058154625093673657740447549614326294735743569213340191546777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.63612798342973101157820509836300191242827895200459268884034502540220343512014
Short name T71
Test name
Test status
Simulation time 8615085608 ps
CPU time 126.07 seconds
Started Nov 22 01:53:18 PM PST 23
Finished Nov 22 01:55:29 PM PST 23
Peak memory 248628 kb
Host smart-fdb8a5ea-df6d-40bc-91e0-ad67e2371706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63612798342973101157820509836300191242827895200459268884034502540220343512014 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.kmac_error.63612798342973101157820509836300191242827895200459268884034502540220343512014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.48926459377854108663876434384528543591177237992509096129667268439791174479332
Short name T57
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.21 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 01:53:38 PM PST 23
Peak memory 207520 kb
Host smart-dd949e1c-e6c7-4c4c-8ecb-497fd200cda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48926459377854108663876434384528543591177237992509096129667268439791174479332 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.kmac_key_error.48926459377854108663876434384528543591177237992509096129667268439791174479332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.7648547219761355176152758225380154951028957214421570248070133449067424799305
Short name T493
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:53:45 PM PST 23
Peak memory 215784 kb
Host smart-c700383d-b7e2-4e53-915f-93de97ec6856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7648547219761355176152758225380154951028957214421570248070133449067424799305 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.kmac_lc_escalation.7648547219761355176152758225380154951028957214421570248070133449067424799305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.102486038432091273713456986769244317990765034468512061989971162701483985844421
Short name T283
Test name
Test status
Simulation time 45517522529 ps
CPU time 701.14 seconds
Started Nov 22 01:52:54 PM PST 23
Finished Nov 22 02:04:36 PM PST 23
Peak memory 288324 kb
Host smart-8048ec17-4925-4303-96d5-f852a6544170
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102486038432091273713456986769244317990765034468512061989971162701483985844421 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.10248603843209127371345698676924431799076503446851206198997116270148
3985844421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.94048954268555077830858646965732202555434059544880447507307706384181049057392
Short name T502
Test name
Test status
Simulation time 7733092664 ps
CPU time 106.35 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 228124 kb
Host smart-4632d8c5-e331-41b4-bfdd-b166142c2c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94048954268555077830858646965732202555434059544880447507307706384181049057392 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.kmac_sideload.94048954268555077830858646965732202555434059544880447507307706384181049057392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.81436252578324021516592872700861042143593378324620875257528585874239286396698
Short name T1061
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.87 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:53:42 PM PST 23
Peak memory 215852 kb
Host smart-b010665a-b6f9-4ff4-8dc0-7c5158d0dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81436252578324021516592872700861042143593378324620875257528585874239286396698 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.kmac_smoke.81436252578324021516592872700861042143593378324620875257528585874239286396698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.38551970300472999730900574984750113699646308453315421306452490617446440588411
Short name T289
Test name
Test status
Simulation time 41434001626 ps
CPU time 602.68 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 02:03:27 PM PST 23
Peak memory 321512 kb
Host smart-ae5cd2e9-e5e3-4662-bb7d-78047ed7f470
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=38551970300472999730900574984750113699646308453315421306452490617446440588411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_st
ress_all.38551970300472999730900574984750113699646308453315421306452490617446440588411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.106721700798515882426965195331129996046360844665900086507135061974888261615198
Short name T621
Test name
Test status
Simulation time 298812853 ps
CPU time 4.37 seconds
Started Nov 22 01:53:31 PM PST 23
Finished Nov 22 01:53:36 PM PST 23
Peak memory 215880 kb
Host smart-228a738c-3052-42ec-954c-c3cba21b2f30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672170079851588242696519533112999604636084466590008
6507135061974888261615198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac.1067217007985158824269651953311299960
46360844665900086507135061974888261615198 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.71013420144955688337286124940080650733244707391071165584691646394211006915299
Short name T516
Test name
Test status
Simulation time 289902210 ps
CPU time 4.14 seconds
Started Nov 22 01:53:18 PM PST 23
Finished Nov 22 01:53:27 PM PST 23
Peak memory 215800 kb
Host smart-5815020c-b672-431b-a6b5-40ce6ed4d7f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71013420144955688337286124940080650733244707391071165
584691646394211006915299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.710134201449556883372861249400
80650733244707391071165584691646394211006915299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.59268555922954798087875404826772800268621358354500713199655680775562458767514
Short name T513
Test name
Test status
Simulation time 115269125226 ps
CPU time 1635.29 seconds
Started Nov 22 01:53:15 PM PST 23
Finished Nov 22 02:20:36 PM PST 23
Peak memory 390316 kb
Host smart-662f1d38-f261-430f-9180-27621153fa4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59268555922954798087875404826772800268621358354500713199655680775562458767514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.kmac_test_vectors_sha3_224.59268555922954798087875404826772800268621358354500713199655680775562458767514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.54620830583522135828563142959142432421521790663782324060093230218896240205376
Short name T530
Test name
Test status
Simulation time 107886220004 ps
CPU time 1589.09 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 02:19:23 PM PST 23
Peak memory 370100 kb
Host smart-378c1aba-e3a2-42b2-bb26-3cca62eb6418
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=54620830583522135828563142959142432421521790663782324060093230218896240205376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.kmac_test_vectors_sha3_256.54620830583522135828563142959142432421521790663782324060093230218896240205376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.77068732397230681644405893095155867833659749263108566520761916075180729039806
Short name T177
Test name
Test status
Simulation time 83070954242 ps
CPU time 1233.92 seconds
Started Nov 22 01:53:12 PM PST 23
Finished Nov 22 02:13:51 PM PST 23
Peak memory 332936 kb
Host smart-b4b4a2f4-e630-4840-b4fa-c64558cadefe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77068732397230681644405893095155867833659749263108566520761916075180729039806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.kmac_test_vectors_sha3_384.77068732397230681644405893095155867833659749263108566520761916075180729039806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.61837045133367044245370748163705884004207230593140714064163136450892760449490
Short name T411
Test name
Test status
Simulation time 58503507926 ps
CPU time 859.25 seconds
Started Nov 22 01:53:13 PM PST 23
Finished Nov 22 02:07:37 PM PST 23
Peak memory 295868 kb
Host smart-0dfa2a2f-fb1a-4a75-b020-7e814744dd85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61837045133367044245370748163705884004207230593140714064163136450892760449490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.kmac_test_vectors_sha3_512.61837045133367044245370748163705884004207230593140714064163136450892760449490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.105565871409454748602597787460360451161816692665670282713642748343219265316458
Short name T197
Test name
Test status
Simulation time 307766781661 ps
CPU time 4504.41 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 03:08:22 PM PST 23
Peak memory 653268 kb
Host smart-aaded961-4441-42ba-8372-9c1455e91d46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=105565871409454748602597787460360451161816692665670282713642748343219265316458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.kmac_test_vectors_shake_128.105565871409454748602597787460360451161816692665670282713642748343219265316458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.23244660259507699079057176922377730128090392325726708344221757959359280584721
Short name T1045
Test name
Test status
Simulation time 258047411562 ps
CPU time 3507.27 seconds
Started Nov 22 01:52:54 PM PST 23
Finished Nov 22 02:51:23 PM PST 23
Peak memory 556148 kb
Host smart-0f203515-b240-45b8-87be-6d5a87b85506
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=23244660259507699079057176922377730128090392325726708344221757959359280584721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.kmac_test_vectors_shake_256.23244660259507699079057176922377730128090392325726708344221757959359280584721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.32181280454920892216533563056128629614500072693213561790574912452351892351863
Short name T178
Test name
Test status
Simulation time 21118646 ps
CPU time 0.72 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 205112 kb
Host smart-524bb4c1-3ea3-4f69-9fab-08ff7fc7fb1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32181280454920892216533563056128629614500072693213561790574912452351892351863 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.kmac_alert_test.32181280454920892216533563056128629614500072693213561790574912452351892351863 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.43246969550520843835972458018751413818201430340587346758023304923091904446342
Short name T860
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.64 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 227392 kb
Host smart-8285eea1-25ce-4c78-a0a0-1ab9d5019acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43246969550520843835972458018751413818201430340587346758023304923091904446342 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.kmac_app.43246969550520843835972458018751413818201430340587346758023304923091904446342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.49961780114682460931460810650183440714237203466228588705148317781064413597674
Short name T1077
Test name
Test status
Simulation time 14812750312 ps
CPU time 243.95 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:58:01 PM PST 23
Peak memory 225552 kb
Host smart-f4292ce8-4228-4685-9f43-2d4fcb151bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49961780114682460931460810650183440714237203466228588705148317781064413597674 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.kmac_burst_write.49961780114682460931460810650183440714237203466228588705148317781064413597674 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.39063795079080796601040464243079751502068002729554840498556828397362646729174
Short name T797
Test name
Test status
Simulation time 2342046507 ps
CPU time 35.1 seconds
Started Nov 22 01:54:14 PM PST 23
Finished Nov 22 01:54:50 PM PST 23
Peak memory 223860 kb
Host smart-9548713d-940a-4edd-9953-bd58b337d1b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=39063795079080796601040464243079751502068002729554840498556828397362646729174 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 13.kmac_edn_timeout_error.39063795079080796601040464243079751502068002729554840498556828397362646729174 +enable_masking=0
+sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.29440729314276546638564758062639387436492458469089986875302271142450042124859
Short name T340
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.52 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 01:54:28 PM PST 23
Peak memory 223868 kb
Host smart-599f6fb3-21be-4029-8809-7655a203eb17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=29440729314276546638564758062639387436492458469089986875302271142450042124859 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.29440729314276546638564758062639387436492458469089986875302271142450042124859 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.38348785651223334046032629234499734486944000525342517000797027711531237083828
Short name T846
Test name
Test status
Simulation time 6743332725 ps
CPU time 76.53 seconds
Started Nov 22 01:54:21 PM PST 23
Finished Nov 22 01:55:43 PM PST 23
Peak memory 227020 kb
Host smart-42a1e503-0149-46a5-9466-964e55cbb2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38348785651223334046032629234499734486944000525342517000797027711531237083828 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.kmac_entropy_refresh.38348785651223334046032629234499734486944000525342517000797027711531237083828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.31554738870781340623797233266542248621362849419817239445992977661441293185004
Short name T878
Test name
Test status
Simulation time 8615085608 ps
CPU time 131.57 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:56:07 PM PST 23
Peak memory 248636 kb
Host smart-1a07cf16-8750-4d66-87cd-e79208649c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31554738870781340623797233266542248621362849419817239445992977661441293185004 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.kmac_error.31554738870781340623797233266542248621362849419817239445992977661441293185004 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.94683790836488636828948770906629419560916102115518041252209666750509239061901
Short name T744
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.26 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 207532 kb
Host smart-934ac51f-9a9f-4861-a12a-159a4c38c377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94683790836488636828948770906629419560916102115518041252209666750509239061901 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.kmac_key_error.94683790836488636828948770906629419560916102115518041252209666750509239061901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.114507606918110312653958058899048601418772031834682011952520459508746779850965
Short name T448
Test name
Test status
Simulation time 58171921 ps
CPU time 1.29 seconds
Started Nov 22 01:54:01 PM PST 23
Finished Nov 22 01:54:04 PM PST 23
Peak memory 215728 kb
Host smart-a44bd7fc-4194-4d43-b971-9ce06ef96e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114507606918110312653958058899048601418772031834682011952520459508746779850965 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.kmac_lc_escalation.114507606918110312653958058899048601418772031834682011952520459508746779850965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.69483407306812159767133936831743875740233064301818542688425690602873457906899
Short name T507
Test name
Test status
Simulation time 45517522529 ps
CPU time 678.5 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 02:05:14 PM PST 23
Peak memory 288224 kb
Host smart-d2ca3305-5b6a-45be-a36e-b68befcf7683
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69483407306812159767133936831743875740233064301818542688425690602873457906899 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.694834073068121597671339368317438757402330643018185426884256906028734
57906899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.82625640761158771073347260554442849451170681552494567034077419721039041328537
Short name T236
Test name
Test status
Simulation time 7733092664 ps
CPU time 110.8 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:55:46 PM PST 23
Peak memory 228152 kb
Host smart-422f3a55-82e6-44c6-bdfa-d9d2543815d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82625640761158771073347260554442849451170681552494567034077419721039041328537 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.kmac_sideload.82625640761158771073347260554442849451170681552494567034077419721039041328537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.80402288011767281194666357875924153164434660864272468463538691053892001167266
Short name T966
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.84 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 01:54:17 PM PST 23
Peak memory 215904 kb
Host smart-ef11a0a0-1835-4a53-a5c2-4221b6bafd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80402288011767281194666357875924153164434660864272468463538691053892001167266 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.kmac_smoke.80402288011767281194666357875924153164434660864272468463538691053892001167266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.99249737700039368742507734303308295607313582252887746602681315446158985449131
Short name T356
Test name
Test status
Simulation time 41434001626 ps
CPU time 597.59 seconds
Started Nov 22 01:54:14 PM PST 23
Finished Nov 22 02:04:12 PM PST 23
Peak memory 321716 kb
Host smart-7d24f644-c7b9-4600-b255-8b1226359cb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=99249737700039368742507734303308295607313582252887746602681315446158985449131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_st
ress_all.99249737700039368742507734303308295607313582252887746602681315446158985449131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.75846406133136676287431766250268029467365563273937835049386025978462014944500
Short name T324
Test name
Test status
Simulation time 298812853 ps
CPU time 4.22 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 215816 kb
Host smart-3c81be0d-a96d-4e71-8953-ff8371a1ec68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75846406133136676287431766250268029467365563273937835
049386025978462014944500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac.75846406133136676287431766250268029467
365563273937835049386025978462014944500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.53226509577895126107767215788890546356696842613678259232655997100104893159743
Short name T21
Test name
Test status
Simulation time 289902210 ps
CPU time 4.09 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 01:53:55 PM PST 23
Peak memory 215808 kb
Host smart-1a9edeaa-fb46-4aa6-ba05-a1a0c0164c76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53226509577895126107767215788890546356696842613678259
232655997100104893159743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.532265095778951261077672157888
90546356696842613678259232655997100104893159743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.61453050508567455147518204003489414363346911852645380274908708753927268141103
Short name T566
Test name
Test status
Simulation time 115269125226 ps
CPU time 1761.49 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 02:23:10 PM PST 23
Peak memory 390352 kb
Host smart-6ab9e356-451c-434a-b862-0793e7a83b72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61453050508567455147518204003489414363346911852645380274908708753927268141103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_224.61453050508567455147518204003489414363346911852645380274908708753927268141103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.78519052244574758163383774352804044559048413289499951025018054567904816491699
Short name T728
Test name
Test status
Simulation time 107886220004 ps
CPU time 1598.51 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 02:20:30 PM PST 23
Peak memory 369972 kb
Host smart-df71c04b-633a-4bcb-b24f-5f3c51b7e057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=78519052244574758163383774352804044559048413289499951025018054567904816491699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_256.78519052244574758163383774352804044559048413289499951025018054567904816491699 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.12360482253763311570027619672677413055976711246474917227906013790315225565590
Short name T1005
Test name
Test status
Simulation time 83070954242 ps
CPU time 1264 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 02:14:59 PM PST 23
Peak memory 332900 kb
Host smart-e59a9358-09c8-4bba-b858-9eeeb37dd310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=12360482253763311570027619672677413055976711246474917227906013790315225565590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_384.12360482253763311570027619672677413055976711246474917227906013790315225565590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.89933888499430626530658163323006939798189850096646877203537175109581412693586
Short name T416
Test name
Test status
Simulation time 58503507926 ps
CPU time 890.17 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 02:08:37 PM PST 23
Peak memory 295936 kb
Host smart-823ff23e-770e-45fd-9347-17ba1899a87a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89933888499430626530658163323006939798189850096646877203537175109581412693586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.kmac_test_vectors_sha3_512.89933888499430626530658163323006939798189850096646877203537175109581412693586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.101558862144417457479638357298122072506342352697450421362751205328071956106854
Short name T672
Test name
Test status
Simulation time 307766781661 ps
CPU time 4379.21 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 03:07:03 PM PST 23
Peak memory 653244 kb
Host smart-63c57443-79b2-41ef-9b2b-f70842b4a888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=101558862144417457479638357298122072506342352697450421362751205328071956106854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.kmac_test_vectors_shake_128.101558862144417457479638357298122072506342352697450421362751205328071956106854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.48212266602037008896554503041870751252363718527643330369298047015716184185425
Short name T856
Test name
Test status
Simulation time 258047411562 ps
CPU time 3729.14 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 02:56:24 PM PST 23
Peak memory 556240 kb
Host smart-bb621047-c2c2-401e-9ddc-74b382e2cf0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=48212266602037008896554503041870751252363718527643330369298047015716184185425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.kmac_test_vectors_shake_256.48212266602037008896554503041870751252363718527643330369298047015716184185425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.4655212327354851187753876779306991288101320658891841814837875972567875563268
Short name T661
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 205328 kb
Host smart-18f841a2-6ae3-43ca-b411-62080d51df97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4655212327354851187753876779306991288101320658891841814837875972567875563268 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.kmac_alert_test.4655212327354851187753876779306991288101320658891841814837875972567875563268 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.87605937359835497895795881361588557593230382347052043661389943854840407393598
Short name T325
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.58 seconds
Started Nov 22 01:53:18 PM PST 23
Finished Nov 22 01:54:38 PM PST 23
Peak memory 227372 kb
Host smart-cdcc8c6d-f13a-4073-b0cf-478bde45be1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87605937359835497895795881361588557593230382347052043661389943854840407393598 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.kmac_app.87605937359835497895795881361588557593230382347052043661389943854840407393598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.25396266217176373121181101790521713232235551026842951674743094950751948089808
Short name T745
Test name
Test status
Simulation time 14812750312 ps
CPU time 250.01 seconds
Started Nov 22 01:53:27 PM PST 23
Finished Nov 22 01:57:38 PM PST 23
Peak memory 225588 kb
Host smart-b7dddfa0-eb22-4cad-bad3-d5bfbcd14b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25396266217176373121181101790521713232235551026842951674743094950751948089808 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.kmac_burst_write.25396266217176373121181101790521713232235551026842951674743094950751948089808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.49905017006401215611464358139214487644875824472165799289772728651318209094825
Short name T689
Test name
Test status
Simulation time 2342046507 ps
CPU time 33.11 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:53:57 PM PST 23
Peak memory 223832 kb
Host smart-89e37a69-4c18-4df2-bc6a-59e13d20ad4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49905017006401215611464358139214487644875824472165799289772728651318209094825 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.kmac_edn_timeout_error.49905017006401215611464358139214487644875824472165799289772728651318209094825 +enable_masking=0
+sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.79620388474537593411877772818098759757461421245646411310234569573032606174207
Short name T812
Test name
Test status
Simulation time 2211297553 ps
CPU time 31.29 seconds
Started Nov 22 01:53:02 PM PST 23
Finished Nov 22 01:53:34 PM PST 23
Peak memory 223928 kb
Host smart-d109a8cf-7f02-48a4-ac45-538149511e46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=79620388474537593411877772818098759757461421245646411310234569573032606174207 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.79620388474537593411877772818098759757461421245646411310234569573032606174207 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_error.70906533407120338120386284752830672020696766533360240012847561638891974153442
Short name T810
Test name
Test status
Simulation time 8615085608 ps
CPU time 129.76 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:55:32 PM PST 23
Peak memory 248604 kb
Host smart-c4673261-91ed-45b7-b5eb-305c44eee1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70906533407120338120386284752830672020696766533360240012847561638891974153442 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.kmac_error.70906533407120338120386284752830672020696766533360240012847561638891974153442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.95509401397868107314269674304904835179362675921575730199569694639825775426283
Short name T403
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.28 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 01:53:01 PM PST 23
Peak memory 207528 kb
Host smart-9b2d51af-5a9c-483d-a384-ba927abc0f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95509401397868107314269674304904835179362675921575730199569694639825775426283 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.kmac_key_error.95509401397868107314269674304904835179362675921575730199569694639825775426283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.10561721637537644394948625280905324741809479105609467145130411264321458676761
Short name T342
Test name
Test status
Simulation time 58171921 ps
CPU time 1.25 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 01:53:25 PM PST 23
Peak memory 215744 kb
Host smart-24e9aecc-d424-4e0f-95d5-8d2e35cc0569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10561721637537644394948625280905324741809479105609467145130411264321458676761 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.kmac_lc_escalation.10561721637537644394948625280905324741809479105609467145130411264321458676761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.114061930983766084876207811214099498579226323541998943846144701774092175992142
Short name T550
Test name
Test status
Simulation time 45517522529 ps
CPU time 699.76 seconds
Started Nov 22 01:54:06 PM PST 23
Finished Nov 22 02:05:47 PM PST 23
Peak memory 288268 kb
Host smart-31096169-b2a2-4875-a2ca-a7a07d486f72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114061930983766084876207811214099498579226323541998943846144701774092175992142 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.11406193098376608487620781121409949857922632354199894384614470177409
2175992142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.38055297598616826655609644631248738172864639230983964392426430786769522773802
Short name T579
Test name
Test status
Simulation time 7733092664 ps
CPU time 113.78 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:56:06 PM PST 23
Peak memory 228008 kb
Host smart-e8c938b4-4a9a-46aa-a8a4-835175a9e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38055297598616826655609644631248738172864639230983964392426430786769522773802 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.kmac_sideload.38055297598616826655609644631248738172864639230983964392426430786769522773802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.92664263227557080645884411196012731148949694756145209291956242053885958590531
Short name T127
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.91 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:54:31 PM PST 23
Peak memory 215848 kb
Host smart-b1c17c27-1b3e-45cb-9797-53e88187b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92664263227557080645884411196012731148949694756145209291956242053885958590531 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.kmac_smoke.92664263227557080645884411196012731148949694756145209291956242053885958590531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.36595836186544486284801089514258898875316239288528638334418273446208036589274
Short name T1031
Test name
Test status
Simulation time 41434001626 ps
CPU time 628.16 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 02:03:51 PM PST 23
Peak memory 321732 kb
Host smart-ca1f9c1a-d219-4319-bb8e-36a557c36ae4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=36595836186544486284801089514258898875316239288528638334418273446208036589274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_st
ress_all.36595836186544486284801089514258898875316239288528638334418273446208036589274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.10260110615439157057770046438935372779449586006350931067874571728614633063736
Short name T538
Test name
Test status
Simulation time 298812853 ps
CPU time 4.36 seconds
Started Nov 22 01:53:29 PM PST 23
Finished Nov 22 01:53:35 PM PST 23
Peak memory 215852 kb
Host smart-0d5c7886-bbf9-4a83-a858-a5d3cdb1f8d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10260110615439157057770046438935372779449586006350931
067874571728614633063736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac.10260110615439157057770046438935372779
449586006350931067874571728614633063736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.102221794359110523827340505114604612340418888743874492313487261600891135336322
Short name T126
Test name
Test status
Simulation time 289902210 ps
CPU time 4.22 seconds
Started Nov 22 01:53:25 PM PST 23
Finished Nov 22 01:53:30 PM PST 23
Peak memory 215788 kb
Host smart-8992592c-8d04-48ae-a7b7-4019d8fd304e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10222179435911052382734050511460461234041888874387449
2313487261600891135336322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.10222179435911052382734050511
4604612340418888743874492313487261600891135336322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.64415862734963278694325822186493054697968458955871174077040698727776785894136
Short name T248
Test name
Test status
Simulation time 115269125226 ps
CPU time 1679.9 seconds
Started Nov 22 01:53:21 PM PST 23
Finished Nov 22 02:21:24 PM PST 23
Peak memory 390332 kb
Host smart-9fce66d8-ccbb-46ee-8278-86d4fff27203
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=64415862734963278694325822186493054697968458955871174077040698727776785894136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.kmac_test_vectors_sha3_224.64415862734963278694325822186493054697968458955871174077040698727776785894136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.2964697688343878457664962821457355756515154291289137613046200879241668546567
Short name T199
Test name
Test status
Simulation time 107886220004 ps
CPU time 1648.45 seconds
Started Nov 22 01:53:15 PM PST 23
Finished Nov 22 02:20:50 PM PST 23
Peak memory 370152 kb
Host smart-b0113e25-3181-447e-b26b-e4b0f9e11c77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2964697688343878457664962821457355756515154291289137613046200879241668546567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
kmac_test_vectors_sha3_256.2964697688343878457664962821457355756515154291289137613046200879241668546567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.69883963800518475421449849779542502271505201640110205228485056334910358992479
Short name T274
Test name
Test status
Simulation time 83070954242 ps
CPU time 1180.18 seconds
Started Nov 22 01:53:21 PM PST 23
Finished Nov 22 02:13:04 PM PST 23
Peak memory 332904 kb
Host smart-08e1676c-fd4b-447b-8e09-c30274099dea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=69883963800518475421449849779542502271505201640110205228485056334910358992479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.kmac_test_vectors_sha3_384.69883963800518475421449849779542502271505201640110205228485056334910358992479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.11027250443909743179675497599111454345893485526141036224179251350107504696760
Short name T445
Test name
Test status
Simulation time 58503507926 ps
CPU time 887.64 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 02:08:11 PM PST 23
Peak memory 295908 kb
Host smart-ae82b28f-cceb-49bc-9b98-fb13f3f77b21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11027250443909743179675497599111454345893485526141036224179251350107504696760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.kmac_test_vectors_sha3_512.11027250443909743179675497599111454345893485526141036224179251350107504696760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.1037035046229036229717152067154159799325417472254027102806444089308492131981
Short name T1060
Test name
Test status
Simulation time 307766781661 ps
CPU time 4349.18 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 03:05:53 PM PST 23
Peak memory 653336 kb
Host smart-7e2a6ae1-5225-480d-9b28-b60f744c971d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1037035046229036229717152067154159799325417472254027102806444089308492131981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.kmac_test_vectors_shake_128.1037035046229036229717152067154159799325417472254027102806444089308492131981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.99874049284711081936011948934948508348016811692129750963305877991063238654973
Short name T957
Test name
Test status
Simulation time 258047411562 ps
CPU time 3589.02 seconds
Started Nov 22 01:53:04 PM PST 23
Finished Nov 22 02:52:54 PM PST 23
Peak memory 556300 kb
Host smart-fa653a32-a7f8-4c70-bc3c-9d7af9f49ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=99874049284711081936011948934948508348016811692129750963305877991063238654973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.kmac_test_vectors_shake_256.99874049284711081936011948934948508348016811692129750963305877991063238654973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.83319489112947176927955664864751515681887344477100407703607835838816281692484
Short name T164
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:52:58 PM PST 23
Finished Nov 22 01:53:00 PM PST 23
Peak memory 205352 kb
Host smart-60bcc9ec-ba33-4ce7-b8fc-27d626df6f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83319489112947176927955664864751515681887344477100407703607835838816281692484 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.kmac_alert_test.83319489112947176927955664864751515681887344477100407703607835838816281692484 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.71967165266295950490148816041025130040579981092721735264439434756928903739598
Short name T520
Test name
Test status
Simulation time 5659537824 ps
CPU time 72.85 seconds
Started Nov 22 01:53:02 PM PST 23
Finished Nov 22 01:54:16 PM PST 23
Peak memory 227372 kb
Host smart-dd4d5a51-9e6a-4d91-bf36-33ba21372c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71967165266295950490148816041025130040579981092721735264439434756928903739598 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.kmac_app.71967165266295950490148816041025130040579981092721735264439434756928903739598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.47731934738830445474433338520999966352633103563195270046164303734609854217622
Short name T115
Test name
Test status
Simulation time 14812750312 ps
CPU time 248.91 seconds
Started Nov 22 01:53:04 PM PST 23
Finished Nov 22 01:57:14 PM PST 23
Peak memory 225536 kb
Host smart-8ed185d3-e29c-493e-ae5d-3142a8dd6d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47731934738830445474433338520999966352633103563195270046164303734609854217622 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.kmac_burst_write.47731934738830445474433338520999966352633103563195270046164303734609854217622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.16774455291481301183733170209577633978589068360552638107669743570775187588797
Short name T1007
Test name
Test status
Simulation time 2342046507 ps
CPU time 34.17 seconds
Started Nov 22 01:52:57 PM PST 23
Finished Nov 22 01:53:32 PM PST 23
Peak memory 223840 kb
Host smart-dc4cf028-6b09-4542-b6d8-77e3c81719d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=16774455291481301183733170209577633978589068360552638107669743570775187588797 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.kmac_edn_timeout_error.16774455291481301183733170209577633978589068360552638107669743570775187588797 +enable_masking=0
+sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.29360263613012223258679705780823682825859557599773707497270406670143446688717
Short name T227
Test name
Test status
Simulation time 2211297553 ps
CPU time 29.86 seconds
Started Nov 22 01:53:22 PM PST 23
Finished Nov 22 01:53:54 PM PST 23
Peak memory 223896 kb
Host smart-b91003fe-dfb8-4ed6-9f5f-358ac71209b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=29360263613012223258679705780823682825859557599773707497270406670143446688717 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.29360263613012223258679705780823682825859557599773707497270406670143446688717 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.77985169662191384492350044262082134311880800123221428776246759237424847428308
Short name T536
Test name
Test status
Simulation time 6743332725 ps
CPU time 76.1 seconds
Started Nov 22 01:52:59 PM PST 23
Finished Nov 22 01:54:16 PM PST 23
Peak memory 226988 kb
Host smart-fc61465e-7671-4b86-8618-a1458e74a98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77985169662191384492350044262082134311880800123221428776246759237424847428308 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.kmac_entropy_refresh.77985169662191384492350044262082134311880800123221428776246759237424847428308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.35388856756147813964622754593513862859130116164502510618372316883877096743130
Short name T742
Test name
Test status
Simulation time 8615085608 ps
CPU time 126.16 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 248576 kb
Host smart-43c8ae21-2ef7-4493-983d-fb8e4b641749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35388856756147813964622754593513862859130116164502510618372316883877096743130 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.kmac_error.35388856756147813964622754593513862859130116164502510618372316883877096743130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.74844755953451943386165003386087369070362184522650718417468595311074889216992
Short name T754
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.28 seconds
Started Nov 22 01:53:18 PM PST 23
Finished Nov 22 01:53:28 PM PST 23
Peak memory 207492 kb
Host smart-ff5a89fe-0072-4346-80ac-6541fa9a2fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74844755953451943386165003386087369070362184522650718417468595311074889216992 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.kmac_key_error.74844755953451943386165003386087369070362184522650718417468595311074889216992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.11789535214248334209922504667839517166040142314008632916827649412729017074765
Short name T841
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:53:25 PM PST 23
Peak memory 215676 kb
Host smart-51690218-586d-4756-9d95-b35cc2308e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11789535214248334209922504667839517166040142314008632916827649412729017074765 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.kmac_lc_escalation.11789535214248334209922504667839517166040142314008632916827649412729017074765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.15803355663026369519347518006002672141157297626130303700798534917797875952227
Short name T303
Test name
Test status
Simulation time 45517522529 ps
CPU time 697.22 seconds
Started Nov 22 01:53:01 PM PST 23
Finished Nov 22 02:04:39 PM PST 23
Peak memory 288216 kb
Host smart-0792414c-8434-42db-b0b4-b86c42946b5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15803355663026369519347518006002672141157297626130303700798534917797875952227 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.158033556630263695193475180060026721411572976261303037007985349177978
75952227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.39890490867130212681383592916757919567975988167135700866052735145455317816089
Short name T511
Test name
Test status
Simulation time 7733092664 ps
CPU time 110.45 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:55:13 PM PST 23
Peak memory 227956 kb
Host smart-0b5dffa8-9e55-4938-8db4-fcf4ac91de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39890490867130212681383592916757919567975988167135700866052735145455317816089 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.kmac_sideload.39890490867130212681383592916757919567975988167135700866052735145455317816089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.96762333285773605475969063899108196972102024480650320312164711724669721269753
Short name T145
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.07 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 215972 kb
Host smart-18e5b074-3c45-416d-b76c-9b20242368cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96762333285773605475969063899108196972102024480650320312164711724669721269753 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.kmac_smoke.96762333285773605475969063899108196972102024480650320312164711724669721269753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.13414878699273376232949629951420837002810617989712388197787135253186505464313
Short name T554
Test name
Test status
Simulation time 298812853 ps
CPU time 4.29 seconds
Started Nov 22 01:53:12 PM PST 23
Finished Nov 22 01:53:21 PM PST 23
Peak memory 215848 kb
Host smart-82c64d88-8d74-4ddd-8c08-b94ebd3aa24c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414878699273376232949629951420837002810617989712388
197787135253186505464313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac.13414878699273376232949629951420837002
810617989712388197787135253186505464313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.95629340486011293736840096472320663885505223221958771422661764467121301414455
Short name T627
Test name
Test status
Simulation time 289902210 ps
CPU time 4.15 seconds
Started Nov 22 01:53:30 PM PST 23
Finished Nov 22 01:53:35 PM PST 23
Peak memory 215696 kb
Host smart-006525fb-b2ea-422e-8575-e150ffa8a339
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95629340486011293736840096472320663885505223221958771
422661764467121301414455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.956293404860112937368400964723
20663885505223221958771422661764467121301414455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.21273224857105229368938803073604384985619366401204753823523023970436707008461
Short name T259
Test name
Test status
Simulation time 115269125226 ps
CPU time 1714.23 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 02:21:30 PM PST 23
Peak memory 390332 kb
Host smart-ae54b669-4732-4739-93ff-270253d8f69b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=21273224857105229368938803073604384985619366401204753823523023970436707008461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_224.21273224857105229368938803073604384985619366401204753823523023970436707008461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.38417848148506498171456636875443752761673203897882395548610484626193268231534
Short name T652
Test name
Test status
Simulation time 107886220004 ps
CPU time 1660.19 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 02:21:04 PM PST 23
Peak memory 370148 kb
Host smart-9910ca74-ace1-4de9-bd3e-628a5f5ffd58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38417848148506498171456636875443752761673203897882395548610484626193268231534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_256.38417848148506498171456636875443752761673203897882395548610484626193268231534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.55340789032889979792800178103385530949747042205982782842277868456066848823692
Short name T149
Test name
Test status
Simulation time 83070954242 ps
CPU time 1283.29 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 02:14:47 PM PST 23
Peak memory 332864 kb
Host smart-3f38ad27-7193-404f-855d-a082ad2f623c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55340789032889979792800178103385530949747042205982782842277868456066848823692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_384.55340789032889979792800178103385530949747042205982782842277868456066848823692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.64463465803415682100477593428836107688480318497859322660634959538051319577290
Short name T487
Test name
Test status
Simulation time 58503507926 ps
CPU time 882.93 seconds
Started Nov 22 01:53:00 PM PST 23
Finished Nov 22 02:07:44 PM PST 23
Peak memory 295888 kb
Host smart-82d87341-3174-4d9d-a56b-7998a74930ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=64463465803415682100477593428836107688480318497859322660634959538051319577290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.kmac_test_vectors_sha3_512.64463465803415682100477593428836107688480318497859322660634959538051319577290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.29590359122429687999748350769016624747869128216198595676321625607125552851777
Short name T122
Test name
Test status
Simulation time 307766781661 ps
CPU time 4583.76 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 03:09:47 PM PST 23
Peak memory 653224 kb
Host smart-c7406b04-b2d7-4dde-bc39-1e314b5e5708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=29590359122429687999748350769016624747869128216198595676321625607125552851777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.kmac_test_vectors_shake_128.29590359122429687999748350769016624747869128216198595676321625607125552851777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.115277556933829350820606326417034349888640141358601498470256911943240724390360
Short name T239
Test name
Test status
Simulation time 258047411562 ps
CPU time 3720.37 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 02:55:18 PM PST 23
Peak memory 556276 kb
Host smart-f93c7a61-e576-4299-b230-bb4a60389047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=115277556933829350820606326417034349888640141358601498470256911943240724390360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.kmac_test_vectors_shake_256.115277556933829350820606326417034349888640141358601498470256911943240724390360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.31660284770900367607853471211513679049319323344326013857729894714320151514603
Short name T705
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 01:53:37 PM PST 23
Peak memory 205224 kb
Host smart-21ec08af-1fcc-411f-8b6b-dd51f6a2d2e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660284770900367607853471211513679049319323344326013857729894714320151514603 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.kmac_alert_test.31660284770900367607853471211513679049319323344326013857729894714320151514603 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.20620712775277495397765322544147893125512275857011541251852769030462065726517
Short name T384
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.31 seconds
Started Nov 22 01:53:18 PM PST 23
Finished Nov 22 01:54:39 PM PST 23
Peak memory 227404 kb
Host smart-30b231c7-2bf4-4b5c-aa3b-a88b2a3f514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20620712775277495397765322544147893125512275857011541251852769030462065726517 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.kmac_app.20620712775277495397765322544147893125512275857011541251852769030462065726517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.108793202723644523715578782154975721670730734441222981170562141335240823247079
Short name T189
Test name
Test status
Simulation time 14812750312 ps
CPU time 245.09 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 01:57:28 PM PST 23
Peak memory 225508 kb
Host smart-e1298c0a-7f4a-47f2-b973-1ffb5a20577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108793202723644523715578782154975721670730734441222981170562141335240823247079 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.kmac_burst_write.108793202723644523715578782154975721670730734441222981170562141335240823247079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.13489870220643001023231139829537622940703932403462350593370660771668542987042
Short name T732
Test name
Test status
Simulation time 2342046507 ps
CPU time 33.84 seconds
Started Nov 22 01:53:25 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 223808 kb
Host smart-c59abcda-4d68-4ca9-b634-2871e8cdae09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13489870220643001023231139829537622940703932403462350593370660771668542987042 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.kmac_edn_timeout_error.13489870220643001023231139829537622940703932403462350593370660771668542987042 +enable_masking=0
+sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.79735389371102744752756657160753620984831212748592437177613927817366109736339
Short name T1015
Test name
Test status
Simulation time 2211297553 ps
CPU time 29.33 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:54:12 PM PST 23
Peak memory 223852 kb
Host smart-104a29ce-c2f9-4c80-8ad2-0b199871320e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=79735389371102744752756657160753620984831212748592437177613927817366109736339 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.79735389371102744752756657160753620984831212748592437177613927817366109736339 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.39035575055594968269179536312090949729563055498865658711599758725041161667609
Short name T708
Test name
Test status
Simulation time 6743332725 ps
CPU time 74.93 seconds
Started Nov 22 01:53:17 PM PST 23
Finished Nov 22 01:54:38 PM PST 23
Peak memory 227040 kb
Host smart-6f0fc142-5c94-47a8-b45e-7aa6fd69fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39035575055594968269179536312090949729563055498865658711599758725041161667609 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.kmac_entropy_refresh.39035575055594968269179536312090949729563055498865658711599758725041161667609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.84641189139276412415730113294088914895460332770939295281857493090023136943883
Short name T590
Test name
Test status
Simulation time 8615085608 ps
CPU time 138.08 seconds
Started Nov 22 01:53:00 PM PST 23
Finished Nov 22 01:55:19 PM PST 23
Peak memory 248560 kb
Host smart-729db6bc-9b16-4808-a6b4-c1ade697f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84641189139276412415730113294088914895460332770939295281857493090023136943883 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.kmac_error.84641189139276412415730113294088914895460332770939295281857493090023136943883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.95623946647739096352995011881838837591796853239080358098124877834654659599732
Short name T499
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.28 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:53:53 PM PST 23
Peak memory 207540 kb
Host smart-5a3dfaa3-d5fa-4766-8405-793fbf0b9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95623946647739096352995011881838837591796853239080358098124877834654659599732 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.kmac_key_error.95623946647739096352995011881838837591796853239080358098124877834654659599732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2391448627332165740214893109116930623866883952146616285843750184773655712640
Short name T924
Test name
Test status
Simulation time 58171921 ps
CPU time 1.26 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:53:41 PM PST 23
Peak memory 215752 kb
Host smart-ff102498-d75f-4120-a8f3-0cc269e0f3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391448627332165740214893109116930623866883952146616285843750184773655712640 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.kmac_lc_escalation.2391448627332165740214893109116930623866883952146616285843750184773655712640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.63942906406167102135805419872907415538580940975639083333282511865714339737172
Short name T443
Test name
Test status
Simulation time 45517522529 ps
CPU time 740.45 seconds
Started Nov 22 01:53:34 PM PST 23
Finished Nov 22 02:05:56 PM PST 23
Peak memory 288364 kb
Host smart-39c68118-3bb4-4781-a236-a01e06a557fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63942906406167102135805419872907415538580940975639083333282511865714339737172 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.639429064061671021358054198729074155385809409756390833332825118657143
39737172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.28118877807704344744387732669934398081695805805102677242988441317795139303450
Short name T850
Test name
Test status
Simulation time 7733092664 ps
CPU time 109.79 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:55:14 PM PST 23
Peak memory 228136 kb
Host smart-d6242a56-dfd8-40ab-8ac4-5c38887d1c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28118877807704344744387732669934398081695805805102677242988441317795139303450 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.kmac_sideload.28118877807704344744387732669934398081695805805102677242988441317795139303450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.29500567900641318955652623301463120105471290158824182487569624207745492018070
Short name T262
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.54 seconds
Started Nov 22 01:53:34 PM PST 23
Finished Nov 22 01:53:53 PM PST 23
Peak memory 215796 kb
Host smart-2f496770-3184-4ac9-b237-624f8daecdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29500567900641318955652623301463120105471290158824182487569624207745492018070 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.kmac_smoke.29500567900641318955652623301463120105471290158824182487569624207745492018070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.29386288362424968645710415234123841797391953158411303973043211178892377488970
Short name T331
Test name
Test status
Simulation time 41434001626 ps
CPU time 624.7 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 02:04:01 PM PST 23
Peak memory 321652 kb
Host smart-ad1f1a79-ea83-422c-a5ba-23db9561877f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=29386288362424968645710415234123841797391953158411303973043211178892377488970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_st
ress_all.29386288362424968645710415234123841797391953158411303973043211178892377488970 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.38326900541277123905689586152597467292138884212993400663444009406421642533861
Short name T203
Test name
Test status
Simulation time 298812853 ps
CPU time 4.18 seconds
Started Nov 22 01:53:12 PM PST 23
Finished Nov 22 01:53:21 PM PST 23
Peak memory 215860 kb
Host smart-1feca504-c721-4c60-ade5-ef3b7b360663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326900541277123905689586152597467292138884212993400
663444009406421642533861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac.38326900541277123905689586152597467292
138884212993400663444009406421642533861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.66997923966688578212960864180336494558190900901199701955086445898920652211346
Short name T591
Test name
Test status
Simulation time 289902210 ps
CPU time 4.09 seconds
Started Nov 22 01:53:01 PM PST 23
Finished Nov 22 01:53:06 PM PST 23
Peak memory 215688 kb
Host smart-399d33f6-d3d1-4449-95dc-a3e49e3e4769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66997923966688578212960864180336494558190900901199701
955086445898920652211346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.669979239666885782129608641803
36494558190900901199701955086445898920652211346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.45198725003258536863210996562643007258534232527682540213871758043412078803244
Short name T1058
Test name
Test status
Simulation time 115269125226 ps
CPU time 1729.63 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 390360 kb
Host smart-be9b5460-8c8c-42fb-bcac-a7f385646c57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45198725003258536863210996562643007258534232527682540213871758043412078803244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.kmac_test_vectors_sha3_224.45198725003258536863210996562643007258534232527682540213871758043412078803244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.6465521048067578412580566865822279592111862726538894189920711970097637251747
Short name T793
Test name
Test status
Simulation time 107886220004 ps
CPU time 1580.98 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 02:19:57 PM PST 23
Peak memory 370100 kb
Host smart-a987acc2-5a71-49c5-ab91-d35320540e38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=6465521048067578412580566865822279592111862726538894189920711970097637251747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
kmac_test_vectors_sha3_256.6465521048067578412580566865822279592111862726538894189920711970097637251747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.114967194226807768014701736964235715915322989770631989099981942624969931700211
Short name T605
Test name
Test status
Simulation time 83070954242 ps
CPU time 1232.45 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 02:13:55 PM PST 23
Peak memory 332932 kb
Host smart-21d5998d-b852-4502-a218-3cdc13d01b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114967194226807768014701736964235715915322989770631989099981942624969931700211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.kmac_test_vectors_sha3_384.114967194226807768014701736964235715915322989770631989099981942624969931700211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.55529898386692824042850234944878696266090333613047447852245934103798696662023
Short name T638
Test name
Test status
Simulation time 58503507926 ps
CPU time 860.87 seconds
Started Nov 22 01:53:04 PM PST 23
Finished Nov 22 02:07:25 PM PST 23
Peak memory 295872 kb
Host smart-67f3c2a0-06c1-40cd-b81b-c664d1814f1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55529898386692824042850234944878696266090333613047447852245934103798696662023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.kmac_test_vectors_sha3_512.55529898386692824042850234944878696266090333613047447852245934103798696662023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.114986296652545365186607179311962809384775827212851760936834263040494085759953
Short name T785
Test name
Test status
Simulation time 258047411562 ps
CPU time 3728.06 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 02:55:05 PM PST 23
Peak memory 556320 kb
Host smart-8071c50e-352f-4394-b0f8-3f1313809fec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=114986296652545365186607179311962809384775827212851760936834263040494085759953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.kmac_test_vectors_shake_256.114986296652545365186607179311962809384775827212851760936834263040494085759953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.34035276537372736822588362950358198328454688881019312840563951404795610055454
Short name T642
Test name
Test status
Simulation time 21118646 ps
CPU time 0.77 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 01:53:58 PM PST 23
Peak memory 205236 kb
Host smart-3d388275-9a10-464e-af99-d3b6fdd20c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34035276537372736822588362950358198328454688881019312840563951404795610055454 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.kmac_alert_test.34035276537372736822588362950358198328454688881019312840563951404795610055454 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.91932356038042685618082518799116741160968145166413409366862619399840258293592
Short name T580
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.62 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:54:58 PM PST 23
Peak memory 227268 kb
Host smart-e3863440-63fb-4aa9-955b-90f7381bb68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91932356038042685618082518799116741160968145166413409366862619399840258293592 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.kmac_app.91932356038042685618082518799116741160968145166413409366862619399840258293592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.94564738951919573428185884276799055835725094926961423959422248069101616328490
Short name T116
Test name
Test status
Simulation time 14812750312 ps
CPU time 243.44 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:58:12 PM PST 23
Peak memory 225592 kb
Host smart-a592abb2-ef93-421b-8f05-fb94ef367c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94564738951919573428185884276799055835725094926961423959422248069101616328490 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.kmac_burst_write.94564738951919573428185884276799055835725094926961423959422248069101616328490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.4510770404127012329859794596553026635490571109289960515640691342877461590260
Short name T213
Test name
Test status
Simulation time 2342046507 ps
CPU time 33.21 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 01:53:57 PM PST 23
Peak memory 223884 kb
Host smart-6b33e0e8-1370-4a78-8f9b-51c7acbcfec3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4510770404127012329859794596553026635490571109289960515640691342877461590260 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.kmac_edn_timeout_error.4510770404127012329859794596553026635490571109289960515640691342877461590260 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.75571835431712284923561213539944727081318854943657114759100098173501772899506
Short name T1048
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.15 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:54:18 PM PST 23
Peak memory 223896 kb
Host smart-6eac2ded-0b1a-4eb6-9344-013287120534
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=75571835431712284923561213539944727081318854943657114759100098173501772899506 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.75571835431712284923561213539944727081318854943657114759100098173501772899506 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.37977420080423163594725445475288212228778741150710853420158015755261524593885
Short name T363
Test name
Test status
Simulation time 6743332725 ps
CPU time 75.28 seconds
Started Nov 22 01:53:25 PM PST 23
Finished Nov 22 01:54:42 PM PST 23
Peak memory 226964 kb
Host smart-69cba64b-cb07-4072-8cb7-3b0d2dfb8f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37977420080423163594725445475288212228778741150710853420158015755261524593885 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.kmac_entropy_refresh.37977420080423163594725445475288212228778741150710853420158015755261524593885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.67908038954566176350850499608849720116354443158705597785662069316217713784010
Short name T481
Test name
Test status
Simulation time 8615085608 ps
CPU time 129.6 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 01:55:47 PM PST 23
Peak memory 248640 kb
Host smart-f80be5b9-c025-4d6b-8595-0cb69002c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67908038954566176350850499608849720116354443158705597785662069316217713784010 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.kmac_error.67908038954566176350850499608849720116354443158705597785662069316217713784010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.19773548332643108269026274697720036682541881776335448913901497381862119146707
Short name T817
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.3 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 01:53:56 PM PST 23
Peak memory 207508 kb
Host smart-dc670247-da19-4c4f-a3d7-6ed360229b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19773548332643108269026274697720036682541881776335448913901497381862119146707 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.kmac_key_error.19773548332643108269026274697720036682541881776335448913901497381862119146707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.91996090784595664113480685431023854036743900461310432671128955792848163633461
Short name T364
Test name
Test status
Simulation time 58171921 ps
CPU time 1.23 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 01:53:38 PM PST 23
Peak memory 215680 kb
Host smart-ca008065-be4c-46be-920d-3f8d6a006913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91996090784595664113480685431023854036743900461310432671128955792848163633461 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.kmac_lc_escalation.91996090784595664113480685431023854036743900461310432671128955792848163633461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.33280782499125713717607002862934916999740234495059197952535291647190987526314
Short name T769
Test name
Test status
Simulation time 45517522529 ps
CPU time 726.54 seconds
Started Nov 22 01:53:29 PM PST 23
Finished Nov 22 02:05:37 PM PST 23
Peak memory 288468 kb
Host smart-668c3983-9499-45a8-a231-9a3bff9ae095
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280782499125713717607002862934916999740234495059197952535291647190987526314 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.332807824991257137176070028629349169997402344950591979525352916471909
87526314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.82487483624328265271644283428565537839877221830023398126102087710430971103955
Short name T931
Test name
Test status
Simulation time 7733092664 ps
CPU time 113.55 seconds
Started Nov 22 01:53:23 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 228112 kb
Host smart-d6433729-1864-46bc-8608-4554b9e72c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82487483624328265271644283428565537839877221830023398126102087710430971103955 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.kmac_sideload.82487483624328265271644283428565537839877221830023398126102087710430971103955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.87531123787050937966344897961023029888212950777349774201095508140424687927771
Short name T1074
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.77 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:53:42 PM PST 23
Peak memory 215736 kb
Host smart-0d0c933b-3f29-4b24-a2bf-9649cb44772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87531123787050937966344897961023029888212950777349774201095508140424687927771 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.kmac_smoke.87531123787050937966344897961023029888212950777349774201095508140424687927771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.101340364534367793801560825022937674768655111324572371606213109360378453396726
Short name T788
Test name
Test status
Simulation time 41434001626 ps
CPU time 611.59 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 02:04:11 PM PST 23
Peak memory 321720 kb
Host smart-6107d521-19b4-4f7b-b3e8-3efe915e2c3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=101340364534367793801560825022937674768655111324572371606213109360378453396726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_s
tress_all.101340364534367793801560825022937674768655111324572371606213109360378453396726 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.83645378946958609557501765935684348519950586063828167099872739837342300313876
Short name T232
Test name
Test status
Simulation time 298812853 ps
CPU time 4.31 seconds
Started Nov 22 01:53:22 PM PST 23
Finished Nov 22 01:53:29 PM PST 23
Peak memory 215812 kb
Host smart-55c6c0c1-58bc-4f78-891f-2ba67d2e29b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83645378946958609557501765935684348519950586063828167
099872739837342300313876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac.83645378946958609557501765935684348519
950586063828167099872739837342300313876 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.112150616324673688162093451667663340156295354113685115101752431686038929496698
Short name T564
Test name
Test status
Simulation time 289902210 ps
CPU time 4.24 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:53:48 PM PST 23
Peak memory 215768 kb
Host smart-46138441-2488-40c1-8cd7-1484eba09a5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215061632467368816209345166766334015629535411368511
5101752431686038929496698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac_xof.11215061632467368816209345166
7663340156295354113685115101752431686038929496698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.37997459963210376611464370534046716859503159590820904565713081202107046281702
Short name T140
Test name
Test status
Simulation time 115269125226 ps
CPU time 1646.85 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 02:20:51 PM PST 23
Peak memory 390356 kb
Host smart-3e02dbb3-a687-44d2-ac73-81860b204ee9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=37997459963210376611464370534046716859503159590820904565713081202107046281702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.kmac_test_vectors_sha3_224.37997459963210376611464370534046716859503159590820904565713081202107046281702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.87419768681286110123952040382946784482572068563516571302646626954325266616148
Short name T132
Test name
Test status
Simulation time 107886220004 ps
CPU time 1698.34 seconds
Started Nov 22 01:53:21 PM PST 23
Finished Nov 22 02:21:43 PM PST 23
Peak memory 370056 kb
Host smart-5629aebc-97ba-4d53-a27a-f56bbdfc13f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=87419768681286110123952040382946784482572068563516571302646626954325266616148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.kmac_test_vectors_sha3_256.87419768681286110123952040382946784482572068563516571302646626954325266616148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.7538340527011265856444118130868770843368866170778750290534802711952406945150
Short name T505
Test name
Test status
Simulation time 83070954242 ps
CPU time 1186.25 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 02:13:10 PM PST 23
Peak memory 333000 kb
Host smart-d5092a67-ded3-4751-9788-579f2acda179
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=7538340527011265856444118130868770843368866170778750290534802711952406945150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
kmac_test_vectors_sha3_384.7538340527011265856444118130868770843368866170778750290534802711952406945150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.101894934947420760717098447070927279972684047657979309493667861262545059388556
Short name T221
Test name
Test status
Simulation time 58503507926 ps
CPU time 858.01 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 02:08:05 PM PST 23
Peak memory 295864 kb
Host smart-9c5a3edf-ed5c-48a3-973b-8cb0a93a8d46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=101894934947420760717098447070927279972684047657979309493667861262545059388556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.kmac_test_vectors_sha3_512.101894934947420760717098447070927279972684047657979309493667861262545059388556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.53829234650202657940340639900116285658903502734699831389843534892826553814405
Short name T121
Test name
Test status
Simulation time 307766781661 ps
CPU time 4588.07 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 03:10:05 PM PST 23
Peak memory 653236 kb
Host smart-36359db5-e4c2-41e2-a4e8-d04d08e060e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=53829234650202657940340639900116285658903502734699831389843534892826553814405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.kmac_test_vectors_shake_128.53829234650202657940340639900116285658903502734699831389843534892826553814405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.27710419053203330199430356023731557936736662997713544173912095513471277445250
Short name T468
Test name
Test status
Simulation time 258047411562 ps
CPU time 3595.49 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 02:53:35 PM PST 23
Peak memory 556320 kb
Host smart-833602d7-7ef4-4a0a-a801-77b11b044e6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=27710419053203330199430356023731557936736662997713544173912095513471277445250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.kmac_test_vectors_shake_256.27710419053203330199430356023731557936736662997713544173912095513471277445250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.7095398083462007496388934563589707423029951202286660844593812081386742958507
Short name T399
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:54:09 PM PST 23
Finished Nov 22 01:54:11 PM PST 23
Peak memory 205228 kb
Host smart-106e31d9-6581-474d-ac1e-638f92eb2103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7095398083462007496388934563589707423029951202286660844593812081386742958507 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.kmac_alert_test.7095398083462007496388934563589707423029951202286660844593812081386742958507 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.64528792419324096412734316662919018289187489997248045774136398475124587503574
Short name T943
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.47 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:55:31 PM PST 23
Peak memory 227332 kb
Host smart-c79fd623-dc34-45e3-a36d-3f6a9bbfdd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64528792419324096412734316662919018289187489997248045774136398475124587503574 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.kmac_app.64528792419324096412734316662919018289187489997248045774136398475124587503574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.99296575120161517109572886961568948898571976099956071934300719743947637302480
Short name T770
Test name
Test status
Simulation time 14812750312 ps
CPU time 230.74 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 01:57:42 PM PST 23
Peak memory 225492 kb
Host smart-52bb0f41-ac24-415f-8c5e-77f07eeb0c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99296575120161517109572886961568948898571976099956071934300719743947637302480 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.kmac_burst_write.99296575120161517109572886961568948898571976099956071934300719743947637302480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.49625111712195453983299870325923313679782818073989086235167744169067838159540
Short name T906
Test name
Test status
Simulation time 2342046507 ps
CPU time 34.68 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:54:22 PM PST 23
Peak memory 223808 kb
Host smart-5c4db10d-6310-4b88-a6b1-d20cb8920cc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49625111712195453983299870325923313679782818073989086235167744169067838159540 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.kmac_edn_timeout_error.49625111712195453983299870325923313679782818073989086235167744169067838159540 +enable_masking=0
+sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.78814666960238246760682991365386650451927736229661093835174140906944474511017
Short name T792
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.82 seconds
Started Nov 22 01:54:14 PM PST 23
Finished Nov 22 01:54:46 PM PST 23
Peak memory 223840 kb
Host smart-3c38e39c-3307-470d-b0e8-ee598ccbbcc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78814666960238246760682991365386650451927736229661093835174140906944474511017 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.78814666960238246760682991365386650451927736229661093835174140906944474511017 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.12069375885884404405761355635177324138722045876395159439507774734464032119258
Short name T588
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.08 seconds
Started Nov 22 01:54:01 PM PST 23
Finished Nov 22 01:55:16 PM PST 23
Peak memory 226968 kb
Host smart-3bc146d0-fe1d-4826-af56-b7cdb44257a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12069375885884404405761355635177324138722045876395159439507774734464032119258 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.kmac_entropy_refresh.12069375885884404405761355635177324138722045876395159439507774734464032119258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.94315142875606597882822188443433996791654011755124405106393594757259761407189
Short name T897
Test name
Test status
Simulation time 8615085608 ps
CPU time 129.59 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 01:56:16 PM PST 23
Peak memory 248572 kb
Host smart-9ae14631-0d20-42df-8882-e2a9107a4fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94315142875606597882822188443433996791654011755124405106393594757259761407189 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.kmac_error.94315142875606597882822188443433996791654011755124405106393594757259761407189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.89209134216119861751896188291561226602414722895963931790304139591974038277274
Short name T648
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.28 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 01:54:16 PM PST 23
Peak memory 207516 kb
Host smart-5da356eb-4643-47b6-b4b3-81b5a67f4240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89209134216119861751896188291561226602414722895963931790304139591974038277274 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.kmac_key_error.89209134216119861751896188291561226602414722895963931790304139591974038277274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.34888143899105028098396991469604295162650420945345057240228505725660998621673
Short name T934
Test name
Test status
Simulation time 58171921 ps
CPU time 1.17 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:54:15 PM PST 23
Peak memory 215736 kb
Host smart-71c98f57-c81b-4f65-99eb-8c2009627576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34888143899105028098396991469604295162650420945345057240228505725660998621673 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.kmac_lc_escalation.34888143899105028098396991469604295162650420945345057240228505725660998621673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.93494236171280696456310329532862796577915586935693888927802758640629699117926
Short name T939
Test name
Test status
Simulation time 45517522529 ps
CPU time 688.81 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 02:05:21 PM PST 23
Peak memory 288304 kb
Host smart-4af924cc-9a33-43dd-9128-537c59ffc933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93494236171280696456310329532862796577915586935693888927802758640629699117926 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.934942361712806964563103295328627965779155869356938889278027586406296
99117926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.13813849055172237971972582721284352428903197719342358046950235268539421082805
Short name T282
Test name
Test status
Simulation time 7733092664 ps
CPU time 107.78 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 01:55:35 PM PST 23
Peak memory 228020 kb
Host smart-c2e0675e-fbd2-410d-9dc0-2d1f1186decf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13813849055172237971972582721284352428903197719342358046950235268539421082805 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.kmac_sideload.13813849055172237971972582721284352428903197719342358046950235268539421082805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.102439799619340429018578570728396045137815519404035000308044660331893816820268
Short name T905
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.93 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 215988 kb
Host smart-22df617b-a835-4529-825b-ca46c442923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102439799619340429018578570728396045137815519404035000308044660331893816820268 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.kmac_smoke.102439799619340429018578570728396045137815519404035000308044660331893816820268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.77592379947166222207667673778258214553600871188310814558135419624569108582237
Short name T276
Test name
Test status
Simulation time 41434001626 ps
CPU time 613.24 seconds
Started Nov 22 01:53:59 PM PST 23
Finished Nov 22 02:04:13 PM PST 23
Peak memory 321600 kb
Host smart-44939e40-e41e-457f-b1d7-305f32124432
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=77592379947166222207667673778258214553600871188310814558135419624569108582237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_st
ress_all.77592379947166222207667673778258214553600871188310814558135419624569108582237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.97998561900984716057568560439312098137187492344953423302643036102072565001034
Short name T74
Test name
Test status
Simulation time 298812853 ps
CPU time 4.29 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 01:53:56 PM PST 23
Peak memory 215812 kb
Host smart-5bcb31f0-260a-45a8-b2ac-7910337bd58f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97998561900984716057568560439312098137187492344953423
302643036102072565001034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac.97998561900984716057568560439312098137
187492344953423302643036102072565001034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.82174286026055271806229251018218960528564174675303130339909171168069579680862
Short name T596
Test name
Test status
Simulation time 289902210 ps
CPU time 4.08 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:54:17 PM PST 23
Peak memory 215820 kb
Host smart-4c1cd04a-49d3-4525-b188-bcb949e04de5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82174286026055271806229251018218960528564174675303130
339909171168069579680862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.821742860260552718062292510182
18960528564174675303130339909171168069579680862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.5781223982157779588300368741942410630322110915022797807950858505724744633476
Short name T759
Test name
Test status
Simulation time 115269125226 ps
CPU time 1698.74 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 02:22:06 PM PST 23
Peak memory 390456 kb
Host smart-22e0e9e2-0f3a-4b23-b042-8827430f604f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=5781223982157779588300368741942410630322110915022797807950858505724744633476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
kmac_test_vectors_sha3_224.5781223982157779588300368741942410630322110915022797807950858505724744633476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.107600331108910465015134932834646948140748854294539880647058827223006782660471
Short name T265
Test name
Test status
Simulation time 107886220004 ps
CPU time 1623.74 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 02:20:56 PM PST 23
Peak memory 370168 kb
Host smart-4f518c79-c0ce-42e7-a04c-af345cda9792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=107600331108910465015134932834646948140748854294539880647058827223006782660471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.kmac_test_vectors_sha3_256.107600331108910465015134932834646948140748854294539880647058827223006782660471 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.45823614419036055663092428317288057067346793030397341313399924646071558863901
Short name T224
Test name
Test status
Simulation time 83070954242 ps
CPU time 1262.11 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 02:15:09 PM PST 23
Peak memory 332916 kb
Host smart-5fd6bc08-6162-4cf0-b80e-52974af95201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45823614419036055663092428317288057067346793030397341313399924646071558863901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.kmac_test_vectors_sha3_384.45823614419036055663092428317288057067346793030397341313399924646071558863901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.8599333185276260732738533304372052347108971688969999098752252331341381813091
Short name T153
Test name
Test status
Simulation time 58503507926 ps
CPU time 857.5 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 02:08:19 PM PST 23
Peak memory 295848 kb
Host smart-b39b0889-73b0-454e-a0ac-c2c101b09cae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=8599333185276260732738533304372052347108971688969999098752252331341381813091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
kmac_test_vectors_sha3_512.8599333185276260732738533304372052347108971688969999098752252331341381813091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.307499053443600288593991836119949790467754010911651465387867019148880782083
Short name T168
Test name
Test status
Simulation time 307766781661 ps
CPU time 4336.32 seconds
Started Nov 22 01:54:03 PM PST 23
Finished Nov 22 03:06:21 PM PST 23
Peak memory 653088 kb
Host smart-c35fff82-6d2f-4f54-b600-ced130b37e22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=307499053443600288593991836119949790467754010911651465387867019148880782083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.kmac_test_vectors_shake_128.307499053443600288593991836119949790467754010911651465387867019148880782083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.87810690046209092775578079045466230917623795224723855725332977798953716626479
Short name T439
Test name
Test status
Simulation time 258047411562 ps
CPU time 3701.44 seconds
Started Nov 22 01:54:07 PM PST 23
Finished Nov 22 02:55:50 PM PST 23
Peak memory 556304 kb
Host smart-333da3d8-1595-438f-ae9b-5aab224263e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=87810690046209092775578079045466230917623795224723855725332977798953716626479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.kmac_test_vectors_shake_256.87810690046209092775578079045466230917623795224723855725332977798953716626479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.91081477243647171618171482904712628843848220780365171332074450610416029160146
Short name T392
Test name
Test status
Simulation time 21118646 ps
CPU time 0.72 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 205208 kb
Host smart-e3939cf9-d465-4a9f-82ca-8c6c1f2a4b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91081477243647171618171482904712628843848220780365171332074450610416029160146 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.kmac_alert_test.91081477243647171618171482904712628843848220780365171332074450610416029160146 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.67287496522333039099341828323329573259383413297875190624278160971907748203534
Short name T344
Test name
Test status
Simulation time 5659537824 ps
CPU time 79.27 seconds
Started Nov 22 01:54:21 PM PST 23
Finished Nov 22 01:55:46 PM PST 23
Peak memory 227392 kb
Host smart-35935463-8498-428d-836e-1ce5dfd82758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67287496522333039099341828323329573259383413297875190624278160971907748203534 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.kmac_app.67287496522333039099341828323329573259383413297875190624278160971907748203534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.17206976938590810063948859251255458336837876869165041929642054143030796495621
Short name T501
Test name
Test status
Simulation time 14812750312 ps
CPU time 240.27 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:58:09 PM PST 23
Peak memory 225572 kb
Host smart-7580dcca-09e3-49ba-8b70-1d4c8b42fbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17206976938590810063948859251255458336837876869165041929642054143030796495621 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.kmac_burst_write.17206976938590810063948859251255458336837876869165041929642054143030796495621 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.68583056915744673117458743385905618948943751439064074311390723179274002175642
Short name T255
Test name
Test status
Simulation time 2342046507 ps
CPU time 34.55 seconds
Started Nov 22 01:53:22 PM PST 23
Finished Nov 22 01:53:59 PM PST 23
Peak memory 223892 kb
Host smart-9e8cd9af-4691-41f3-a538-2958c2d8072f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=68583056915744673117458743385905618948943751439064074311390723179274002175642 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.kmac_edn_timeout_error.68583056915744673117458743385905618948943751439064074311390723179274002175642 +enable_masking=0
+sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.82256363075189744501798228066520484776758208896162675240079607197556939740642
Short name T285
Test name
Test status
Simulation time 2211297553 ps
CPU time 29.43 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:54:16 PM PST 23
Peak memory 223852 kb
Host smart-4e3b786a-2267-4a9a-b3b8-e405e16dd076
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=82256363075189744501798228066520484776758208896162675240079607197556939740642 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.82256363075189744501798228066520484776758208896162675240079607197556939740642 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.110521862849601499759762123224077799510167416076066063901284981019815815706157
Short name T422
Test name
Test status
Simulation time 6743332725 ps
CPU time 75.14 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 01:55:22 PM PST 23
Peak memory 227024 kb
Host smart-81003e99-0730-4002-a637-3d95e4e3d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110521862849601499759762123224077799510167416076066063901284981019815815706157 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_entropy_refresh.110521862849601499759762123224077799510167416076066063901284981019815815706157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.40845344050105664381449940523978859223635347977755262359904017848687690753796
Short name T602
Test name
Test status
Simulation time 8615085608 ps
CPU time 133.89 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:56:27 PM PST 23
Peak memory 247828 kb
Host smart-4e618dea-1439-4b15-99cb-e1e76912c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40845344050105664381449940523978859223635347977755262359904017848687690753796 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.kmac_error.40845344050105664381449940523978859223635347977755262359904017848687690753796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.90967863985210085576221614830750246846825901005582232007013822928528096040911
Short name T610
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.21 seconds
Started Nov 22 01:53:37 PM PST 23
Finished Nov 22 01:53:43 PM PST 23
Peak memory 207516 kb
Host smart-92764fd4-7f74-45b1-bcd8-bf7a29c3100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90967863985210085576221614830750246846825901005582232007013822928528096040911 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.kmac_key_error.90967863985210085576221614830750246846825901005582232007013822928528096040911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.46453461782320198584800554617311328712666882614446727602822175205744635530045
Short name T700
Test name
Test status
Simulation time 58171921 ps
CPU time 1.25 seconds
Started Nov 22 01:53:25 PM PST 23
Finished Nov 22 01:53:27 PM PST 23
Peak memory 215692 kb
Host smart-4ed0ad97-0fba-4295-9b4a-b334acd491f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46453461782320198584800554617311328712666882614446727602822175205744635530045 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.kmac_lc_escalation.46453461782320198584800554617311328712666882614446727602822175205744635530045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.66970774884819450672851355623299275364611752566990141923066761183321558492236
Short name T609
Test name
Test status
Simulation time 45517522529 ps
CPU time 731.62 seconds
Started Nov 22 01:54:20 PM PST 23
Finished Nov 22 02:06:36 PM PST 23
Peak memory 288344 kb
Host smart-4146d48f-da66-47bf-a361-518b38ad6b62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66970774884819450672851355623299275364611752566990141923066761183321558492236 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.669707748848194506728513556232992753646117525669901419230667611833215
58492236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.69624649863845659922266556445908825807573000043377821177341122610204379581290
Short name T811
Test name
Test status
Simulation time 7733092664 ps
CPU time 109.41 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:56:16 PM PST 23
Peak memory 228048 kb
Host smart-dc65fd0f-580d-4035-ab7b-2b12d1c1119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69624649863845659922266556445908825807573000043377821177341122610204379581290 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.kmac_sideload.69624649863845659922266556445908825807573000043377821177341122610204379581290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.59964104236468901735543748364502159852642092715093712327015760482519868102702
Short name T999
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.97 seconds
Started Nov 22 01:54:23 PM PST 23
Finished Nov 22 01:54:46 PM PST 23
Peak memory 215612 kb
Host smart-c1e74ebe-779c-4242-9f00-00109fc85cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59964104236468901735543748364502159852642092715093712327015760482519868102702 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.kmac_smoke.59964104236468901735543748364502159852642092715093712327015760482519868102702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.86669924583033163561686080858192062323168857021200740940161018162489993105408
Short name T950
Test name
Test status
Simulation time 41434001626 ps
CPU time 616.69 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 02:03:58 PM PST 23
Peak memory 321752 kb
Host smart-f6793c6a-4dd2-4bd8-a7ea-128bdf202473
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=86669924583033163561686080858192062323168857021200740940161018162489993105408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_st
ress_all.86669924583033163561686080858192062323168857021200740940161018162489993105408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.63456635172128437918078260208007748180434126931789068469991114704695945792298
Short name T736
Test name
Test status
Simulation time 298812853 ps
CPU time 4.53 seconds
Started Nov 22 01:54:07 PM PST 23
Finished Nov 22 01:54:12 PM PST 23
Peak memory 215852 kb
Host smart-afd0f6a9-fd89-4ab3-be02-2f2db76ffab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63456635172128437918078260208007748180434126931789068
469991114704695945792298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac.63456635172128437918078260208007748180
434126931789068469991114704695945792298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.1916818660532921379215280023320364294869483943218170048583955664877442005010
Short name T66
Test name
Test status
Simulation time 289902210 ps
CPU time 4.13 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:54:13 PM PST 23
Peak memory 215832 kb
Host smart-828e6259-c876-4d61-9ec3-2b3ea34099d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19168186605329213792152800233203642948694839432181700
48583955664877442005010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.1916818660532921379215280023320
364294869483943218170048583955664877442005010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.29021523895066056116183105772976370497184865185587319425123083988287645756723
Short name T172
Test name
Test status
Simulation time 115269125226 ps
CPU time 1732.69 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 02:23:07 PM PST 23
Peak memory 390488 kb
Host smart-397cb550-83f9-4cc8-80b0-ff8988537cfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=29021523895066056116183105772976370497184865185587319425123083988287645756723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.kmac_test_vectors_sha3_224.29021523895066056116183105772976370497184865185587319425123083988287645756723 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.71130310032887303475986435008571639451601651741838652388897008144483051343024
Short name T985
Test name
Test status
Simulation time 107886220004 ps
CPU time 1583.12 seconds
Started Nov 22 01:54:18 PM PST 23
Finished Nov 22 02:20:43 PM PST 23
Peak memory 370052 kb
Host smart-3fe283fb-191d-463d-ac56-b16558d1a8e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=71130310032887303475986435008571639451601651741838652388897008144483051343024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.kmac_test_vectors_sha3_256.71130310032887303475986435008571639451601651741838652388897008144483051343024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.4137507141105073009555826836903017038925755903472535808389065255981573770684
Short name T727
Test name
Test status
Simulation time 83070954242 ps
CPU time 1204.6 seconds
Started Nov 22 01:54:18 PM PST 23
Finished Nov 22 02:14:25 PM PST 23
Peak memory 332904 kb
Host smart-cd4f0c69-72b9-4708-bd74-162a89809463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4137507141105073009555826836903017038925755903472535808389065255981573770684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
kmac_test_vectors_sha3_384.4137507141105073009555826836903017038925755903472535808389065255981573770684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.42434172825070322852464339898442318912698513794583142289130613015384303038672
Short name T389
Test name
Test status
Simulation time 58503507926 ps
CPU time 914.91 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 02:09:22 PM PST 23
Peak memory 295864 kb
Host smart-46c4c9b9-d473-4694-b60d-38fe0228d8b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=42434172825070322852464339898442318912698513794583142289130613015384303038672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.kmac_test_vectors_sha3_512.42434172825070322852464339898442318912698513794583142289130613015384303038672 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.82976725578942897253111023724066085834404226342344327682327888242518724022745
Short name T296
Test name
Test status
Simulation time 307766781661 ps
CPU time 4455.06 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 03:08:28 PM PST 23
Peak memory 653252 kb
Host smart-de44b154-6081-4296-81a3-b815a6700ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=82976725578942897253111023724066085834404226342344327682327888242518724022745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.kmac_test_vectors_shake_128.82976725578942897253111023724066085834404226342344327682327888242518724022745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.63606794228879392835186490997363440244497761764110319188717097469599927570300
Short name T402
Test name
Test status
Simulation time 258047411562 ps
CPU time 3585.64 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 02:53:57 PM PST 23
Peak memory 556336 kb
Host smart-accd9c31-6e64-4cf4-a0d3-987f58b4f0fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=63606794228879392835186490997363440244497761764110319188717097469599927570300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.kmac_test_vectors_shake_256.63606794228879392835186490997363440244497761764110319188717097469599927570300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.29878081236664285587307672285805408124457741326499927553818036827100754899037
Short name T795
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:52:48 PM PST 23
Peak memory 205188 kb
Host smart-b9a7bf97-1989-4c9a-b918-fe22e998553f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878081236664285587307672285805408124457741326499927553818036827100754899037 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.kmac_alert_test.29878081236664285587307672285805408124457741326499927553818036827100754899037 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.24244439176665388974556575058759559909027880474339587483781293011285883414646
Short name T515
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.77 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:54:04 PM PST 23
Peak memory 227380 kb
Host smart-088ff4ee-a01a-4411-b30a-b76d86af8d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24244439176665388974556575058759559909027880474339587483781293011285883414646 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.kmac_app.24244439176665388974556575058759559909027880474339587483781293011285883414646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.51361517621364555292065206188171402428614682371508319383317630749934123666341
Short name T375
Test name
Test status
Simulation time 7615861459 ps
CPU time 80.41 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 226020 kb
Host smart-10872d6d-d20e-4549-9ff8-cf4a2a3a2af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51361517621364555292065206188171402428614682371508319383317630749934123666341 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_app_with_partial_data.51361517621364555292065206188171402428614682371508319383317630749934123666341 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.75626365881124066917218978257431218899867733572973979858904677377489237878259
Short name T459
Test name
Test status
Simulation time 14812750312 ps
CPU time 249.56 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 01:56:45 PM PST 23
Peak memory 225472 kb
Host smart-7161e0cb-bfec-488b-9df6-ea7a8dffa5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75626365881124066917218978257431218899867733572973979858904677377489237878259 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.kmac_burst_write.75626365881124066917218978257431218899867733572973979858904677377489237878259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.105598976618662102002792724608948107802864784692375612613354685239362373217148
Short name T991
Test name
Test status
Simulation time 2342046507 ps
CPU time 35.49 seconds
Started Nov 22 01:52:37 PM PST 23
Finished Nov 22 01:53:20 PM PST 23
Peak memory 223764 kb
Host smart-f2846281-affd-419b-8d70-9ed9eed01bb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=105598976618662102002792724608948107802864784692375612613354685239362373217148 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.105598976618662102002792724608948107802864784692375612613354685239362373217148 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.90849853266549227772999310694682784950903569784119740950830372519016601138981
Short name T154
Test name
Test status
Simulation time 2211297553 ps
CPU time 29.46 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 01:53:03 PM PST 23
Peak memory 223864 kb
Host smart-4d36b684-47b7-4bc1-a598-233c9d294962
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90849853266549227772999310694682784950903569784119740950830372519016601138981 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.90849853266549227772999310694682784950903569784119740950830372519016601138981 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.13344699413923395752564257906906511277057909461757084928376252585412379273495
Short name T454
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.84 seconds
Started Nov 22 01:52:46 PM PST 23
Finished Nov 22 01:53:09 PM PST 23
Peak memory 216920 kb
Host smart-6ce1de23-8051-4d68-b286-31d8945a61f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13344699413923395752564257906906511277057909461757084928376252585412379273495 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.kmac_entropy_ready_error.13344699413923395752564257906906511277057909461757084928376252585412379273495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.86923249794589043818364459017801115179860217314193021749427832516516142933494
Short name T909
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.46 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:54:05 PM PST 23
Peak memory 226968 kb
Host smart-7f6d5038-811b-4e3a-b158-c67e25789b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86923249794589043818364459017801115179860217314193021749427832516516142933494 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.kmac_entropy_refresh.86923249794589043818364459017801115179860217314193021749427832516516142933494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.32118176605389368801067672179712913244814190733664646379892112305584028694922
Short name T498
Test name
Test status
Simulation time 8615085608 ps
CPU time 130.79 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 248568 kb
Host smart-3288c597-a7a2-4579-bfa3-abcb82c0c943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32118176605389368801067672179712913244814190733664646379892112305584028694922 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.kmac_error.32118176605389368801067672179712913244814190733664646379892112305584028694922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.54302721303641518300530220448041597030832986149608331208291487324593753862588
Short name T783
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.26 seconds
Started Nov 22 01:52:25 PM PST 23
Finished Nov 22 01:52:32 PM PST 23
Peak memory 207588 kb
Host smart-0aa4cc50-0481-42dd-b10c-a5fc84c672be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54302721303641518300530220448041597030832986149608331208291487324593753862588 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.kmac_key_error.54302721303641518300530220448041597030832986149608331208291487324593753862588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.40816410366503828005794478018952865665206570613396844282243156989324047621679
Short name T519
Test name
Test status
Simulation time 58171921 ps
CPU time 1.21 seconds
Started Nov 22 01:52:21 PM PST 23
Finished Nov 22 01:52:24 PM PST 23
Peak memory 215660 kb
Host smart-cea029b8-76b1-41d3-97a0-384dff6d1d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40816410366503828005794478018952865665206570613396844282243156989324047621679 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.kmac_lc_escalation.40816410366503828005794478018952865665206570613396844282243156989324047621679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.8408057010362629309802221481646860858435653286719368070853170705166284936176
Short name T476
Test name
Test status
Simulation time 45517522529 ps
CPU time 717.67 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 02:04:33 PM PST 23
Peak memory 288244 kb
Host smart-a88a9530-88eb-453c-b1ea-b6a341472880
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8408057010362629309802221481646860858435653286719368070853170705166284936176 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.84080570103626293098022214816468608584356532867193680708531707051662849
36176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.19366907302720484501636420658664057456704870521701158260730953038157916796087
Short name T353
Test name
Test status
Simulation time 5640716546 ps
CPU time 76.38 seconds
Started Nov 22 01:52:22 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 227736 kb
Host smart-ff13f40b-8e39-4eb8-a493-b1ac9d1cd9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19366907302720484501636420658664057456704870521701158260730953038157916796087 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.kmac_mubi.19366907302720484501636420658664057456704870521701158260730953038157916796087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sideload.33432341785710455409002598531747343251709273811594735241770406461390486182553
Short name T573
Test name
Test status
Simulation time 7733092664 ps
CPU time 112.76 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:54:41 PM PST 23
Peak memory 228120 kb
Host smart-ebee02ad-7570-4fa2-a292-1159e0ea9946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33432341785710455409002598531747343251709273811594735241770406461390486182553 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.kmac_sideload.33432341785710455409002598531747343251709273811594735241770406461390486182553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.13045717325613343575546623911280270832633929655561371857191218784883178120629
Short name T676
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.36 seconds
Started Nov 22 01:52:20 PM PST 23
Finished Nov 22 01:52:41 PM PST 23
Peak memory 215916 kb
Host smart-ab80b077-9b58-4345-b586-1a1f26cf53cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13045717325613343575546623911280270832633929655561371857191218784883178120629 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.kmac_smoke.13045717325613343575546623911280270832633929655561371857191218784883178120629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.46983282059466669141433580571146339297847200831176451538384173000482771114516
Short name T358
Test name
Test status
Simulation time 41434001626 ps
CPU time 626.11 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 02:03:08 PM PST 23
Peak memory 321680 kb
Host smart-a089c3e6-a713-431c-9c33-f264fe89a449
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=46983282059466669141433580571146339297847200831176451538384173000482771114516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_str
ess_all.46983282059466669141433580571146339297847200831176451538384173000482771114516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.16170270833590688430819226202374456072272279118966795712892178899031823687774
Short name T130
Test name
Test status
Simulation time 298812853 ps
CPU time 4.4 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:52:52 PM PST 23
Peak memory 215788 kb
Host smart-564e808a-5042-4357-852b-ef249103b479
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16170270833590688430819226202374456072272279118966795
712892178899031823687774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.161702708335906884308192262023744560722
72279118966795712892178899031823687774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.58984548088601351422421988507787015325486665785749444423168753215059431332540
Short name T772
Test name
Test status
Simulation time 289902210 ps
CPU time 4.25 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:52:43 PM PST 23
Peak memory 215844 kb
Host smart-97c98122-b2b9-43e1-a8e8-33bc95c2b5ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58984548088601351422421988507787015325486665785749444
423168753215059431332540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.5898454808860135142242198850778
7015325486665785749444423168753215059431332540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.42544248818011990262817559221775974693470831667898509686458205527214624184163
Short name T65
Test name
Test status
Simulation time 115269125226 ps
CPU time 1806.53 seconds
Started Nov 22 01:52:30 PM PST 23
Finished Nov 22 02:22:41 PM PST 23
Peak memory 390468 kb
Host smart-1b3019e2-204b-4aef-88d8-0aadf4d0e365
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=42544248818011990262817559221775974693470831667898509686458205527214624184163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
kmac_test_vectors_sha3_224.42544248818011990262817559221775974693470831667898509686458205527214624184163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.38068074464953720105612618386475209565383524028373965626114305181768896009507
Short name T1036
Test name
Test status
Simulation time 107886220004 ps
CPU time 1614.67 seconds
Started Nov 22 01:52:36 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 370180 kb
Host smart-3aa709e8-6496-462b-aaa9-a579893788d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38068074464953720105612618386475209565383524028373965626114305181768896009507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
kmac_test_vectors_sha3_256.38068074464953720105612618386475209565383524028373965626114305181768896009507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.108003330720634698917068251949541129772557946669987977976646528345666851252020
Short name T254
Test name
Test status
Simulation time 83070954242 ps
CPU time 1212.06 seconds
Started Nov 22 01:52:33 PM PST 23
Finished Nov 22 02:12:48 PM PST 23
Peak memory 332904 kb
Host smart-7120ae0a-f9d7-44e8-bad2-25d837fda6f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=108003330720634698917068251949541129772557946669987977976646528345666851252020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.kmac_test_vectors_sha3_384.108003330720634698917068251949541129772557946669987977976646528345666851252020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.6173888625611939368689932753693204035773291445864213268688576285513094099172
Short name T429
Test name
Test status
Simulation time 58503507926 ps
CPU time 898.83 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 02:07:32 PM PST 23
Peak memory 295808 kb
Host smart-4a4f497c-68fd-48cc-8070-5f17af37b114
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=6173888625611939368689932753693204035773291445864213268688576285513094099172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.k
mac_test_vectors_sha3_512.6173888625611939368689932753693204035773291445864213268688576285513094099172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.27591419274174016713150242908190553438402942098770813438931252223103244347944
Short name T960
Test name
Test status
Simulation time 307766781661 ps
CPU time 4573.53 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 03:09:00 PM PST 23
Peak memory 653188 kb
Host smart-e7c7ea64-39c2-4b9f-b96d-70960b4aa105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=27591419274174016713150242908190553438402942098770813438931252223103244347944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.kmac_test_vectors_shake_128.27591419274174016713150242908190553438402942098770813438931252223103244347944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.89875492438120775975675367926341301252897978543551237655392662649012109062019
Short name T447
Test name
Test status
Simulation time 258047411562 ps
CPU time 3691.7 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 02:54:20 PM PST 23
Peak memory 556316 kb
Host smart-a72171e7-6552-45f4-9310-0d2d23a55799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=89875492438120775975675367926341301252897978543551237655392662649012109062019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.kmac_test_vectors_shake_256.89875492438120775975675367926341301252897978543551237655392662649012109062019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.94655658336041846828737855110595061847826043964829118630096553389067611427378
Short name T185
Test name
Test status
Simulation time 21118646 ps
CPU time 0.76 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 204712 kb
Host smart-dd8fae2a-d424-415e-a010-bce51f9dc219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94655658336041846828737855110595061847826043964829118630096553389067611427378 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.kmac_alert_test.94655658336041846828737855110595061847826043964829118630096553389067611427378 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.45527887201217721222055343764460699997260342682263430180853758827160860234792
Short name T581
Test name
Test status
Simulation time 5659537824 ps
CPU time 75.44 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 01:55:22 PM PST 23
Peak memory 227380 kb
Host smart-76074ac8-01b4-42b5-9f97-8d3c54d28e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45527887201217721222055343764460699997260342682263430180853758827160860234792 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.kmac_app.45527887201217721222055343764460699997260342682263430180853758827160860234792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.69824031806809548486908200317021741174681152547765455738346891726324632734487
Short name T355
Test name
Test status
Simulation time 14812750312 ps
CPU time 246.39 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:58:19 PM PST 23
Peak memory 225580 kb
Host smart-da2b0a2c-ce48-438d-912b-166588f0af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69824031806809548486908200317021741174681152547765455738346891726324632734487 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.kmac_burst_write.69824031806809548486908200317021741174681152547765455738346891726324632734487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.5599061573044179767725993979357374069239944203042679244297457838121989294244
Short name T696
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.16 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 01:55:06 PM PST 23
Peak memory 227008 kb
Host smart-49e4992e-999e-490d-97de-69706fc59f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5599061573044179767725993979357374069239944203042679244297457838121989294244 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.kmac_entropy_refresh.5599061573044179767725993979357374069239944203042679244297457838121989294244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.35049773014353499644910676546377241024641530443407981608603535097127057263696
Short name T1003
Test name
Test status
Simulation time 8615085608 ps
CPU time 124.8 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 01:55:57 PM PST 23
Peak memory 248544 kb
Host smart-233b6d13-0a44-458e-82a8-4eb854486e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35049773014353499644910676546377241024641530443407981608603535097127057263696 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.kmac_error.35049773014353499644910676546377241024641530443407981608603535097127057263696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.29002470438816180374459953364702342806364173408419163476043139989227107747893
Short name T976
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.18 seconds
Started Nov 22 01:53:52 PM PST 23
Finished Nov 22 01:53:58 PM PST 23
Peak memory 207472 kb
Host smart-71a80f6b-db5a-4df9-8940-30e33f9ac2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29002470438816180374459953364702342806364173408419163476043139989227107747893 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.kmac_key_error.29002470438816180374459953364702342806364173408419163476043139989227107747893 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.77830218196688945076573652553871352576062332089367570963398773555161001303771
Short name T311
Test name
Test status
Simulation time 58171921 ps
CPU time 1.3 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:54:10 PM PST 23
Peak memory 215680 kb
Host smart-50bd3dbc-8ab1-4f8b-b9de-f601408863cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77830218196688945076573652553871352576062332089367570963398773555161001303771 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.kmac_lc_escalation.77830218196688945076573652553871352576062332089367570963398773555161001303771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.43950705923163562179816542429014282948980995539976241442599402773887850773196
Short name T593
Test name
Test status
Simulation time 45517522529 ps
CPU time 749.5 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 02:05:53 PM PST 23
Peak memory 288356 kb
Host smart-369d515b-14fb-4f01-a12f-bb93e1d960ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43950705923163562179816542429014282948980995539976241442599402773887850773196 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.439507059231635621798165424290142829489809955399762414425994027738878
50773196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.115271610474747644365017382498008258879915731622953680598043888759783179423927
Short name T845
Test name
Test status
Simulation time 7733092664 ps
CPU time 110.41 seconds
Started Nov 22 01:53:48 PM PST 23
Finished Nov 22 01:55:40 PM PST 23
Peak memory 228072 kb
Host smart-3f81339a-ae3e-4fa1-be2d-644c97ef5381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115271610474747644365017382498008258879915731622953680598043888759783179423927 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.kmac_sideload.115271610474747644365017382498008258879915731622953680598043888759783179423927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.92770392953482095587723967962100994636458673380016430083533174784351143533716
Short name T989
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.01 seconds
Started Nov 22 01:53:34 PM PST 23
Finished Nov 22 01:53:53 PM PST 23
Peak memory 215920 kb
Host smart-a7758a44-52b9-40fd-b476-89d3c3eab363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92770392953482095587723967962100994636458673380016430083533174784351143533716 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.kmac_smoke.92770392953482095587723967962100994636458673380016430083533174784351143533716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.8753066997127152931799938125947733440845423858056276881312769424261273811277
Short name T309
Test name
Test status
Simulation time 41434001626 ps
CPU time 616.53 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 02:04:30 PM PST 23
Peak memory 321684 kb
Host smart-0ff216c8-7e01-4498-a932-eae42b5edefe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=8753066997127152931799938125947733440845423858056276881312769424261273811277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_str
ess_all.8753066997127152931799938125947733440845423858056276881312769424261273811277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.27243759331622687603584682054764193787783452287855894456991349718155416915387
Short name T1052
Test name
Test status
Simulation time 298812853 ps
CPU time 4.24 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 215760 kb
Host smart-0be70ab0-e4ca-4381-9b27-4103132763be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243759331622687603584682054764193787783452287855894
456991349718155416915387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac.27243759331622687603584682054764193787
783452287855894456991349718155416915387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.75149866553776786969208427564632677487417505355346577444999565833728408805905
Short name T790
Test name
Test status
Simulation time 289902210 ps
CPU time 4.35 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 01:53:59 PM PST 23
Peak memory 215776 kb
Host smart-c7b297db-d88e-4f84-a597-5c854f03f490
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75149866553776786969208427564632677487417505355346577
444999565833728408805905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.751498665537767869692084275646
32677487417505355346577444999565833728408805905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.9439959716017477850833075482998499288868363283178816574540630824324001336809
Short name T531
Test name
Test status
Simulation time 115269125226 ps
CPU time 1730.85 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 390432 kb
Host smart-86efa203-1363-4373-b139-4d8757d45b6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=9439959716017477850833075482998499288868363283178816574540630824324001336809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
kmac_test_vectors_sha3_224.9439959716017477850833075482998499288868363283178816574540630824324001336809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.82323642320477002517101407484234870625547700992436272631576007561238767039908
Short name T690
Test name
Test status
Simulation time 107886220004 ps
CPU time 1561.35 seconds
Started Nov 22 01:53:48 PM PST 23
Finished Nov 22 02:19:52 PM PST 23
Peak memory 370100 kb
Host smart-b634e146-8a4d-4dac-9ebf-ac98607a3dfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=82323642320477002517101407484234870625547700992436272631576007561238767039908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.kmac_test_vectors_sha3_256.82323642320477002517101407484234870625547700992436272631576007561238767039908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.62374603269979922395340001505328835394515457410965345541642947535117110901510
Short name T449
Test name
Test status
Simulation time 83070954242 ps
CPU time 1239.42 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:14:27 PM PST 23
Peak memory 332952 kb
Host smart-abf3de65-1bba-41d3-9a31-22adba015d17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=62374603269979922395340001505328835394515457410965345541642947535117110901510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.kmac_test_vectors_sha3_384.62374603269979922395340001505328835394515457410965345541642947535117110901510 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.55185374110979066788318059259752466413084517818249769259677467502302352383431
Short name T587
Test name
Test status
Simulation time 58503507926 ps
CPU time 901.33 seconds
Started Nov 22 01:53:57 PM PST 23
Finished Nov 22 02:08:59 PM PST 23
Peak memory 295904 kb
Host smart-1a966acd-0f42-40a5-a5af-5437e4c92199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55185374110979066788318059259752466413084517818249769259677467502302352383431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.kmac_test_vectors_sha3_512.55185374110979066788318059259752466413084517818249769259677467502302352383431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.83078115396623592196213146954715759859233406992019814273856168884945473361575
Short name T226
Test name
Test status
Simulation time 307766781661 ps
CPU time 4509.67 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 03:08:57 PM PST 23
Peak memory 653220 kb
Host smart-309b9b18-beec-4566-bad5-fcd475d21402
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=83078115396623592196213146954715759859233406992019814273856168884945473361575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.kmac_test_vectors_shake_128.83078115396623592196213146954715759859233406992019814273856168884945473361575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.91221602089424825839219087832842607122809796278280985328530511266501727889550
Short name T826
Test name
Test status
Simulation time 258047411562 ps
CPU time 3682.42 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 02:55:28 PM PST 23
Peak memory 556260 kb
Host smart-333757ce-dc8b-4eaa-8e5c-ca938590a3fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=91221602089424825839219087832842607122809796278280985328530511266501727889550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.kmac_test_vectors_shake_256.91221602089424825839219087832842607122809796278280985328530511266501727889550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.17656800766889886934782720401945719592373693320892329004465066197291250487716
Short name T624
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 01:53:42 PM PST 23
Peak memory 205212 kb
Host smart-ea17e838-5b6a-44bc-9e6b-f4ca2338fa89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17656800766889886934782720401945719592373693320892329004465066197291250487716 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.kmac_alert_test.17656800766889886934782720401945719592373693320892329004465066197291250487716 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.98440818918631998053200444346773123236495617845594878080848517471725784284016
Short name T823
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.58 seconds
Started Nov 22 01:53:25 PM PST 23
Finished Nov 22 01:54:42 PM PST 23
Peak memory 227348 kb
Host smart-ce3fa4ff-65d9-405d-b7bc-5d8a1d58f77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98440818918631998053200444346773123236495617845594878080848517471725784284016 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.kmac_app.98440818918631998053200444346773123236495617845594878080848517471725784284016 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.103042130144365695873769859374167224984369558919544266225575689734019006715184
Short name T330
Test name
Test status
Simulation time 14812750312 ps
CPU time 239.4 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 01:58:11 PM PST 23
Peak memory 225576 kb
Host smart-b43ad4e0-38bc-4042-a436-f5ddc95290b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103042130144365695873769859374167224984369558919544266225575689734019006715184 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.kmac_burst_write.103042130144365695873769859374167224984369558919544266225575689734019006715184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.91053117789064977935499972945093845717188586290403664276497546406398283681541
Short name T733
Test name
Test status
Simulation time 6743332725 ps
CPU time 71.59 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 01:54:48 PM PST 23
Peak memory 227024 kb
Host smart-830a5561-a663-4b49-9b34-dfd64b4fdb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91053117789064977935499972945093845717188586290403664276497546406398283681541 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.kmac_entropy_refresh.91053117789064977935499972945093845717188586290403664276497546406398283681541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.8540103995905770937645093028439681497622590617621466719489974352567045711796
Short name T893
Test name
Test status
Simulation time 8615085608 ps
CPU time 120.07 seconds
Started Nov 22 01:53:22 PM PST 23
Finished Nov 22 01:55:25 PM PST 23
Peak memory 248524 kb
Host smart-0421b3ce-2a49-4e22-abac-2baa478d3e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8540103995905770937645093028439681497622590617621466719489974352567045711796 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.kmac_error.8540103995905770937645093028439681497622590617621466719489974352567045711796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.8465192852852775054370112236461447328572574007381237236507429706052280551652
Short name T657
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.28 seconds
Started Nov 22 01:53:37 PM PST 23
Finished Nov 22 01:53:43 PM PST 23
Peak memory 207600 kb
Host smart-7bc2d905-3bcd-49b7-b9f8-7e7921d92da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8465192852852775054370112236461447328572574007381237236507429706052280551652 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.kmac_key_error.8465192852852775054370112236461447328572574007381237236507429706052280551652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.57890577627274638514031494870454858506186022156697576411219085784882173650371
Short name T997
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:53:42 PM PST 23
Peak memory 215760 kb
Host smart-d53012f2-05a1-48e7-be4e-2318f36d2051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57890577627274638514031494870454858506186022156697576411219085784882173650371 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.kmac_lc_escalation.57890577627274638514031494870454858506186022156697576411219085784882173650371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.42220339002856984741823781315178076682871055165889061475191298102135958331423
Short name T414
Test name
Test status
Simulation time 45517522529 ps
CPU time 718.55 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 02:06:14 PM PST 23
Peak memory 288256 kb
Host smart-7f104a76-ce2d-4183-a273-8c0aede409db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42220339002856984741823781315178076682871055165889061475191298102135958331423 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.422203390028569847418237813151780766828710551658890614751912981021359
58331423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.51045384147198241157199601071984982068172823048828378211705734963048275358686
Short name T44
Test name
Test status
Simulation time 7733092664 ps
CPU time 109.77 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 01:56:06 PM PST 23
Peak memory 228068 kb
Host smart-c90276e9-a142-43fd-9cb1-cc3990df5e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51045384147198241157199601071984982068172823048828378211705734963048275358686 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.kmac_sideload.51045384147198241157199601071984982068172823048828378211705734963048275358686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.38147845631849085707765322380080373038372081026817944189046233633811105140165
Short name T291
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.95 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 01:54:33 PM PST 23
Peak memory 215864 kb
Host smart-8c93a2d2-7734-4691-9d68-1ae1eb712dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38147845631849085707765322380080373038372081026817944189046233633811105140165 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.kmac_smoke.38147845631849085707765322380080373038372081026817944189046233633811105140165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.107087156337643487601687431213460577925933359413809473261934274575620618403762
Short name T500
Test name
Test status
Simulation time 41434001626 ps
CPU time 621.82 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 02:04:04 PM PST 23
Peak memory 321684 kb
Host smart-949a24c6-b5f4-4f73-a6c3-00258de7a310
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=107087156337643487601687431213460577925933359413809473261934274575620618403762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_s
tress_all.107087156337643487601687431213460577925933359413809473261934274575620618403762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.85137054038225828333305329535559889474598606574272402218389871400655313685071
Short name T852
Test name
Test status
Simulation time 298812853 ps
CPU time 4.41 seconds
Started Nov 22 01:53:44 PM PST 23
Finished Nov 22 01:53:50 PM PST 23
Peak memory 215824 kb
Host smart-c4d1ca29-2673-4536-a880-7f17f054ad77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85137054038225828333305329535559889474598606574272402
218389871400655313685071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac.85137054038225828333305329535559889474
598606574272402218389871400655313685071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.72067303744975872381034797063518836151602125735862956483976632833054900643553
Short name T567
Test name
Test status
Simulation time 289902210 ps
CPU time 4.14 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:53:44 PM PST 23
Peak memory 215804 kb
Host smart-de2e22ad-0576-4f27-b6a9-96297d3feb49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72067303744975872381034797063518836151602125735862956
483976632833054900643553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac_xof.720673037449758723810347970635
18836151602125735862956483976632833054900643553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.58139170728144951863865972557547549735955423911760452512180439620615928459804
Short name T457
Test name
Test status
Simulation time 115269125226 ps
CPU time 1734.17 seconds
Started Nov 22 01:54:23 PM PST 23
Finished Nov 22 02:23:21 PM PST 23
Peak memory 390384 kb
Host smart-e5cbfb1e-3ad7-4476-ae6b-cb86bf4fd49d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=58139170728144951863865972557547549735955423911760452512180439620615928459804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_224.58139170728144951863865972557547549735955423911760452512180439620615928459804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.34410150923592616143916365675570721074195273337388224706781096889187575163745
Short name T327
Test name
Test status
Simulation time 107886220004 ps
CPU time 1616.48 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:20:44 PM PST 23
Peak memory 370116 kb
Host smart-fd560198-3f03-44b4-8fdd-f51ed381bc31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=34410150923592616143916365675570721074195273337388224706781096889187575163745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_256.34410150923592616143916365675570721074195273337388224706781096889187575163745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.42053921830573241329961359293407589977805539678732570078284998095250103430708
Short name T547
Test name
Test status
Simulation time 83070954242 ps
CPU time 1243.47 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 02:14:55 PM PST 23
Peak memory 332804 kb
Host smart-b5541c52-6cdf-4f54-8137-0d2eb57e8c16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=42053921830573241329961359293407589977805539678732570078284998095250103430708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_384.42053921830573241329961359293407589977805539678732570078284998095250103430708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.18971745812811412487505781756212946064024190820231726180864307875910638644153
Short name T467
Test name
Test status
Simulation time 58503507926 ps
CPU time 864.85 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 02:08:30 PM PST 23
Peak memory 295900 kb
Host smart-37fec14f-ed53-4f51-ae11-fbd8db51af77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=18971745812811412487505781756212946064024190820231726180864307875910638644153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.kmac_test_vectors_sha3_512.18971745812811412487505781756212946064024190820231726180864307875910638644153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.14848691851838843623421216140828806853269648258600800042529944501275955920295
Short name T667
Test name
Test status
Simulation time 307766781661 ps
CPU time 4465.23 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 03:08:27 PM PST 23
Peak memory 653212 kb
Host smart-ce378c30-e1a1-447a-9ac0-530042fc5259
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=14848691851838843623421216140828806853269648258600800042529944501275955920295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.kmac_test_vectors_shake_128.14848691851838843623421216140828806853269648258600800042529944501275955920295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.32602232762357705352486890469453737963828618535529902500402920194331067675292
Short name T632
Test name
Test status
Simulation time 258047411562 ps
CPU time 3620.97 seconds
Started Nov 22 01:53:26 PM PST 23
Finished Nov 22 02:53:48 PM PST 23
Peak memory 556264 kb
Host smart-5d251e98-c4c9-4043-8d16-c3a15ce905e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=32602232762357705352486890469453737963828618535529902500402920194331067675292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.kmac_test_vectors_shake_256.32602232762357705352486890469453737963828618535529902500402920194331067675292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.46624758280809561488955559189190045068913718971212199757790075690458354363970
Short name T150
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 205236 kb
Host smart-3b946947-57d7-40ef-a465-5d0b7f5b126c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46624758280809561488955559189190045068913718971212199757790075690458354363970 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.kmac_alert_test.46624758280809561488955559189190045068913718971212199757790075690458354363970 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.99343366321119541252350332769523866670654303710508329951168613747467418214277
Short name T1063
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.39 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 01:54:56 PM PST 23
Peak memory 227308 kb
Host smart-328e8246-e6fa-4f73-9a82-f8e8c8fd9656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99343366321119541252350332769523866670654303710508329951168613747467418214277 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.kmac_app.99343366321119541252350332769523866670654303710508329951168613747467418214277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.112377214926778515262667030335105234826946145352199699399008565184283784879278
Short name T1072
Test name
Test status
Simulation time 14812750312 ps
CPU time 242.95 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 01:57:45 PM PST 23
Peak memory 225572 kb
Host smart-95412289-115b-486e-8f05-dbab7da3933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112377214926778515262667030335105234826946145352199699399008565184283784879278 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.kmac_burst_write.112377214926778515262667030335105234826946145352199699399008565184283784879278 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.66866787697288764312126572833587311975857232137272264192802224040625570962224
Short name T723
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.17 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 227040 kb
Host smart-6cd2534b-7c2f-4423-9b89-dd322daffbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66866787697288764312126572833587311975857232137272264192802224040625570962224 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.kmac_entropy_refresh.66866787697288764312126572833587311975857232137272264192802224040625570962224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.20126964251484057562302621815763997423925763440789839730008060166810494978629
Short name T206
Test name
Test status
Simulation time 8615085608 ps
CPU time 134.04 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:55:59 PM PST 23
Peak memory 248656 kb
Host smart-f3ce3f15-51f3-48a7-a8d3-c1b8c1551be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20126964251484057562302621815763997423925763440789839730008060166810494978629 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.kmac_error.20126964251484057562302621815763997423925763440789839730008060166810494978629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.77001649007650348155800182478395800561659023528783796305520189193000548246761
Short name T666
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.35 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:53:54 PM PST 23
Peak memory 207520 kb
Host smart-987f2d71-9630-4a36-8909-18b4bbfddc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77001649007650348155800182478395800561659023528783796305520189193000548246761 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.kmac_key_error.77001649007650348155800182478395800561659023528783796305520189193000548246761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.97347417587629157586327054608846603016625935442214692955025816450879039008162
Short name T911
Test name
Test status
Simulation time 58171921 ps
CPU time 1.22 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 01:53:52 PM PST 23
Peak memory 215700 kb
Host smart-5f7f1b13-4b81-4ff8-9b75-37c3a76fdbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97347417587629157586327054608846603016625935442214692955025816450879039008162 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.kmac_lc_escalation.97347417587629157586327054608846603016625935442214692955025816450879039008162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.13631875921621901415418497695981657234342582772044790174485285387756776068728
Short name T435
Test name
Test status
Simulation time 45517522529 ps
CPU time 704.13 seconds
Started Nov 22 01:53:22 PM PST 23
Finished Nov 22 02:05:08 PM PST 23
Peak memory 288244 kb
Host smart-986e441a-d239-4aa9-aea6-188889beec8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13631875921621901415418497695981657234342582772044790174485285387756776068728 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.136318759216219014154184976959816572343425827720447901744852853877567
76068728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.57420483410222338189081000512628598571864213685032382004475938742710112479218
Short name T884
Test name
Test status
Simulation time 7733092664 ps
CPU time 106.19 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 01:55:25 PM PST 23
Peak memory 228164 kb
Host smart-1b507e49-f34e-40d3-84cf-a3fc40c3093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57420483410222338189081000512628598571864213685032382004475938742710112479218 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.kmac_sideload.57420483410222338189081000512628598571864213685032382004475938742710112479218 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.78738145367272665189190009075684658288536417957812846212381404711690440609561
Short name T522
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.35 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 215984 kb
Host smart-8ca8685d-53eb-4bff-8633-f0ceddbdba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78738145367272665189190009075684658288536417957812846212381404711690440609561 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.kmac_smoke.78738145367272665189190009075684658288536417957812846212381404711690440609561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.112373874316974983363191629725047136388610560279836080528893091118897303723732
Short name T604
Test name
Test status
Simulation time 41434001626 ps
CPU time 602.69 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:03:50 PM PST 23
Peak memory 321716 kb
Host smart-46617079-444a-4284-ab60-a6490c99fd16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=112373874316974983363191629725047136388610560279836080528893091118897303723732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_s
tress_all.112373874316974983363191629725047136388610560279836080528893091118897303723732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.59150143444792553780012833166198288316712216421505810708825206901044647950815
Short name T981
Test name
Test status
Simulation time 298812853 ps
CPU time 4.35 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 01:53:46 PM PST 23
Peak memory 215788 kb
Host smart-7b01f003-69eb-41b1-8921-078b5a6d4c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59150143444792553780012833166198288316712216421505810
708825206901044647950815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac.59150143444792553780012833166198288316
712216421505810708825206901044647950815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.89957360387444033395400094745230544084174340661826786821222450092536427311673
Short name T1000
Test name
Test status
Simulation time 289902210 ps
CPU time 4.09 seconds
Started Nov 22 01:53:57 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 215752 kb
Host smart-d5c190b3-2da1-4347-a455-da54ebc49f84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89957360387444033395400094745230544084174340661826786
821222450092536427311673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac_xof.899573603874440333954000947452
30544084174340661826786821222450092536427311673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.24895427346473877833460121723310564084527526770111071413935842334088644424387
Short name T120
Test name
Test status
Simulation time 115269125226 ps
CPU time 1734.15 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 390476 kb
Host smart-64797db1-662c-46a5-b3a6-415885ffbdc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=24895427346473877833460121723310564084527526770111071413935842334088644424387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.kmac_test_vectors_sha3_224.24895427346473877833460121723310564084527526770111071413935842334088644424387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.112905619637266475344139003604421578241979875274443523068950236728657287850542
Short name T555
Test name
Test status
Simulation time 107886220004 ps
CPU time 1604.34 seconds
Started Nov 22 01:53:37 PM PST 23
Finished Nov 22 02:20:23 PM PST 23
Peak memory 370204 kb
Host smart-6f6b91b9-20fd-4a53-aa7d-9bb514552d81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=112905619637266475344139003604421578241979875274443523068950236728657287850542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.kmac_test_vectors_sha3_256.112905619637266475344139003604421578241979875274443523068950236728657287850542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.99795417333934523819871717139295586716094034430693819812624189671302734531917
Short name T1037
Test name
Test status
Simulation time 83070954242 ps
CPU time 1221.12 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 02:13:57 PM PST 23
Peak memory 332908 kb
Host smart-1411ec45-21dc-4c67-b01b-53a0914b4a72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=99795417333934523819871717139295586716094034430693819812624189671302734531917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.kmac_test_vectors_sha3_384.99795417333934523819871717139295586716094034430693819812624189671302734531917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.5812383204676928385539027780433381524952577593365234924578236417504380713602
Short name T141
Test name
Test status
Simulation time 58503507926 ps
CPU time 898.62 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 02:08:43 PM PST 23
Peak memory 295808 kb
Host smart-5f2a62a5-8150-494d-b997-1b3b2c7bdbd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=5812383204676928385539027780433381524952577593365234924578236417504380713602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
kmac_test_vectors_sha3_512.5812383204676928385539027780433381524952577593365234924578236417504380713602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.86661388739294311060831849270015763711497310267443182411385816972540407260292
Short name T1068
Test name
Test status
Simulation time 307766781661 ps
CPU time 4426.29 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 03:07:38 PM PST 23
Peak memory 653124 kb
Host smart-4424de6f-ed45-4101-ac5d-180708109da4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=86661388739294311060831849270015763711497310267443182411385816972540407260292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.kmac_test_vectors_shake_128.86661388739294311060831849270015763711497310267443182411385816972540407260292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.27803112124587462734339786039743059027249195135032220849987295970588568572762
Short name T618
Test name
Test status
Simulation time 258047411562 ps
CPU time 3625.21 seconds
Started Nov 22 01:53:35 PM PST 23
Finished Nov 22 02:54:02 PM PST 23
Peak memory 556328 kb
Host smart-cf30d53a-a4ff-45f1-9133-dc45bf8ef2e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=27803112124587462734339786039743059027249195135032220849987295970588568572762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.kmac_test_vectors_shake_256.27803112124587462734339786039743059027249195135032220849987295970588568572762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.93498072164773359783346584043368325862928166545232118868672305529612779939849
Short name T803
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:54:10 PM PST 23
Peak memory 205228 kb
Host smart-789b1c44-f9b0-4dc9-acb9-d79da9f768de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93498072164773359783346584043368325862928166545232118868672305529612779939849 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.kmac_alert_test.93498072164773359783346584043368325862928166545232118868672305529612779939849 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.57473957190381232645671865087204099295528952533586701007702379623952352321791
Short name T47
Test name
Test status
Simulation time 5659537824 ps
CPU time 78.69 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 227340 kb
Host smart-e0924330-39e6-4852-80c9-047bf8bdbf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57473957190381232645671865087204099295528952533586701007702379623952352321791 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.kmac_app.57473957190381232645671865087204099295528952533586701007702379623952352321791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.88672064312670973419151869896877462334617311072941818589766108626051678970656
Short name T543
Test name
Test status
Simulation time 14812750312 ps
CPU time 240.17 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 01:58:06 PM PST 23
Peak memory 225592 kb
Host smart-c4a11603-96c9-4a72-95b9-c40b5aac4884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88672064312670973419151869896877462334617311072941818589766108626051678970656 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.kmac_burst_write.88672064312670973419151869896877462334617311072941818589766108626051678970656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.46109013674591693733209702711497086847857418614470909102369916131779620639675
Short name T151
Test name
Test status
Simulation time 6743332725 ps
CPU time 78.53 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:55:31 PM PST 23
Peak memory 226992 kb
Host smart-477749cb-f2e5-411c-9d19-c0e8c250dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46109013674591693733209702711497086847857418614470909102369916131779620639675 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.kmac_entropy_refresh.46109013674591693733209702711497086847857418614470909102369916131779620639675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.82801212627467726604256796015123538517134340902627629048914128781094854191332
Short name T594
Test name
Test status
Simulation time 8615085608 ps
CPU time 136.17 seconds
Started Nov 22 01:54:23 PM PST 23
Finished Nov 22 01:56:43 PM PST 23
Peak memory 248588 kb
Host smart-1acd94c3-8c8d-45a2-a954-645e710f6fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82801212627467726604256796015123538517134340902627629048914128781094854191332 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.kmac_error.82801212627467726604256796015123538517134340902627629048914128781094854191332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.65381717871688816099574464970315517645906783443398570581201643105029106620940
Short name T658
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.25 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:54:18 PM PST 23
Peak memory 207532 kb
Host smart-99908c92-2126-44ea-9795-75469a9bfaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65381717871688816099574464970315517645906783443398570581201643105029106620940 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.kmac_key_error.65381717871688816099574464970315517645906783443398570581201643105029106620940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3272734764483747211413318783897712456558938068380606178673028762986390309463
Short name T418
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:54:24 PM PST 23
Finished Nov 22 01:54:28 PM PST 23
Peak memory 215684 kb
Host smart-21ca506d-a938-4b66-9a83-08f5416e4ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272734764483747211413318783897712456558938068380606178673028762986390309463 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.kmac_lc_escalation.3272734764483747211413318783897712456558938068380606178673028762986390309463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.30767784198858881393365594913528473592839196090216166917194954835834417968801
Short name T242
Test name
Test status
Simulation time 45517522529 ps
CPU time 669.22 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 02:04:51 PM PST 23
Peak memory 288300 kb
Host smart-ded7497e-b95b-4322-9211-c44e153d8c7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767784198858881393365594913528473592839196090216166917194954835834417968801 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.307677841988588813933655949135284735928391960902161669171949548358344
17968801 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.33966180083729685965767773287659986103799758677691083790322703822477090588816
Short name T869
Test name
Test status
Simulation time 7733092664 ps
CPU time 110.44 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 01:55:41 PM PST 23
Peak memory 228096 kb
Host smart-1dd05a1f-8039-4827-8fb2-93022387dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33966180083729685965767773287659986103799758677691083790322703822477090588816 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.kmac_sideload.33966180083729685965767773287659986103799758677691083790322703822477090588816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.24932731559705522814038722145460877003790149621346816684514575070115101273240
Short name T671
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.63 seconds
Started Nov 22 01:53:44 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 215824 kb
Host smart-12f63cc3-01fa-4e74-bf08-b6bcbe283359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24932731559705522814038722145460877003790149621346816684514575070115101273240 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.kmac_smoke.24932731559705522814038722145460877003790149621346816684514575070115101273240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.94626934332084242749207344677874168684865190469673284753784091940681411379913
Short name T713
Test name
Test status
Simulation time 41434001626 ps
CPU time 614.13 seconds
Started Nov 22 01:54:23 PM PST 23
Finished Nov 22 02:04:41 PM PST 23
Peak memory 321332 kb
Host smart-85d866d8-bd97-4174-a07c-bec9caaa67e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=94626934332084242749207344677874168684865190469673284753784091940681411379913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_st
ress_all.94626934332084242749207344677874168684865190469673284753784091940681411379913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.51605701733017724603379303962603602787902048139674173958857894910270392030755
Short name T1069
Test name
Test status
Simulation time 298812853 ps
CPU time 4.29 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 01:54:05 PM PST 23
Peak memory 215800 kb
Host smart-f6a9805e-ae85-47dd-9ba4-f10ad59eb22a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51605701733017724603379303962603602787902048139674173
958857894910270392030755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac.51605701733017724603379303962603602787
902048139674173958857894910270392030755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.25362828719437227073170211663763492220515048211547449783644319922802759327598
Short name T748
Test name
Test status
Simulation time 289902210 ps
CPU time 4.26 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:54:12 PM PST 23
Peak memory 215784 kb
Host smart-cd891515-8e76-42a3-adc2-be8fdc66985e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25362828719437227073170211663763492220515048211547449
783644319922802759327598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.253628287194372270731702116637
63492220515048211547449783644319922802759327598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.2027421189699227309315575579802504903209417637473674329205494350323302873919
Short name T734
Test name
Test status
Simulation time 115269125226 ps
CPU time 1742.72 seconds
Started Nov 22 01:54:06 PM PST 23
Finished Nov 22 02:23:10 PM PST 23
Peak memory 390404 kb
Host smart-984d0c94-c3ca-4437-8bfd-720558c99a87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2027421189699227309315575579802504903209417637473674329205494350323302873919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
kmac_test_vectors_sha3_224.2027421189699227309315575579802504903209417637473674329205494350323302873919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.52332136167206994205356152798884153861772258533978488755944709442332487637788
Short name T886
Test name
Test status
Simulation time 107886220004 ps
CPU time 1593.85 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 02:20:40 PM PST 23
Peak memory 369732 kb
Host smart-e16ea872-3c6f-4b4c-93c2-5e59fd07d60c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=52332136167206994205356152798884153861772258533978488755944709442332487637788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.kmac_test_vectors_sha3_256.52332136167206994205356152798884153861772258533978488755944709442332487637788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.57575620011739322569938689538061267590875694797187740458883892292340390168311
Short name T231
Test name
Test status
Simulation time 83070954242 ps
CPU time 1253.69 seconds
Started Nov 22 01:54:14 PM PST 23
Finished Nov 22 02:15:08 PM PST 23
Peak memory 332908 kb
Host smart-944c140a-9089-434e-aeaf-56dcb1e72d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57575620011739322569938689538061267590875694797187740458883892292340390168311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.kmac_test_vectors_sha3_384.57575620011739322569938689538061267590875694797187740458883892292340390168311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.61010517258658521939153278639202627481273699152933807230625030021363040297843
Short name T720
Test name
Test status
Simulation time 58503507926 ps
CPU time 864.08 seconds
Started Nov 22 01:53:59 PM PST 23
Finished Nov 22 02:08:24 PM PST 23
Peak memory 295832 kb
Host smart-f8fc111c-1992-44b2-a2e2-cb3eadf65ed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61010517258658521939153278639202627481273699152933807230625030021363040297843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.kmac_test_vectors_sha3_512.61010517258658521939153278639202627481273699152933807230625030021363040297843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.59416655458122361202184927632722362000026942146731331652974850059012911336663
Short name T831
Test name
Test status
Simulation time 307766781661 ps
CPU time 4544.54 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 03:10:02 PM PST 23
Peak memory 653192 kb
Host smart-2c94568c-607c-4774-9447-94dba0387fa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=59416655458122361202184927632722362000026942146731331652974850059012911336663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.kmac_test_vectors_shake_128.59416655458122361202184927632722362000026942146731331652974850059012911336663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.37188070199156421581791214471750369420151332590568432735701837033931147740136
Short name T746
Test name
Test status
Simulation time 258047411562 ps
CPU time 3666.46 seconds
Started Nov 22 01:54:16 PM PST 23
Finished Nov 22 02:55:23 PM PST 23
Peak memory 556300 kb
Host smart-1eb4f11d-ce11-432d-a03d-ba37f5b983ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=37188070199156421581791214471750369420151332590568432735701837033931147740136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.kmac_test_vectors_shake_256.37188070199156421581791214471750369420151332590568432735701837033931147740136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.78863750505355017035466863053307025713581631038502078106786435993640019445207
Short name T473
Test name
Test status
Simulation time 21118646 ps
CPU time 0.71 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 205128 kb
Host smart-1cc21e50-1b71-429e-a9d1-aa89b4b03799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78863750505355017035466863053307025713581631038502078106786435993640019445207 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.kmac_alert_test.78863750505355017035466863053307025713581631038502078106786435993640019445207 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.55396884468870366920273433033175982119479512868786402967664899490085241649942
Short name T441
Test name
Test status
Simulation time 5659537824 ps
CPU time 75.63 seconds
Started Nov 22 01:54:01 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 227320 kb
Host smart-c09c1fd5-ca17-4e42-9f86-79873f06f03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55396884468870366920273433033175982119479512868786402967664899490085241649942 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.kmac_app.55396884468870366920273433033175982119479512868786402967664899490085241649942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.107195030066964917293419132978850306292352576026679557971639348502402182904491
Short name T1064
Test name
Test status
Simulation time 14812750312 ps
CPU time 240.63 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 01:58:15 PM PST 23
Peak memory 225464 kb
Host smart-56195188-8662-44ae-bfea-6cec38cc1a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107195030066964917293419132978850306292352576026679557971639348502402182904491 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.kmac_burst_write.107195030066964917293419132978850306292352576026679557971639348502402182904491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.29666044670991492142827466631707061357337131217765073570999299794517535159235
Short name T784
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.33 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 01:54:47 PM PST 23
Peak memory 227120 kb
Host smart-223d3f90-6eee-4dc3-8de1-66c35a419a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29666044670991492142827466631707061357337131217765073570999299794517535159235 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.kmac_entropy_refresh.29666044670991492142827466631707061357337131217765073570999299794517535159235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.1841563263169814160067819417531939580885087172980928301891930326358667075438
Short name T612
Test name
Test status
Simulation time 8615085608 ps
CPU time 127.18 seconds
Started Nov 22 01:54:07 PM PST 23
Finished Nov 22 01:56:15 PM PST 23
Peak memory 248564 kb
Host smart-36bd6c99-e4d7-4de2-a5d5-5d1388ffb0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841563263169814160067819417531939580885087172980928301891930326358667075438 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.kmac_error.1841563263169814160067819417531939580885087172980928301891930326358667075438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.48837377757367092340084817801156059982725178786916468447943392724571317469565
Short name T484
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.19 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:53:50 PM PST 23
Peak memory 207560 kb
Host smart-ace39860-a7f4-4c97-852c-88d98b13ef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48837377757367092340084817801156059982725178786916468447943392724571317469565 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.kmac_key_error.48837377757367092340084817801156059982725178786916468447943392724571317469565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.90674243686499642104376463991114753539167207412441934095424002716028107642271
Short name T517
Test name
Test status
Simulation time 58171921 ps
CPU time 1.23 seconds
Started Nov 22 01:53:27 PM PST 23
Finished Nov 22 01:53:29 PM PST 23
Peak memory 215840 kb
Host smart-9675cc3c-cb95-40ec-bb31-1de64b586d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90674243686499642104376463991114753539167207412441934095424002716028107642271 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.kmac_lc_escalation.90674243686499642104376463991114753539167207412441934095424002716028107642271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.80687512949579655441130682511663157056591662708008052335439195599468093449057
Short name T571
Test name
Test status
Simulation time 45517522529 ps
CPU time 717.75 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 02:06:01 PM PST 23
Peak memory 288324 kb
Host smart-ff242f1d-1360-479f-b994-e7e8d66a3e47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80687512949579655441130682511663157056591662708008052335439195599468093449057 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.806875129495796554411306825116631570565916627080080523354391955994680
93449057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.42025905592476937640651634698654453487157284364490333458044954828809637395975
Short name T134
Test name
Test status
Simulation time 7733092664 ps
CPU time 112.38 seconds
Started Nov 22 01:54:18 PM PST 23
Finished Nov 22 01:56:12 PM PST 23
Peak memory 228048 kb
Host smart-dfb860b0-ff94-4431-87aa-7442af8bbd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42025905592476937640651634698654453487157284364490333458044954828809637395975 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.kmac_sideload.42025905592476937640651634698654453487157284364490333458044954828809637395975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.101757880021388962830244718098278976158320510207923259722007756106635802302929
Short name T188
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.24 seconds
Started Nov 22 01:54:09 PM PST 23
Finished Nov 22 01:54:28 PM PST 23
Peak memory 215876 kb
Host smart-807feebc-8835-46e7-9622-706db4a6dfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101757880021388962830244718098278976158320510207923259722007756106635802302929 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.kmac_smoke.101757880021388962830244718098278976158320510207923259722007756106635802302929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.79028123134748516522999735228324896888371378084064441231231572852110758121043
Short name T77
Test name
Test status
Simulation time 41434001626 ps
CPU time 596.73 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 02:03:39 PM PST 23
Peak memory 321636 kb
Host smart-34b44f08-1f5a-406c-9ad3-c144a7841e8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=79028123134748516522999735228324896888371378084064441231231572852110758121043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_st
ress_all.79028123134748516522999735228324896888371378084064441231231572852110758121043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.24558034742281997146825277235014251349283883661564980354678298410047563564846
Short name T916
Test name
Test status
Simulation time 298812853 ps
CPU time 4.55 seconds
Started Nov 22 01:54:27 PM PST 23
Finished Nov 22 01:54:35 PM PST 23
Peak memory 215804 kb
Host smart-b44c50e4-b8d2-4772-8d2a-f6c5fa0bf057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24558034742281997146825277235014251349283883661564980
354678298410047563564846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac.24558034742281997146825277235014251349
283883661564980354678298410047563564846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.32597660016625900347627301459079513187227606769399725427852823974197237778998
Short name T362
Test name
Test status
Simulation time 289902210 ps
CPU time 4.02 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 01:54:11 PM PST 23
Peak memory 215796 kb
Host smart-728b63e8-3e11-4198-a405-3ca5d55c4682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597660016625900347627301459079513187227606769399725
427852823974197237778998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.325976600166259003476273014590
79513187227606769399725427852823974197237778998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.93959830290787439107036621180408374560182281287816057065021242793111605213445
Short name T323
Test name
Test status
Simulation time 115269125226 ps
CPU time 1702.7 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 390488 kb
Host smart-25fb929d-8545-43a6-aae5-b1c888b48531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=93959830290787439107036621180408374560182281287816057065021242793111605213445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.kmac_test_vectors_sha3_224.93959830290787439107036621180408374560182281287816057065021242793111605213445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.36818445721165259425756380346031879282288783603974792178934172861970317959069
Short name T945
Test name
Test status
Simulation time 107886220004 ps
CPU time 1621.18 seconds
Started Nov 22 01:54:18 PM PST 23
Finished Nov 22 02:21:21 PM PST 23
Peak memory 370052 kb
Host smart-f8872731-896d-431b-8c1a-c3b8c5d1cad2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=36818445721165259425756380346031879282288783603974792178934172861970317959069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.kmac_test_vectors_sha3_256.36818445721165259425756380346031879282288783603974792178934172861970317959069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.600237186556262463578069981339931142777192729148377783253522626599256148652
Short name T739
Test name
Test status
Simulation time 83070954242 ps
CPU time 1235.4 seconds
Started Nov 22 01:54:25 PM PST 23
Finished Nov 22 02:15:04 PM PST 23
Peak memory 332904 kb
Host smart-0461b46a-63b8-419d-ae3e-f6fb14f7efb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=600237186556262463578069981339931142777192729148377783253522626599256148652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.k
mac_test_vectors_sha3_384.600237186556262463578069981339931142777192729148377783253522626599256148652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.26898296578731012656523930058009518002144504029016426934543152599552516306994
Short name T463
Test name
Test status
Simulation time 58503507926 ps
CPU time 856.45 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 02:08:30 PM PST 23
Peak memory 295956 kb
Host smart-31328141-33a7-436c-9e74-d17cc2bbf211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=26898296578731012656523930058009518002144504029016426934543152599552516306994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.kmac_test_vectors_sha3_512.26898296578731012656523930058009518002144504029016426934543152599552516306994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.105831117668456482528821238728847930564150786209679101276020149288679916710754
Short name T773
Test name
Test status
Simulation time 307766781661 ps
CPU time 4438.24 seconds
Started Nov 22 01:54:26 PM PST 23
Finished Nov 22 03:08:29 PM PST 23
Peak memory 653288 kb
Host smart-36d9718e-e0be-4ac0-b512-30448c1e6a93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=105831117668456482528821238728847930564150786209679101276020149288679916710754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.kmac_test_vectors_shake_128.105831117668456482528821238728847930564150786209679101276020149288679916710754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.111415708994798200070383076084039532846595091908721781624117359038897376117458
Short name T270
Test name
Test status
Simulation time 258047411562 ps
CPU time 3768.87 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 02:56:45 PM PST 23
Peak memory 556300 kb
Host smart-f21c1c88-b981-4ad3-88b0-28019982b4ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=111415708994798200070383076084039532846595091908721781624117359038897376117458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.kmac_test_vectors_shake_256.111415708994798200070383076084039532846595091908721781624117359038897376117458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.10064041701699700552292086536285875456484613084765638685439154316688684237266
Short name T299
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:53:57 PM PST 23
Peak memory 205188 kb
Host smart-e0a249b2-3012-4b4e-b21d-dfb234e8c784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10064041701699700552292086536285875456484613084765638685439154316688684237266 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.kmac_alert_test.10064041701699700552292086536285875456484613084765638685439154316688684237266 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.67731075770605119997902129600232078804295838062066253322640608718279262102850
Short name T347
Test name
Test status
Simulation time 5659537824 ps
CPU time 73.19 seconds
Started Nov 22 01:53:26 PM PST 23
Finished Nov 22 01:54:40 PM PST 23
Peak memory 227352 kb
Host smart-8dce6ff4-d6b7-4c4f-87a3-32e462a29e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67731075770605119997902129600232078804295838062066253322640608718279262102850 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.kmac_app.67731075770605119997902129600232078804295838062066253322640608718279262102850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.45125319305549639402269323823623884064033045695880093354969158405067948758761
Short name T35
Test name
Test status
Simulation time 14812750312 ps
CPU time 243.8 seconds
Started Nov 22 01:53:32 PM PST 23
Finished Nov 22 01:57:37 PM PST 23
Peak memory 225444 kb
Host smart-2d9e8790-0a7c-47e9-9737-77cd14f4e90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45125319305549639402269323823623884064033045695880093354969158405067948758761 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.kmac_burst_write.45125319305549639402269323823623884064033045695880093354969158405067948758761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.95927846035288403048639319469487023596325470500972324263236049326453645630106
Short name T675
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.84 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 226992 kb
Host smart-59c19ab9-7386-4878-a71f-bfada8c4439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95927846035288403048639319469487023596325470500972324263236049326453645630106 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.kmac_entropy_refresh.95927846035288403048639319469487023596325470500972324263236049326453645630106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.112933769649789879074434991097951570104102795646801931412279922283266744217366
Short name T611
Test name
Test status
Simulation time 8615085608 ps
CPU time 129.13 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 01:55:56 PM PST 23
Peak memory 248612 kb
Host smart-ffdf5476-23ef-4557-b8a1-acc73cd8e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112933769649789879074434991097951570104102795646801931412279922283266744217366 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.kmac_error.112933769649789879074434991097951570104102795646801931412279922283266744217366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.28884140562273686761567606924037310168842348617252429974010995221510375930929
Short name T1024
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.19 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:54:01 PM PST 23
Peak memory 207504 kb
Host smart-6b2f7116-7b81-477c-b04c-e25e2c5e750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28884140562273686761567606924037310168842348617252429974010995221510375930929 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.kmac_key_error.28884140562273686761567606924037310168842348617252429974010995221510375930929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.30684269173887278069792861949746282436690774395360171360141002480254548795252
Short name T544
Test name
Test status
Simulation time 58171921 ps
CPU time 1.28 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:53:54 PM PST 23
Peak memory 215780 kb
Host smart-e4f2b4e9-b83d-4e4a-8da7-96f8354897e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30684269173887278069792861949746282436690774395360171360141002480254548795252 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.kmac_lc_escalation.30684269173887278069792861949746282436690774395360171360141002480254548795252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.25396522030802070450985652879208041904357249143600991680294549249130291306536
Short name T865
Test name
Test status
Simulation time 45517522529 ps
CPU time 710.69 seconds
Started Nov 22 01:53:23 PM PST 23
Finished Nov 22 02:05:15 PM PST 23
Peak memory 288384 kb
Host smart-63d8507b-1679-4775-bdd3-994f6d7e4ea7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25396522030802070450985652879208041904357249143600991680294549249130291306536 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.253965220308020704509856528792080419043572491436009916802945492491302
91306536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.23604142653898381741883289337563477041028605432725890984760875636421672484081
Short name T935
Test name
Test status
Simulation time 7733092664 ps
CPU time 107.23 seconds
Started Nov 22 01:53:37 PM PST 23
Finished Nov 22 01:55:26 PM PST 23
Peak memory 228104 kb
Host smart-f230a574-bf3d-4454-80e0-a5c43bdce7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23604142653898381741883289337563477041028605432725890984760875636421672484081 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.kmac_sideload.23604142653898381741883289337563477041028605432725890984760875636421672484081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.49364380680800616007675767283314748694076449355765449779784499795702169270690
Short name T548
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.81 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:53:58 PM PST 23
Peak memory 215932 kb
Host smart-ed18e4ac-4f2b-436c-b2b0-ee010c0026cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49364380680800616007675767283314748694076449355765449779784499795702169270690 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.kmac_smoke.49364380680800616007675767283314748694076449355765449779784499795702169270690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.11932633809715959486610164980712761986127393726839465754777898398896414019065
Short name T827
Test name
Test status
Simulation time 41434001626 ps
CPU time 599.02 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:03:47 PM PST 23
Peak memory 321696 kb
Host smart-dcbed6b0-a955-4ef0-9476-b8bcc726ed9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=11932633809715959486610164980712761986127393726839465754777898398896414019065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_st
ress_all.11932633809715959486610164980712761986127393726839465754777898398896414019065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.33110598533465659273581263639913205686298785743099471561810019603429927991081
Short name T838
Test name
Test status
Simulation time 298812853 ps
CPU time 4.28 seconds
Started Nov 22 01:53:21 PM PST 23
Finished Nov 22 01:53:28 PM PST 23
Peak memory 215576 kb
Host smart-a210c8f7-384e-40b6-8942-4f87a3f2156f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33110598533465659273581263639913205686298785743099471
561810019603429927991081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac.33110598533465659273581263639913205686
298785743099471561810019603429927991081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.45085605534813587428015723805114926850347780920251599782753969930537495708641
Short name T417
Test name
Test status
Simulation time 289902210 ps
CPU time 4.29 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:53:45 PM PST 23
Peak memory 215824 kb
Host smart-34032f67-f0e7-4fba-9019-a923e4137274
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45085605534813587428015723805114926850347780920251599
782753969930537495708641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac_xof.450856055348135874280157238051
14926850347780920251599782753969930537495708641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.114515954125248719339781483324133986508811676815770201465172043446086759817814
Short name T968
Test name
Test status
Simulation time 115269125226 ps
CPU time 1783.83 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 02:23:31 PM PST 23
Peak memory 389488 kb
Host smart-0456688a-2a0d-428c-9596-9af21d3efbb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114515954125248719339781483324133986508811676815770201465172043446086759817814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.kmac_test_vectors_sha3_224.114515954125248719339781483324133986508811676815770201465172043446086759817814 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.29142659842341363832526959797550848574189194437529958407124542956599116940232
Short name T951
Test name
Test status
Simulation time 107886220004 ps
CPU time 1614.21 seconds
Started Nov 22 01:53:31 PM PST 23
Finished Nov 22 02:20:26 PM PST 23
Peak memory 370120 kb
Host smart-860a2fdf-863d-452d-99df-bf4508f7492a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=29142659842341363832526959797550848574189194437529958407124542956599116940232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.kmac_test_vectors_sha3_256.29142659842341363832526959797550848574189194437529958407124542956599116940232 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.112537525849543953736717684160698322249330117103685701833442237802902197653369
Short name T918
Test name
Test status
Simulation time 83070954242 ps
CPU time 1177.56 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 02:13:20 PM PST 23
Peak memory 332844 kb
Host smart-f6d686ba-1574-4098-a4cc-9a83d130c98d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=112537525849543953736717684160698322249330117103685701833442237802902197653369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.kmac_test_vectors_sha3_384.112537525849543953736717684160698322249330117103685701833442237802902197653369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.70670595075693464848359027404751777982887603876147525807686941854805869476538
Short name T891
Test name
Test status
Simulation time 58503507926 ps
CPU time 860.42 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 02:08:00 PM PST 23
Peak memory 295824 kb
Host smart-f2fd7f7a-2abc-487b-a305-1a9c636ecc71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=70670595075693464848359027404751777982887603876147525807686941854805869476538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.kmac_test_vectors_sha3_512.70670595075693464848359027404751777982887603876147525807686941854805869476538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.20684692548463757684786456477940546043510332218208445979229244866219907372121
Short name T914
Test name
Test status
Simulation time 307766781661 ps
CPU time 4552.07 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 03:09:34 PM PST 23
Peak memory 653128 kb
Host smart-065ef92d-2c0f-414e-bb1a-c1bbedc9e610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=20684692548463757684786456477940546043510332218208445979229244866219907372121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.kmac_test_vectors_shake_128.20684692548463757684786456477940546043510332218208445979229244866219907372121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.59323684384291327646783583488050364403044604863997300741341315212417963962856
Short name T376
Test name
Test status
Simulation time 258047411562 ps
CPU time 3809.55 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 02:57:14 PM PST 23
Peak memory 556388 kb
Host smart-241a9dd3-53a2-4af7-8ea6-afafec2f1e18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=59323684384291327646783583488050364403044604863997300741341315212417963962856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.kmac_test_vectors_shake_256.59323684384291327646783583488050364403044604863997300741341315212417963962856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.85202797333468836641174496677542918226047431653162366816200900509695365607544
Short name T764
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:53:49 PM PST 23
Peak memory 205288 kb
Host smart-a90adcf5-6e2e-4207-8c8d-f10340c24461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85202797333468836641174496677542918226047431653162366816200900509695365607544 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.kmac_alert_test.85202797333468836641174496677542918226047431653162366816200900509695365607544 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.47911349085330601986492777083661946184846895488847160224579384232904277586756
Short name T1055
Test name
Test status
Simulation time 5659537824 ps
CPU time 78.25 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:55:06 PM PST 23
Peak memory 227356 kb
Host smart-36945dfa-1f22-4502-8d63-762ed0baf5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47911349085330601986492777083661946184846895488847160224579384232904277586756 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.kmac_app.47911349085330601986492777083661946184846895488847160224579384232904277586756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.66800152361394650740455390711002353574033636149372432144185041071747095684089
Short name T339
Test name
Test status
Simulation time 14812750312 ps
CPU time 239.73 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 01:57:52 PM PST 23
Peak memory 225504 kb
Host smart-1ebf90fe-519b-4760-85be-1eb1caa401b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66800152361394650740455390711002353574033636149372432144185041071747095684089 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.kmac_burst_write.66800152361394650740455390711002353574033636149372432144185041071747095684089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.98814474584267901789785729643604673739323199687431679236239734590400091799484
Short name T747
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.22 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:54:55 PM PST 23
Peak memory 227056 kb
Host smart-c7ff5ef0-4523-481d-84a9-8c296101a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98814474584267901789785729643604673739323199687431679236239734590400091799484 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.kmac_entropy_refresh.98814474584267901789785729643604673739323199687431679236239734590400091799484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.108582266278524835899935004541912711526348438016000858323579718004980469599419
Short name T870
Test name
Test status
Simulation time 8615085608 ps
CPU time 125.45 seconds
Started Nov 22 01:54:03 PM PST 23
Finished Nov 22 01:56:10 PM PST 23
Peak memory 248472 kb
Host smart-d6206733-9479-493c-ad3f-b8ee6e9c598c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108582266278524835899935004541912711526348438016000858323579718004980469599419 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.kmac_error.108582266278524835899935004541912711526348438016000858323579718004980469599419 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.105860344660039436482431775798857414415914377951490533130320972979676286485551
Short name T1073
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.18 seconds
Started Nov 22 01:53:52 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 207528 kb
Host smart-f6979a10-0b4b-44f3-a971-fe0629d712e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105860344660039436482431775798857414415914377951490533130320972979676286485551 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.kmac_key_error.105860344660039436482431775798857414415914377951490533130320972979676286485551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.81070697826652297593764358457956096895443764149496362702888287312884265873706
Short name T431
Test name
Test status
Simulation time 58171921 ps
CPU time 1.2 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 215752 kb
Host smart-14a7b69d-7d43-4b65-a1cb-55b294d94cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81070697826652297593764358457956096895443764149496362702888287312884265873706 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.kmac_lc_escalation.81070697826652297593764358457956096895443764149496362702888287312884265873706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.104165886614211197331272229834554849981563109115971693391897019279721000819997
Short name T541
Test name
Test status
Simulation time 45517522529 ps
CPU time 698.63 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 02:05:28 PM PST 23
Peak memory 288328 kb
Host smart-225bcbad-aa88-4d03-816f-0aaaa269dff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104165886614211197331272229834554849981563109115971693391897019279721000819997 -assert n
opostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.10416588661421119733127222983455484998156310911597169339189701927972
1000819997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.2373164741339491426945574345075108024798178112406502861478419362740476829520
Short name T986
Test name
Test status
Simulation time 7733092664 ps
CPU time 108.22 seconds
Started Nov 22 01:53:48 PM PST 23
Finished Nov 22 01:55:38 PM PST 23
Peak memory 228160 kb
Host smart-6229c6d5-1af2-4077-b334-001f4f4a1a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373164741339491426945574345075108024798178112406502861478419362740476829520 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.kmac_sideload.2373164741339491426945574345075108024798178112406502861478419362740476829520 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.4129862111670847783437168896802639198803969809490914374656485584862782032556
Short name T335
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.34 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 01:54:11 PM PST 23
Peak memory 215940 kb
Host smart-8da6030f-5f24-4c91-b6eb-b2a79338a723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129862111670847783437168896802639198803969809490914374656485584862782032556 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.kmac_smoke.4129862111670847783437168896802639198803969809490914374656485584862782032556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.114173719644559917927896008646522770377821757392774318488007362113550452981425
Short name T569
Test name
Test status
Simulation time 41434001626 ps
CPU time 628.12 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 02:04:24 PM PST 23
Peak memory 321708 kb
Host smart-86a6241c-6cd2-4c68-bcbf-1f2f038dfc64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=114173719644559917927896008646522770377821757392774318488007362113550452981425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_s
tress_all.114173719644559917927896008646522770377821757392774318488007362113550452981425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.33473755182153939329064558859885293169782987862515004447793621204757690451154
Short name T482
Test name
Test status
Simulation time 298812853 ps
CPU time 4.33 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:53:52 PM PST 23
Peak memory 215812 kb
Host smart-e9bbead5-c700-437c-b8fc-1b415dc2fdb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473755182153939329064558859885293169782987862515004
447793621204757690451154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac.33473755182153939329064558859885293169
782987862515004447793621204757690451154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.83198763551677154399907093685305432507438119869777261546711515006594268233977
Short name T628
Test name
Test status
Simulation time 289902210 ps
CPU time 4.19 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 01:53:46 PM PST 23
Peak memory 215772 kb
Host smart-22e6a617-ec4d-4f00-8657-0f26e1a6a57b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83198763551677154399907093685305432507438119869777261
546711515006594268233977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.831987635516771543999070936853
05432507438119869777261546711515006594268233977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.91424384967386868784213553979460519935295191221002769397979411739874285675023
Short name T219
Test name
Test status
Simulation time 115269125226 ps
CPU time 1694.05 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 02:22:06 PM PST 23
Peak memory 390292 kb
Host smart-7ac7565b-cab9-4efe-9cd9-1bc352aded95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=91424384967386868784213553979460519935295191221002769397979411739874285675023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.kmac_test_vectors_sha3_224.91424384967386868784213553979460519935295191221002769397979411739874285675023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.86550853880773360180413835564779725328256789303823334637473998168085025293979
Short name T310
Test name
Test status
Simulation time 107886220004 ps
CPU time 1687.43 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 02:21:49 PM PST 23
Peak memory 370128 kb
Host smart-da3971d0-ae17-4fe8-9b5e-ff6716ebd213
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=86550853880773360180413835564779725328256789303823334637473998168085025293979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.kmac_test_vectors_sha3_256.86550853880773360180413835564779725328256789303823334637473998168085025293979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.54654812805435702008633827365281165443631672529962802872485533765417542379249
Short name T750
Test name
Test status
Simulation time 83070954242 ps
CPU time 1248.76 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 02:14:45 PM PST 23
Peak memory 332868 kb
Host smart-af6d13a2-bba7-466b-83fd-57713b4f8d9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=54654812805435702008633827365281165443631672529962802872485533765417542379249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.kmac_test_vectors_sha3_384.54654812805435702008633827365281165443631672529962802872485533765417542379249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.80210110280306954498400029514329472406017353289066145092064168798640234325833
Short name T804
Test name
Test status
Simulation time 58503507926 ps
CPU time 901.61 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 02:08:39 PM PST 23
Peak memory 295952 kb
Host smart-2014d3a8-6ec3-4f9f-bacd-6f8a76efcc08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=80210110280306954498400029514329472406017353289066145092064168798640234325833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.kmac_test_vectors_sha3_512.80210110280306954498400029514329472406017353289066145092064168798640234325833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.35493434944701225570445170569827444847354794741483429394443241184999626950870
Short name T460
Test name
Test status
Simulation time 307766781661 ps
CPU time 4443.08 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 03:07:45 PM PST 23
Peak memory 653180 kb
Host smart-8bf0cb27-9f08-420d-b9be-ec0b5f482f73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=35493434944701225570445170569827444847354794741483429394443241184999626950870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.kmac_test_vectors_shake_128.35493434944701225570445170569827444847354794741483429394443241184999626950870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.89359939349861746949977169843372793881495530469361471070336513571186856446505
Short name T486
Test name
Test status
Simulation time 258047411562 ps
CPU time 3563.91 seconds
Started Nov 22 01:53:38 PM PST 23
Finished Nov 22 02:53:03 PM PST 23
Peak memory 556204 kb
Host smart-f39ba257-fe15-40bb-861f-ef65d756193a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=89359939349861746949977169843372793881495530469361471070336513571186856446505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.kmac_test_vectors_shake_256.89359939349861746949977169843372793881495530469361471070336513571186856446505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.56127599912896063354835002358172893613438829334921935066082069465462688835807
Short name T680
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 01:53:48 PM PST 23
Peak memory 205268 kb
Host smart-0ff0018b-9c45-4614-a7f5-66829b467793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56127599912896063354835002358172893613438829334921935066082069465462688835807 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.kmac_alert_test.56127599912896063354835002358172893613438829334921935066082069465462688835807 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.69752970874858667567505592459180103187094477197357326649991480824037472157447
Short name T354
Test name
Test status
Simulation time 5659537824 ps
CPU time 75.24 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 227380 kb
Host smart-1a9abcb2-372e-4259-bdba-586938f4e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69752970874858667567505592459180103187094477197357326649991480824037472157447 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.kmac_app.69752970874858667567505592459180103187094477197357326649991480824037472157447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.50921914158333061072045148840484399023957554877463994355150074717905280423189
Short name T258
Test name
Test status
Simulation time 14812750312 ps
CPU time 246.89 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:57:51 PM PST 23
Peak memory 225668 kb
Host smart-770014f5-8ff4-46df-a70e-8e1a1a7e627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50921914158333061072045148840484399023957554877463994355150074717905280423189 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.kmac_burst_write.50921914158333061072045148840484399023957554877463994355150074717905280423189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.70390722811330063501011743360255863943649367890261758658115314430903069814613
Short name T49
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.36 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 01:55:10 PM PST 23
Peak memory 226964 kb
Host smart-dfbcf617-d351-4841-85e7-d9960a156e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70390722811330063501011743360255863943649367890261758658115314430903069814613 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.kmac_entropy_refresh.70390722811330063501011743360255863943649367890261758658115314430903069814613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.21812597902664851007398590099940244941523280119435095266965595906347556041850
Short name T572
Test name
Test status
Simulation time 8615085608 ps
CPU time 131.18 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:55:59 PM PST 23
Peak memory 248620 kb
Host smart-10ae837c-0b5e-42db-a916-5210fd15745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21812597902664851007398590099940244941523280119435095266965595906347556041850 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.kmac_error.21812597902664851007398590099940244941523280119435095266965595906347556041850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.50012123555425561599709468869339606076355780298265278928354011455997266898733
Short name T1038
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.12 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:53:48 PM PST 23
Peak memory 207556 kb
Host smart-8c53a598-1bea-4d27-911f-c6caba2f853f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50012123555425561599709468869339606076355780298265278928354011455997266898733 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.kmac_key_error.50012123555425561599709468869339606076355780298265278928354011455997266898733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.50850506696133476297222809438220902248678873435719350652951122913111231467967
Short name T716
Test name
Test status
Simulation time 58171921 ps
CPU time 1.23 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:53:49 PM PST 23
Peak memory 215756 kb
Host smart-1af31a36-78c2-4cfa-a307-0634fbf1c4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50850506696133476297222809438220902248678873435719350652951122913111231467967 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.kmac_lc_escalation.50850506696133476297222809438220902248678873435719350652951122913111231467967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.18078948674575496901626752462300781093823924452755720105799296037378548603718
Short name T456
Test name
Test status
Simulation time 45517522529 ps
CPU time 687.33 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:05:16 PM PST 23
Peak memory 288340 kb
Host smart-13943f17-b6fe-473a-95ed-af6a74d9af6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18078948674575496901626752462300781093823924452755720105799296037378548603718 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.180789486745754969016267524623007810938239244527557201057992960373785
48603718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.49824556880799245397484260749809516963506401288503047207671032568445478006057
Short name T184
Test name
Test status
Simulation time 7733092664 ps
CPU time 111.04 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 01:55:58 PM PST 23
Peak memory 228080 kb
Host smart-7bb25bd4-1e4d-40a8-867a-46a4968d8f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49824556880799245397484260749809516963506401288503047207671032568445478006057 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.kmac_sideload.49824556880799245397484260749809516963506401288503047207671032568445478006057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.94762708765367008339151973574171022336706469222955975334245339294101972362081
Short name T919
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.93 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 01:53:59 PM PST 23
Peak memory 215944 kb
Host smart-1dfe7a3a-348e-45a6-aa32-c39405dd2113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94762708765367008339151973574171022336706469222955975334245339294101972362081 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.kmac_smoke.94762708765367008339151973574171022336706469222955975334245339294101972362081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.76299668550657608852897362902949349495114301898207710644912431754524661905912
Short name T798
Test name
Test status
Simulation time 41434001626 ps
CPU time 605.52 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 02:04:02 PM PST 23
Peak memory 321640 kb
Host smart-e20c198e-bc26-49cd-aef9-eaa0b901ea1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=76299668550657608852897362902949349495114301898207710644912431754524661905912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_st
ress_all.76299668550657608852897362902949349495114301898207710644912431754524661905912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.25402201419809390650083304843876994303381853252286156205791254191848631054028
Short name T651
Test name
Test status
Simulation time 298812853 ps
CPU time 4.38 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:53:49 PM PST 23
Peak memory 215824 kb
Host smart-c0ae9153-91d2-482c-b5fa-62ae4ed6ee78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402201419809390650083304843876994303381853252286156
205791254191848631054028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac.25402201419809390650083304843876994303
381853252286156205791254191848631054028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.97008120559057816634146579871313409418048666648124806174751491373522438530179
Short name T462
Test name
Test status
Simulation time 289902210 ps
CPU time 4.03 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:53:53 PM PST 23
Peak memory 215864 kb
Host smart-220c7fbf-d64a-49fe-8f75-2657d05af67c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97008120559057816634146579871313409418048666648124806
174751491373522438530179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.970081205590578166341465798713
13409418048666648124806174751491373522438530179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.82692062225679520187610036675627448465288662231928774754217531532568219900636
Short name T1023
Test name
Test status
Simulation time 115269125226 ps
CPU time 1747.95 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 02:22:55 PM PST 23
Peak memory 390440 kb
Host smart-a33b6409-0795-47c9-9ea8-d5adc37a3ff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=82692062225679520187610036675627448465288662231928774754217531532568219900636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_224.82692062225679520187610036675627448465288662231928774754217531532568219900636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.68696401843042406806522330740501394319693396676725620015494002780901816952259
Short name T1032
Test name
Test status
Simulation time 107886220004 ps
CPU time 1613.53 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 02:20:43 PM PST 23
Peak memory 370200 kb
Host smart-006735bb-a9b0-4596-aece-b1cfe3a240c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=68696401843042406806522330740501394319693396676725620015494002780901816952259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_256.68696401843042406806522330740501394319693396676725620015494002780901816952259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.38564469773460366266038061650640774541240309447981517815705831003782070607828
Short name T1057
Test name
Test status
Simulation time 83070954242 ps
CPU time 1255.18 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 02:14:38 PM PST 23
Peak memory 332920 kb
Host smart-1817dc86-6adb-4547-858d-6aa924ff29a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38564469773460366266038061650640774541240309447981517815705831003782070607828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_384.38564469773460366266038061650640774541240309447981517815705831003782070607828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.46018124620059420929450400811409563192028130076269723223133002426058049766842
Short name T360
Test name
Test status
Simulation time 58503507926 ps
CPU time 873.32 seconds
Started Nov 22 01:53:48 PM PST 23
Finished Nov 22 02:08:23 PM PST 23
Peak memory 295896 kb
Host smart-eaf8c0b7-a197-4f9d-8930-961dd3cdee15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=46018124620059420929450400811409563192028130076269723223133002426058049766842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.kmac_test_vectors_sha3_512.46018124620059420929450400811409563192028130076269723223133002426058049766842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.98778352612041879364121759251581169132876957524703757739668585531451790585686
Short name T634
Test name
Test status
Simulation time 307766781661 ps
CPU time 4385.57 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 03:06:47 PM PST 23
Peak memory 653224 kb
Host smart-1b1ae1d8-489f-48e3-8c9e-5286cd6c5830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=98778352612041879364121759251581169132876957524703757739668585531451790585686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.kmac_test_vectors_shake_128.98778352612041879364121759251581169132876957524703757739668585531451790585686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.69042833111342136947788766772757339148685314347717006960611544776560783419432
Short name T491
Test name
Test status
Simulation time 258047411562 ps
CPU time 3706.62 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 02:55:36 PM PST 23
Peak memory 556280 kb
Host smart-e130f145-1761-409d-8e43-47398396cda9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=69042833111342136947788766772757339148685314347717006960611544776560783419432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.kmac_test_vectors_shake_256.69042833111342136947788766772757339148685314347717006960611544776560783419432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.46977626992687804873974887956345066650921972323785304562944371392686213069863
Short name T958
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:53:56 PM PST 23
Peak memory 205204 kb
Host smart-bea85cb1-64ff-4884-b31a-81e1dc5a00e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46977626992687804873974887956345066650921972323785304562944371392686213069863 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.kmac_alert_test.46977626992687804873974887956345066650921972323785304562944371392686213069863 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.78246051476523602071566651521111803639748132598696433548228865499485698122837
Short name T885
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.05 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 227348 kb
Host smart-b6cd20d6-d7fb-4544-b3e0-de9c946201b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78246051476523602071566651521111803639748132598696433548228865499485698122837 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.kmac_app.78246051476523602071566651521111803639748132598696433548228865499485698122837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.17798484001291225675489989092919771417403365185659779451178327237963777496156
Short name T76
Test name
Test status
Simulation time 14812750312 ps
CPU time 244.66 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:57:46 PM PST 23
Peak memory 225572 kb
Host smart-2f1796f9-33fc-483e-ad3a-edd3ced79f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17798484001291225675489989092919771417403365185659779451178327237963777496156 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.kmac_burst_write.17798484001291225675489989092919771417403365185659779451178327237963777496156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.108598841213929932285128345392085605031734061330950674522939034773326235658773
Short name T1029
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.67 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 01:54:50 PM PST 23
Peak memory 227036 kb
Host smart-c071ff11-ae8b-4cfc-b47a-ecf2288a80d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108598841213929932285128345392085605031734061330950674522939034773326235658773 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.kmac_entropy_refresh.108598841213929932285128345392085605031734061330950674522939034773326235658773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.74146360967471501716141296168775810962772735266189891215469229122772906215978
Short name T200
Test name
Test status
Simulation time 8615085608 ps
CPU time 126.43 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 01:55:58 PM PST 23
Peak memory 248564 kb
Host smart-3f164bd4-eb43-4cc8-b53c-ad706db3e97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74146360967471501716141296168775810962772735266189891215469229122772906215978 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.kmac_error.74146360967471501716141296168775810962772735266189891215469229122772906215978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.91546275856743173018668627967883368569828791749674357934545890430600423862948
Short name T892
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.19 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 207384 kb
Host smart-e5802373-e5ca-4d50-8d02-d92475bcfe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91546275856743173018668627967883368569828791749674357934545890430600423862948 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.kmac_key_error.91546275856743173018668627967883368569828791749674357934545890430600423862948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.22462179329493809833111110606441925102612334780639231133518974018276367176589
Short name T391
Test name
Test status
Simulation time 58171921 ps
CPU time 1.26 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:53:45 PM PST 23
Peak memory 215756 kb
Host smart-ca25e47d-4b23-4e53-b9f2-97e6bc258636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22462179329493809833111110606441925102612334780639231133518974018276367176589 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.kmac_lc_escalation.22462179329493809833111110606441925102612334780639231133518974018276367176589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.7527451778533858818741611465091162480991296587705768838713432912515810281800
Short name T192
Test name
Test status
Simulation time 45517522529 ps
CPU time 719.98 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 02:05:41 PM PST 23
Peak memory 288368 kb
Host smart-e1780057-8e01-4eaf-9f1e-b6899272bf4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7527451778533858818741611465091162480991296587705768838713432912515810281800 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.7527451778533858818741611465091162480991296587705768838713432912515810
281800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.54816031651441508102880850800327665964073040780636221166697157595217305495769
Short name T349
Test name
Test status
Simulation time 7733092664 ps
CPU time 108.51 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:55:32 PM PST 23
Peak memory 228164 kb
Host smart-31c732c9-cc0f-4a5d-9e45-c999561b827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54816031651441508102880850800327665964073040780636221166697157595217305495769 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.kmac_sideload.54816031651441508102880850800327665964073040780636221166697157595217305495769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.35736510777869676382662129298601038626784230141219371544648081445084405393067
Short name T370
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.6 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 01:54:16 PM PST 23
Peak memory 215832 kb
Host smart-7395c8fd-02c5-426d-b4f9-0c17b22cbf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35736510777869676382662129298601038626784230141219371544648081445084405393067 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.kmac_smoke.35736510777869676382662129298601038626784230141219371544648081445084405393067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.21772760426450459133459431803229530181893408238270427271976286619200680047392
Short name T79
Test name
Test status
Simulation time 41434001626 ps
CPU time 616.61 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 02:04:11 PM PST 23
Peak memory 321672 kb
Host smart-fac71e0b-e9af-48ab-a36e-4acd75ed5029
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=21772760426450459133459431803229530181893408238270427271976286619200680047392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_st
ress_all.21772760426450459133459431803229530181893408238270427271976286619200680047392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.52908970364749506678908906727318110764505904511079553597006373478066797859472
Short name T273
Test name
Test status
Simulation time 298812853 ps
CPU time 4.13 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 01:54:01 PM PST 23
Peak memory 215748 kb
Host smart-58758b75-2825-40ff-ba0f-b4a099f95814
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52908970364749506678908906727318110764505904511079553
597006373478066797859472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac.52908970364749506678908906727318110764
505904511079553597006373478066797859472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.50151821005120897111204473739791870772867763345624245232093212914971044428697
Short name T557
Test name
Test status
Simulation time 289902210 ps
CPU time 4.12 seconds
Started Nov 22 01:53:48 PM PST 23
Finished Nov 22 01:53:54 PM PST 23
Peak memory 215860 kb
Host smart-cf61bbf9-15fe-4948-97b7-97fef9ece36e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50151821005120897111204473739791870772867763345624245
232093212914971044428697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.501518210051208971112044737397
91870772867763345624245232093212914971044428697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.77259650544680769188531867897919446262230880617128283415205492023917042669685
Short name T495
Test name
Test status
Simulation time 115269125226 ps
CPU time 1702.44 seconds
Started Nov 22 01:54:03 PM PST 23
Finished Nov 22 02:22:27 PM PST 23
Peak memory 390216 kb
Host smart-14ec9a7a-9288-494d-b435-2f6f9f7fb0c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77259650544680769188531867897919446262230880617128283415205492023917042669685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.kmac_test_vectors_sha3_224.77259650544680769188531867897919446262230880617128283415205492023917042669685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.11816001264953715659406129018655951506159557537140565828145636375379597058850
Short name T757
Test name
Test status
Simulation time 107886220004 ps
CPU time 1623.28 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:20:51 PM PST 23
Peak memory 370180 kb
Host smart-a15f6cda-78e8-48d7-a60d-6297b0f37014
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11816001264953715659406129018655951506159557537140565828145636375379597058850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.kmac_test_vectors_sha3_256.11816001264953715659406129018655951506159557537140565828145636375379597058850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.81448932174468250945201801333849523043306604184442956893826911412914949902001
Short name T133
Test name
Test status
Simulation time 83070954242 ps
CPU time 1230.09 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 02:14:13 PM PST 23
Peak memory 332932 kb
Host smart-591baedc-f79b-46fd-a214-fc016bd53777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=81448932174468250945201801333849523043306604184442956893826911412914949902001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.kmac_test_vectors_sha3_384.81448932174468250945201801333849523043306604184442956893826911412914949902001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.88503718701403005422132753264657487102786016297523257548310285344827618567502
Short name T839
Test name
Test status
Simulation time 58503507926 ps
CPU time 869.25 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 02:08:18 PM PST 23
Peak memory 295816 kb
Host smart-8f4d6675-d300-4e6c-bd47-1cf0c4747708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=88503718701403005422132753264657487102786016297523257548310285344827618567502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.kmac_test_vectors_sha3_512.88503718701403005422132753264657487102786016297523257548310285344827618567502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.72785659557252607281335695985771300301452494140653415914308977292019152617785
Short name T701
Test name
Test status
Simulation time 307766781661 ps
CPU time 4595.88 seconds
Started Nov 22 01:53:40 PM PST 23
Finished Nov 22 03:10:18 PM PST 23
Peak memory 653216 kb
Host smart-8cf3f16a-c984-4932-8997-7ab692e94d8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=72785659557252607281335695985771300301452494140653415914308977292019152617785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.kmac_test_vectors_shake_128.72785659557252607281335695985771300301452494140653415914308977292019152617785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.46344464216272527878825811600402398847349109099413951453761184438565980308774
Short name T277
Test name
Test status
Simulation time 258047411562 ps
CPU time 3650.69 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 02:54:35 PM PST 23
Peak memory 556220 kb
Host smart-93695e79-4f4f-4dff-9dde-e5b110683c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=46344464216272527878825811600402398847349109099413951453761184438565980308774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.kmac_test_vectors_shake_256.46344464216272527878825811600402398847349109099413951453761184438565980308774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.113986695000080173721187634354855641461246740264514780608805106901655405461166
Short name T640
Test name
Test status
Simulation time 21118646 ps
CPU time 0.76 seconds
Started Nov 22 01:53:57 PM PST 23
Finished Nov 22 01:53:59 PM PST 23
Peak memory 205212 kb
Host smart-110d306c-d2c6-433f-b7d1-17f2cc2b9753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113986695000080173721187634354855641461246740264514780608805106901655405461166 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.113986695000080173721187634354855641461246740264514780608805106901655405461166 +enable_masking=0
+sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.22425245528924980191203563629775643150730563348889731327275085820341553328170
Short name T490
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.17 seconds
Started Nov 22 01:54:06 PM PST 23
Finished Nov 22 01:55:23 PM PST 23
Peak memory 227288 kb
Host smart-fad0c7b4-8c0b-4b68-8982-38f1f47637d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22425245528924980191203563629775643150730563348889731327275085820341553328170 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.kmac_app.22425245528924980191203563629775643150730563348889731327275085820341553328170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.82334536347155517908620904238820059800398634332788501581974965551474854169106
Short name T297
Test name
Test status
Simulation time 14812750312 ps
CPU time 244.71 seconds
Started Nov 22 01:53:52 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 225544 kb
Host smart-b9850049-0bfa-43fc-b1b6-27e6c239973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82334536347155517908620904238820059800398634332788501581974965551474854169106 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.kmac_burst_write.82334536347155517908620904238820059800398634332788501581974965551474854169106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.107253701041242351335222059879419299300796186731655218571038838276068488126719
Short name T318
Test name
Test status
Simulation time 6743332725 ps
CPU time 76.75 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 01:55:16 PM PST 23
Peak memory 227000 kb
Host smart-e2839660-44cd-49ba-86f6-fa936613c9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107253701041242351335222059879419299300796186731655218571038838276068488126719 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_entropy_refresh.107253701041242351335222059879419299300796186731655218571038838276068488126719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.7340094314176409189654100321844369992543095570781854954374772743760571353065
Short name T196
Test name
Test status
Simulation time 8615085608 ps
CPU time 125.64 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:55:49 PM PST 23
Peak memory 248532 kb
Host smart-78ab41e8-3e4d-4a32-9a36-b43482c70177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7340094314176409189654100321844369992543095570781854954374772743760571353065 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.kmac_error.7340094314176409189654100321844369992543095570781854954374772743760571353065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.94836607878460127705990237071668669243066669856412774566366757130137915465448
Short name T62
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.13 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 207440 kb
Host smart-65de050d-130f-4517-a539-be3da5036faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94836607878460127705990237071668669243066669856412774566366757130137915465448 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.kmac_key_error.94836607878460127705990237071668669243066669856412774566366757130137915465448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.95270197411044153905963633588918838750283641989701684144368617950855903289653
Short name T717
Test name
Test status
Simulation time 58171921 ps
CPU time 1.31 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 215728 kb
Host smart-10fc182f-9826-48a0-bf7c-e5d872195759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95270197411044153905963633588918838750283641989701684144368617950855903289653 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.kmac_lc_escalation.95270197411044153905963633588918838750283641989701684144368617950855903289653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.11031451468714119322021447106125075773556578355739276195321756638627470392228
Short name T595
Test name
Test status
Simulation time 45517522529 ps
CPU time 697.8 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 02:05:30 PM PST 23
Peak memory 288304 kb
Host smart-fafb3339-6061-4436-9c47-7a5bfbe2504a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031451468714119322021447106125075773556578355739276195321756638627470392228 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.110314514687141193220214471061250757735565783557392761953217566386274
70392228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.82134753580270748685054445016845715175966462159935711498207189861240891987110
Short name T835
Test name
Test status
Simulation time 7733092664 ps
CPU time 112.41 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 01:56:08 PM PST 23
Peak memory 228120 kb
Host smart-6675af29-556a-4314-a8f6-60c94d6f3d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82134753580270748685054445016845715175966462159935711498207189861240891987110 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.kmac_sideload.82134753580270748685054445016845715175966462159935711498207189861240891987110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.34103993932239272766165390926992751871335007173668171230983741491730500728900
Short name T216
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.22 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 215968 kb
Host smart-224e8b94-4c0f-43e1-87ca-630c9d8c4523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34103993932239272766165390926992751871335007173668171230983741491730500728900 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.kmac_smoke.34103993932239272766165390926992751871335007173668171230983741491730500728900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.105028123700668412909655887806774372587767166409136580810619149835817359143086
Short name T317
Test name
Test status
Simulation time 41434001626 ps
CPU time 623.58 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 02:04:20 PM PST 23
Peak memory 321724 kb
Host smart-ee967686-9acc-4fca-8305-ec671da09404
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=105028123700668412909655887806774372587767166409136580810619149835817359143086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_s
tress_all.105028123700668412909655887806774372587767166409136580810619149835817359143086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.75632856175093465047703044776660380267955296450546130380207865406817779614147
Short name T619
Test name
Test status
Simulation time 298812853 ps
CPU time 4.6 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 215820 kb
Host smart-831cc6f5-ec93-4306-bd0b-07ae13486243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75632856175093465047703044776660380267955296450546130
380207865406817779614147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac.75632856175093465047703044776660380267
955296450546130380207865406817779614147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.3335939783300076057751177659398019098054811055277002454038219713908313674019
Short name T301
Test name
Test status
Simulation time 289902210 ps
CPU time 3.94 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 01:53:55 PM PST 23
Peak memory 215656 kb
Host smart-f75dc0c5-a607-49a7-926b-e3f00f29b921
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33359397833000760577511776593980190980548110552770024
54038219713908313674019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.3335939783300076057751177659398
019098054811055277002454038219713908313674019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.97298083907008749773078079050069707130293512238523726805220486059237196459440
Short name T181
Test name
Test status
Simulation time 115269125226 ps
CPU time 1698.37 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 02:22:11 PM PST 23
Peak memory 390388 kb
Host smart-7fe628d0-7662-45db-a9be-8dfec270fb96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=97298083907008749773078079050069707130293512238523726805220486059237196459440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_224.97298083907008749773078079050069707130293512238523726805220486059237196459440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.23515265959215860680832205152032672276114986822477605008846985799262707029448
Short name T553
Test name
Test status
Simulation time 107886220004 ps
CPU time 1623.04 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 370144 kb
Host smart-f1f05976-d8d9-45b9-a81c-b72887c379d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=23515265959215860680832205152032672276114986822477605008846985799262707029448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_256.23515265959215860680832205152032672276114986822477605008846985799262707029448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.68325249716168012231088037510604893913409648788234932503338598563948738643292
Short name T446
Test name
Test status
Simulation time 83070954242 ps
CPU time 1238.98 seconds
Started Nov 22 01:54:17 PM PST 23
Finished Nov 22 02:14:57 PM PST 23
Peak memory 332912 kb
Host smart-3a7d8010-477e-479f-bd78-427c5a2880c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=68325249716168012231088037510604893913409648788234932503338598563948738643292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_384.68325249716168012231088037510604893913409648788234932503338598563948738643292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.14083260071751189831967907938735477724619358671205002655615210742571842273472
Short name T128
Test name
Test status
Simulation time 58503507926 ps
CPU time 871.74 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 02:08:46 PM PST 23
Peak memory 295856 kb
Host smart-0f13b4e2-46ce-44ea-9d99-96819b086b09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=14083260071751189831967907938735477724619358671205002655615210742571842273472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.kmac_test_vectors_sha3_512.14083260071751189831967907938735477724619358671205002655615210742571842273472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.107114802727222254457274266322557968739265467884205073101903832776866811597659
Short name T312
Test name
Test status
Simulation time 307766781661 ps
CPU time 4507.06 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 03:08:55 PM PST 23
Peak memory 653332 kb
Host smart-9b79b03e-1f3b-4af3-8deb-b4ca8db903f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=107114802727222254457274266322557968739265467884205073101903832776866811597659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.kmac_test_vectors_shake_128.107114802727222254457274266322557968739265467884205073101903832776866811597659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.69702871499080502276053166813603344847260233013367648002617701314130084011108
Short name T974
Test name
Test status
Simulation time 258047411562 ps
CPU time 3680.2 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 02:55:33 PM PST 23
Peak memory 556304 kb
Host smart-9cba67ac-4f3c-41e4-81f9-3602a30faefd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=69702871499080502276053166813603344847260233013367648002617701314130084011108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.kmac_test_vectors_shake_256.69702871499080502276053166813603344847260233013367648002617701314130084011108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.55829657524784919413867339712984779987295613357003361899704564690839817934239
Short name T137
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:52:47 PM PST 23
Peak memory 205232 kb
Host smart-dd28a73d-6caf-45cc-aeba-4920ca3cd11e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55829657524784919413867339712984779987295613357003361899704564690839817934239 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.kmac_alert_test.55829657524784919413867339712984779987295613357003361899704564690839817934239 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.18362766412482240571795737704243132497516479317984463628409258019328407557482
Short name T647
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.07 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 227352 kb
Host smart-9c1f8439-1064-497b-8af9-a948ecd166e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18362766412482240571795737704243132497516479317984463628409258019328407557482 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.kmac_app.18362766412482240571795737704243132497516479317984463628409258019328407557482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.84360902884165033410157336639547294310332551230709471263872605499769032366054
Short name T514
Test name
Test status
Simulation time 7615861459 ps
CPU time 83.36 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:54:15 PM PST 23
Peak memory 226040 kb
Host smart-456c9daf-fcaf-4a25-b437-8d80ffe5ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84360902884165033410157336639547294310332551230709471263872605499769032366054 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_app_with_partial_data.84360902884165033410157336639547294310332551230709471263872605499769032366054 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.77355814780924842575988146734237923513181715096680199943568439796089660537906
Short name T771
Test name
Test status
Simulation time 14812750312 ps
CPU time 236.15 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:56:44 PM PST 23
Peak memory 225176 kb
Host smart-60bca772-5fa1-4bcf-b00c-ffbdf1b992f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77355814780924842575988146734237923513181715096680199943568439796089660537906 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.kmac_burst_write.77355814780924842575988146734237923513181715096680199943568439796089660537906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.64873751039675951534714102373927905489806817951537379215047636869777365341129
Short name T1008
Test name
Test status
Simulation time 2342046507 ps
CPU time 33.92 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 223880 kb
Host smart-79b291fd-ba9e-4d60-8a9a-79e439e2d744
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=64873751039675951534714102373927905489806817951537379215047636869777365341129 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.kmac_edn_timeout_error.64873751039675951534714102373927905489806817951537379215047636869777365341129 +enable_masking=0
+sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.104155464830943829443774748904845213671299801426902848846463547415865840412845
Short name T396
Test name
Test status
Simulation time 2211297553 ps
CPU time 31.12 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 223952 kb
Host smart-8d4db6be-901d-4556-acbc-ef88d9bea264
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104155464830943829443774748904845213671299801426902848846463547415865840412845 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.104155464830943829443774748904845213671299801426902848846463547415865840412845 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.90643908571291025467687213360479785461063194156793713397619196791645426983614
Short name T29
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.28 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 01:53:11 PM PST 23
Peak memory 216856 kb
Host smart-fbf921b5-f0d1-44b6-b07f-282041d65e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90643908571291025467687213360479785461063194156793713397619196791645426983614 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.kmac_entropy_ready_error.90643908571291025467687213360479785461063194156793713397619196791645426983614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.12875120820784084695865293542742735428327958577573021100220148624189745024914
Short name T625
Test name
Test status
Simulation time 6743332725 ps
CPU time 74.24 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 227024 kb
Host smart-20d8aa11-5ea6-4f64-a635-37c31c0ee0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12875120820784084695865293542742735428327958577573021100220148624189745024914 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.kmac_entropy_refresh.12875120820784084695865293542742735428327958577573021100220148624189745024914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.91008848041460387750032453559133631443904462288747305513248671968075752769110
Short name T864
Test name
Test status
Simulation time 8615085608 ps
CPU time 128.66 seconds
Started Nov 22 01:52:31 PM PST 23
Finished Nov 22 01:54:43 PM PST 23
Peak memory 248592 kb
Host smart-fd02c07e-9b12-4717-ab0e-a9021434d23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91008848041460387750032453559133631443904462288747305513248671968075752769110 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.kmac_error.91008848041460387750032453559133631443904462288747305513248671968075752769110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.87788186950194523062716220311923156129417726161160763672334315527137151028099
Short name T60
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.65 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:52:58 PM PST 23
Peak memory 207652 kb
Host smart-5d483beb-55a0-48f8-8427-ff87314548f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87788186950194523062716220311923156129417726161160763672334315527137151028099 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.kmac_key_error.87788186950194523062716220311923156129417726161160763672334315527137151028099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.70663152678486253078981169168120099079340261176108866759396530294694563685634
Short name T228
Test name
Test status
Simulation time 58171921 ps
CPU time 1.27 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 215756 kb
Host smart-49e2032b-25d7-4e6b-a584-301c657673d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70663152678486253078981169168120099079340261176108866759396530294694563685634 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.kmac_lc_escalation.70663152678486253078981169168120099079340261176108866759396530294694563685634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.34128192643935859388725381525095189363370156790341735200536313662859462268436
Short name T929
Test name
Test status
Simulation time 45517522529 ps
CPU time 697.61 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 02:04:30 PM PST 23
Peak memory 288324 kb
Host smart-322f8e4d-3146-4795-9edd-22497bdd669d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128192643935859388725381525095189363370156790341735200536313662859462268436 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3412819264393585938872538152509518936337015679034173520053631366285946
2268436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.41963211757115956497247629911578408625026517911545463359680445834804784745419
Short name T80
Test name
Test status
Simulation time 5640716546 ps
CPU time 76.5 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 227144 kb
Host smart-017b8fb8-dcf4-4360-a8d9-5aeb0bbf62ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41963211757115956497247629911578408625026517911545463359680445834804784745419 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.kmac_mubi.41963211757115956497247629911578408625026517911545463359680445834804784745419 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.103968079149337429851155896090420626922496191572877579258640351114376775542088
Short name T28
Test name
Test status
Simulation time 4127675079 ps
CPU time 32.63 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:53:21 PM PST 23
Peak memory 248912 kb
Host smart-a76e309a-0b68-4b8f-9b07-80c8a1d32e02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103968079149337429851155896090420626922496191572877579258640351114376775542088 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.kmac_sec_cm.103968079149337429851155896090420626922496191572877579258640351114376775542088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.99695805949414408168274344065018725655284262997656304815106124177544735647298
Short name T307
Test name
Test status
Simulation time 7733092664 ps
CPU time 114.31 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:54:43 PM PST 23
Peak memory 228088 kb
Host smart-692a2f07-960f-4ba2-ab19-898c736693d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99695805949414408168274344065018725655284262997656304815106124177544735647298 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.kmac_sideload.99695805949414408168274344065018725655284262997656304815106124177544735647298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.24844310845399309323082599690825631425460460527403037692956886373909804097791
Short name T521
Test name
Test status
Simulation time 1554463522 ps
CPU time 19.54 seconds
Started Nov 22 01:52:38 PM PST 23
Finished Nov 22 01:53:04 PM PST 23
Peak memory 215844 kb
Host smart-1c3625bd-974c-4036-968a-990bf608c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24844310845399309323082599690825631425460460527403037692956886373909804097791 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.kmac_smoke.24844310845399309323082599690825631425460460527403037692956886373909804097791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.77143788452315020691449322208568856232299931105880476901897671536607815431271
Short name T45
Test name
Test status
Simulation time 41434001626 ps
CPU time 615.58 seconds
Started Nov 22 01:52:37 PM PST 23
Finished Nov 22 02:03:00 PM PST 23
Peak memory 321648 kb
Host smart-c565433e-5d0b-4f1a-ad2c-79131c5f5cb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=77143788452315020691449322208568856232299931105880476901897671536607815431271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_str
ess_all.77143788452315020691449322208568856232299931105880476901897671536607815431271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.32580500160128612268872482961475837916810028952289435202268412954870919637990
Short name T890
Test name
Test status
Simulation time 298812853 ps
CPU time 4.4 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:52:51 PM PST 23
Peak memory 215680 kb
Host smart-f24f32b3-6e42-4029-ace8-5bd19a3f9a12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32580500160128612268872482961475837916810028952289435
202268412954870919637990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.325805001601286122688724829614758379168
10028952289435202268412954870919637990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.47710772900609585670928631796775644968638240776602632326944737533590538768924
Short name T30
Test name
Test status
Simulation time 289902210 ps
CPU time 4.09 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 01:52:41 PM PST 23
Peak memory 215840 kb
Host smart-48594b32-abc9-42a5-89ce-0fd30d8d6264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47710772900609585670928631796775644968638240776602632
326944737533590538768924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4771077290060958567092863179677
5644968638240776602632326944737533590538768924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.79423830597235670540239412418219535904384010803216888672023788401171176308690
Short name T946
Test name
Test status
Simulation time 115269125226 ps
CPU time 1665.68 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 02:20:39 PM PST 23
Peak memory 390312 kb
Host smart-8a2d179b-b092-4497-ba2e-6ce459917423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=79423830597235670540239412418219535904384010803216888672023788401171176308690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_224.79423830597235670540239412418219535904384010803216888672023788401171176308690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.53408690398951276456851006464338862029504490975813760547237358363894917352472
Short name T780
Test name
Test status
Simulation time 107886220004 ps
CPU time 1644.19 seconds
Started Nov 22 01:52:27 PM PST 23
Finished Nov 22 02:19:58 PM PST 23
Peak memory 370180 kb
Host smart-bc0eb11d-81ed-4ee8-a5db-fd63aff1c00c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=53408690398951276456851006464338862029504490975813760547237358363894917352472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_256.53408690398951276456851006464338862029504490975813760547237358363894917352472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.25482178014483765582050312180060378241851065720238793838309733188503902443799
Short name T269
Test name
Test status
Simulation time 83070954242 ps
CPU time 1323.82 seconds
Started Nov 22 01:52:37 PM PST 23
Finished Nov 22 02:14:48 PM PST 23
Peak memory 332904 kb
Host smart-bc47fffb-4aba-4916-8ef3-2fcff15d6eda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25482178014483765582050312180060378241851065720238793838309733188503902443799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_384.25482178014483765582050312180060378241851065720238793838309733188503902443799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.52305862621178994989103112706708338698237290146002772897045858718512352028763
Short name T635
Test name
Test status
Simulation time 58503507926 ps
CPU time 898.34 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 02:07:51 PM PST 23
Peak memory 295880 kb
Host smart-d696b5e3-ffd0-49b3-8505-e2ea3e15c791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=52305862621178994989103112706708338698237290146002772897045858718512352028763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
kmac_test_vectors_sha3_512.52305862621178994989103112706708338698237290146002772897045858718512352028763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.38085874253939795062175916712724131237002346933903377151174397453703815863957
Short name T377
Test name
Test status
Simulation time 307766781661 ps
CPU time 4482.94 seconds
Started Nov 22 01:52:34 PM PST 23
Finished Nov 22 03:07:22 PM PST 23
Peak memory 653260 kb
Host smart-830bd6fc-d4ea-4f1c-8415-5dfaefecaf18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=38085874253939795062175916712724131237002346933903377151174397453703815863957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.kmac_test_vectors_shake_128.38085874253939795062175916712724131237002346933903377151174397453703815863957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.12969442211899660667699865356362374961933091779503770625722743013743294502332
Short name T532
Test name
Test status
Simulation time 258047411562 ps
CPU time 3612.37 seconds
Started Nov 22 01:52:51 PM PST 23
Finished Nov 22 02:53:06 PM PST 23
Peak memory 556344 kb
Host smart-71144eeb-1243-4f7b-b1f5-41438d989e57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=12969442211899660667699865356362374961933091779503770625722743013743294502332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.kmac_test_vectors_shake_256.12969442211899660667699865356362374961933091779503770625722743013743294502332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.78812720695529042406576380623888713250533840163424426390760692309851112849731
Short name T233
Test name
Test status
Simulation time 21118646 ps
CPU time 0.78 seconds
Started Nov 22 01:54:01 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 205248 kb
Host smart-e6db3245-5341-4626-a123-c33500cdb9f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78812720695529042406576380623888713250533840163424426390760692309851112849731 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.kmac_alert_test.78812720695529042406576380623888713250533840163424426390760692309851112849731 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.105125164129267648112141071536073417389383257686430179002730582780239560828959
Short name T214
Test name
Test status
Simulation time 5659537824 ps
CPU time 78.75 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 01:55:17 PM PST 23
Peak memory 227364 kb
Host smart-0daa683e-82f1-4a41-80a8-50a5cfdc1fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105125164129267648112141071536073417389383257686430179002730582780239560828959 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.kmac_app.105125164129267648112141071536073417389383257686430179002730582780239560828959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.17282803111031652302845996751823307392275694186610312286596281689988195492078
Short name T1076
Test name
Test status
Simulation time 14812750312 ps
CPU time 237.77 seconds
Started Nov 22 01:53:37 PM PST 23
Finished Nov 22 01:57:36 PM PST 23
Peak memory 225524 kb
Host smart-ccc1edee-f132-4064-8558-3d92f59c98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17282803111031652302845996751823307392275694186610312286596281689988195492078 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.kmac_burst_write.17282803111031652302845996751823307392275694186610312286596281689988195492078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.54024797048830754109582765828688558335650718694648746469951882654909674617505
Short name T582
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.63 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 01:55:00 PM PST 23
Peak memory 226988 kb
Host smart-b0f454db-eedd-4444-ab23-a9f93b6ac54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54024797048830754109582765828688558335650718694648746469951882654909674617505 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.kmac_entropy_refresh.54024797048830754109582765828688558335650718694648746469951882654909674617505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.63381953162531171784212274031966712577679565631591126726072735471480120057366
Short name T249
Test name
Test status
Simulation time 8615085608 ps
CPU time 136.63 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 01:56:00 PM PST 23
Peak memory 248656 kb
Host smart-f8c38625-bb67-4309-8693-fc280f2045c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63381953162531171784212274031966712577679565631591126726072735471480120057366 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.kmac_error.63381953162531171784212274031966712577679565631591126726072735471480120057366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.79367793316807291300740961235391129548576986741697684528402336738109295726658
Short name T444
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.12 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:54:01 PM PST 23
Peak memory 207504 kb
Host smart-7f038064-a136-46e8-a23c-6275a8461e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79367793316807291300740961235391129548576986741697684528402336738109295726658 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.kmac_key_error.79367793316807291300740961235391129548576986741697684528402336738109295726658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.28296955660142247888398602179748572973162958529616562629999575875235415447466
Short name T936
Test name
Test status
Simulation time 58171921 ps
CPU time 1.2 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:53:49 PM PST 23
Peak memory 215792 kb
Host smart-46fcd4bc-8b1e-45b4-b727-d80c76d9a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28296955660142247888398602179748572973162958529616562629999575875235415447466 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.kmac_lc_escalation.28296955660142247888398602179748572973162958529616562629999575875235415447466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.29332797802579579507009675699581636645138991199724762161389499896696180611558
Short name T762
Test name
Test status
Simulation time 45517522529 ps
CPU time 692.26 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:05:20 PM PST 23
Peak memory 288404 kb
Host smart-8d01af6a-c54f-457d-8188-5a6cfefe2d79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29332797802579579507009675699581636645138991199724762161389499896696180611558 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.293327978025795795070096756995816366451389911997247621613894998966961
80611558 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.114488526666601195468923438823057688824434856406131612176432576087367763123169
Short name T492
Test name
Test status
Simulation time 7733092664 ps
CPU time 109.22 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:55:46 PM PST 23
Peak memory 228056 kb
Host smart-78ed08e2-905c-4067-a037-f2d38e61db2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114488526666601195468923438823057688824434856406131612176432576087367763123169 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.kmac_sideload.114488526666601195468923438823057688824434856406131612176432576087367763123169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.104575913649917160039439909946731843306448871729386379412200180971151956702823
Short name T398
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.67 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:54:07 PM PST 23
Peak memory 215964 kb
Host smart-e633cdd7-44fa-4637-b9d6-70c0d81b128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104575913649917160039439909946731843306448871729386379412200180971151956702823 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 30.kmac_smoke.104575913649917160039439909946731843306448871729386379412200180971151956702823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.98868795795655806745397971638827715272679318385801983100175077367348157281607
Short name T292
Test name
Test status
Simulation time 41434001626 ps
CPU time 609.99 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 02:04:08 PM PST 23
Peak memory 321608 kb
Host smart-e108c3a6-7da4-48f5-9cc8-ac8b6599bff5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=98868795795655806745397971638827715272679318385801983100175077367348157281607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_st
ress_all.98868795795655806745397971638827715272679318385801983100175077367348157281607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.35329241129543925398494059827506488418525501002268311958035936599365108854456
Short name T938
Test name
Test status
Simulation time 298812853 ps
CPU time 4.24 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 01:53:59 PM PST 23
Peak memory 215692 kb
Host smart-8e8efd87-b98c-4a51-a984-7a23d93c27ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35329241129543925398494059827506488418525501002268311
958035936599365108854456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac.35329241129543925398494059827506488418
525501002268311958035936599365108854456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2430387038596531442154402379909718263231179373390640159848823988837874851291
Short name T426
Test name
Test status
Simulation time 289902210 ps
CPU time 4.23 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 01:53:53 PM PST 23
Peak memory 215868 kb
Host smart-f5ccdaff-d49d-4064-9fa3-f167cdc9c233
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303870385965314421544023799097182632311793733906401
59848823988837874851291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2430387038596531442154402379909
718263231179373390640159848823988837874851291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.77939377194153537710978931218122075282108599614074058523828000005941792308395
Short name T508
Test name
Test status
Simulation time 115269125226 ps
CPU time 1803.35 seconds
Started Nov 22 01:53:41 PM PST 23
Finished Nov 22 02:23:46 PM PST 23
Peak memory 390548 kb
Host smart-72361e6f-96df-493a-b6bc-a9443b0c4d97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77939377194153537710978931218122075282108599614074058523828000005941792308395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.kmac_test_vectors_sha3_224.77939377194153537710978931218122075282108599614074058523828000005941792308395 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.82994411154136389739535691269847302160808059588835208818440022464469176864903
Short name T1001
Test name
Test status
Simulation time 107886220004 ps
CPU time 1578.57 seconds
Started Nov 22 01:53:52 PM PST 23
Finished Nov 22 02:20:12 PM PST 23
Peak memory 369972 kb
Host smart-74b22365-553f-4ff3-9392-51019904efce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=82994411154136389739535691269847302160808059588835208818440022464469176864903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.kmac_test_vectors_sha3_256.82994411154136389739535691269847302160808059588835208818440022464469176864903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.43327035831121810483952768284970031899072588036904446301987945835199361316123
Short name T217
Test name
Test status
Simulation time 83070954242 ps
CPU time 1271.65 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 02:15:15 PM PST 23
Peak memory 332916 kb
Host smart-266baae1-1b22-4ad6-bc7b-7db8fedae45b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=43327035831121810483952768284970031899072588036904446301987945835199361316123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.kmac_test_vectors_sha3_384.43327035831121810483952768284970031899072588036904446301987945835199361316123 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.57111137853307437186501678854390133879236590474421301053161732130046690817857
Short name T576
Test name
Test status
Simulation time 58503507926 ps
CPU time 883.33 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:08:31 PM PST 23
Peak memory 295908 kb
Host smart-88573366-2d25-4f89-a3df-d9b0ee89ce49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57111137853307437186501678854390133879236590474421301053161732130046690817857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.kmac_test_vectors_sha3_512.57111137853307437186501678854390133879236590474421301053161732130046690817857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.50407099082316158051411799707727678865181848528793961901551159096115740998517
Short name T889
Test name
Test status
Simulation time 307766781661 ps
CPU time 4531.97 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 03:09:24 PM PST 23
Peak memory 653220 kb
Host smart-38dfa3ab-12ed-45b5-a1f5-91d45e46668e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=50407099082316158051411799707727678865181848528793961901551159096115740998517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.kmac_test_vectors_shake_128.50407099082316158051411799707727678865181848528793961901551159096115740998517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.97965330444350867052618494533503754940988122753736165194208486861090066035544
Short name T506
Test name
Test status
Simulation time 258047411562 ps
CPU time 3718.37 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 02:55:48 PM PST 23
Peak memory 556280 kb
Host smart-daa73d2f-5f8f-4fcf-a3da-16499d306178
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=97965330444350867052618494533503754940988122753736165194208486861090066035544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.kmac_test_vectors_shake_256.97965330444350867052618494533503754940988122753736165194208486861090066035544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.85690180041046161357108061357112997295432502039624890011127489126206228684681
Short name T386
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 01:54:04 PM PST 23
Peak memory 205252 kb
Host smart-a2408286-f113-4994-a2ec-69833b64683b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85690180041046161357108061357112997295432502039624890011127489126206228684681 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.kmac_alert_test.85690180041046161357108061357112997295432502039624890011127489126206228684681 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.113107135671738513966342824684725543728676345650832741236155882306025135615820
Short name T163
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.13 seconds
Started Nov 22 01:53:44 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 227372 kb
Host smart-633d4782-5da7-4131-9805-4ea6fd61ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113107135671738513966342824684725543728676345650832741236155882306025135615820 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.kmac_app.113107135671738513966342824684725543728676345650832741236155882306025135615820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.51939480270569610425413411021111362367410393176774412699442377834620406617307
Short name T1009
Test name
Test status
Simulation time 14812750312 ps
CPU time 252.62 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:58:08 PM PST 23
Peak memory 225560 kb
Host smart-04469233-a6da-4d6a-a4f8-fdc8eca35aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51939480270569610425413411021111362367410393176774412699442377834620406617307 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.kmac_burst_write.51939480270569610425413411021111362367410393176774412699442377834620406617307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.51039575817872958996788179613658832408521737893799370373844812315585241369620
Short name T650
Test name
Test status
Simulation time 6743332725 ps
CPU time 71.41 seconds
Started Nov 22 01:53:39 PM PST 23
Finished Nov 22 01:54:52 PM PST 23
Peak memory 227020 kb
Host smart-f563ac38-8505-4851-ad25-0334e7259ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51039575817872958996788179613658832408521737893799370373844812315585241369620 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.kmac_entropy_refresh.51039575817872958996788179613658832408521737893799370373844812315585241369620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.8869948480930964146344833666773547570611614309821463068526242512859851357723
Short name T849
Test name
Test status
Simulation time 8615085608 ps
CPU time 128.45 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 01:56:06 PM PST 23
Peak memory 248536 kb
Host smart-439523af-b0f6-488e-84c7-c44994c0a4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8869948480930964146344833666773547570611614309821463068526242512859851357723 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.kmac_error.8869948480930964146344833666773547570611614309821463068526242512859851357723 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.45473438424307626048896692195410526128510130343191686319738534537288532687789
Short name T848
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.36 seconds
Started Nov 22 01:53:44 PM PST 23
Finished Nov 22 01:53:51 PM PST 23
Peak memory 207548 kb
Host smart-f819bf12-3297-446e-b205-261cc185d6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45473438424307626048896692195410526128510130343191686319738534537288532687789 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.kmac_key_error.45473438424307626048896692195410526128510130343191686319738534537288532687789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.57852750405672773211797259299020443870288738354825000098451302750536190064053
Short name T975
Test name
Test status
Simulation time 58171921 ps
CPU time 1.19 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 01:53:53 PM PST 23
Peak memory 215692 kb
Host smart-a19f64c4-4283-44fa-9838-242ec3bcb8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57852750405672773211797259299020443870288738354825000098451302750536190064053 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.kmac_lc_escalation.57852750405672773211797259299020443870288738354825000098451302750536190064053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.51581704623850701736878651110380538488576488109018602978410698442799949149389
Short name T875
Test name
Test status
Simulation time 45517522529 ps
CPU time 712.25 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 02:05:53 PM PST 23
Peak memory 288304 kb
Host smart-841316ad-e306-4a0b-89ca-6212d6f0e7aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51581704623850701736878651110380538488576488109018602978410698442799949149389 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.515817046238507017368786511103805384885764881090186029784106984427999
49149389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.68891462292547644408642560155524297787122668576214492768989751694877245283240
Short name T930
Test name
Test status
Simulation time 7733092664 ps
CPU time 111.34 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:55:48 PM PST 23
Peak memory 228172 kb
Host smart-e5bc113d-ab1c-40a0-9d59-61c23f5ea772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68891462292547644408642560155524297787122668576214492768989751694877245283240 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.kmac_sideload.68891462292547644408642560155524297787122668576214492768989751694877245283240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.93300099411289053706075489843885781136521678820377253788445862342703882588181
Short name T868
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.39 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 01:54:25 PM PST 23
Peak memory 215952 kb
Host smart-324d0f27-9c51-4bd7-9a19-49d883120561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93300099411289053706075489843885781136521678820377253788445862342703882588181 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.kmac_smoke.93300099411289053706075489843885781136521678820377253788445862342703882588181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.73909493402147974007833029504049661556845758054495380603386553825435617224640
Short name T40
Test name
Test status
Simulation time 41434001626 ps
CPU time 605.51 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 02:03:56 PM PST 23
Peak memory 321752 kb
Host smart-3efe76ef-df5b-4754-afd5-f3b7ce7ae005
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=73909493402147974007833029504049661556845758054495380603386553825435617224640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_st
ress_all.73909493402147974007833029504049661556845758054495380603386553825435617224640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.79499285010593320148507828017210452722652300043819487079861850286252520511271
Short name T577
Test name
Test status
Simulation time 298812853 ps
CPU time 4.14 seconds
Started Nov 22 01:53:44 PM PST 23
Finished Nov 22 01:53:49 PM PST 23
Peak memory 215848 kb
Host smart-795e03da-f77a-4f8e-9907-e71f0870549a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79499285010593320148507828017210452722652300043819487
079861850286252520511271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac.79499285010593320148507828017210452722
652300043819487079861850286252520511271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.13160322752465936267381531016378726667658380135351667405186506041728786343865
Short name T195
Test name
Test status
Simulation time 289902210 ps
CPU time 4.15 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:54:13 PM PST 23
Peak memory 215760 kb
Host smart-d6b5c435-470f-42dc-aa27-bb17bd23eff2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13160322752465936267381531016378726667658380135351667
405186506041728786343865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.131603227524659362673815310163
78726667658380135351667405186506041728786343865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.13074683106074647989595438508672874712251997380150649432784938375756782314534
Short name T965
Test name
Test status
Simulation time 115269125226 ps
CPU time 1609.1 seconds
Started Nov 22 01:53:43 PM PST 23
Finished Nov 22 02:20:33 PM PST 23
Peak memory 390328 kb
Host smart-f6e09522-1c77-4ffe-8517-1a59b06b6061
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=13074683106074647989595438508672874712251997380150649432784938375756782314534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.kmac_test_vectors_sha3_224.13074683106074647989595438508672874712251997380150649432784938375756782314534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.11192607459203838181674940452296649474279827462922225398837890898340437742917
Short name T756
Test name
Test status
Simulation time 107886220004 ps
CPU time 1592.86 seconds
Started Nov 22 01:53:47 PM PST 23
Finished Nov 22 02:20:22 PM PST 23
Peak memory 370136 kb
Host smart-2564be13-5bba-40f6-ab23-53e96ba0b0fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11192607459203838181674940452296649474279827462922225398837890898340437742917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.kmac_test_vectors_sha3_256.11192607459203838181674940452296649474279827462922225398837890898340437742917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.76573070695060145026774474932211454862696771852370987451530545064543220690108
Short name T359
Test name
Test status
Simulation time 83070954242 ps
CPU time 1241.25 seconds
Started Nov 22 01:53:48 PM PST 23
Finished Nov 22 02:14:31 PM PST 23
Peak memory 332956 kb
Host smart-7b86d088-1e68-4e74-ad1f-fc45aad1aef8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=76573070695060145026774474932211454862696771852370987451530545064543220690108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.kmac_test_vectors_sha3_384.76573070695060145026774474932211454862696771852370987451530545064543220690108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.90500809968399107418394115958172084849818085605239511061849223489495565855750
Short name T423
Test name
Test status
Simulation time 58503507926 ps
CPU time 850.94 seconds
Started Nov 22 01:53:52 PM PST 23
Finished Nov 22 02:08:05 PM PST 23
Peak memory 295916 kb
Host smart-9fed0d3a-03fa-431e-8c18-0d6e69e8053b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90500809968399107418394115958172084849818085605239511061849223489495565855750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.kmac_test_vectors_sha3_512.90500809968399107418394115958172084849818085605239511061849223489495565855750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.31299335694023160633634108866591320423408610809963604150289475000963597283876
Short name T143
Test name
Test status
Simulation time 307766781661 ps
CPU time 4578.38 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 03:10:18 PM PST 23
Peak memory 653204 kb
Host smart-c692cfbe-68eb-4466-b24c-8fa248e860fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=31299335694023160633634108866591320423408610809963604150289475000963597283876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.kmac_test_vectors_shake_128.31299335694023160633634108866591320423408610809963604150289475000963597283876 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.57376408169283673987074645111539881309296811291099816626990253966946093853244
Short name T655
Test name
Test status
Simulation time 258047411562 ps
CPU time 3714.8 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 02:55:42 PM PST 23
Peak memory 556272 kb
Host smart-ffdce284-d4fb-43fa-b002-cdca5aff0c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=57376408169283673987074645111539881309296811291099816626990253966946093853244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.kmac_test_vectors_shake_256.57376408169283673987074645111539881309296811291099816626990253966946093853244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.26717514017683507329230042804920569537495336881595505732708821264194178163500
Short name T1053
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 01:53:55 PM PST 23
Peak memory 205268 kb
Host smart-d51c09e1-d29f-4d38-9edb-e0bb212aa44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26717514017683507329230042804920569537495336881595505732708821264194178163500 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.kmac_alert_test.26717514017683507329230042804920569537495336881595505732708821264194178163500 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.6530546330978156295047102154249191811450884922135347727373809928567165941470
Short name T458
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.82 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:55:12 PM PST 23
Peak memory 227348 kb
Host smart-57c8032f-91e6-4a62-9d42-ed1a0e2e1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6530546330978156295047102154249191811450884922135347727373809928567165941470 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.kmac_app.6530546330978156295047102154249191811450884922135347727373809928567165941470 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.78747135050446257713225399422864306579444686116768722524118819823534105359973
Short name T704
Test name
Test status
Simulation time 14812750312 ps
CPU time 246.58 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:58:20 PM PST 23
Peak memory 224872 kb
Host smart-748d4901-62fb-4d18-a327-4e33cc956126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78747135050446257713225399422864306579444686116768722524118819823534105359973 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.kmac_burst_write.78747135050446257713225399422864306579444686116768722524118819823534105359973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.71337051770304989982820101416877514036554838345643732146113606375572871692816
Short name T637
Test name
Test status
Simulation time 6743332725 ps
CPU time 71 seconds
Started Nov 22 01:53:57 PM PST 23
Finished Nov 22 01:55:09 PM PST 23
Peak memory 226968 kb
Host smart-12be6659-15c8-4fa5-9d3d-51951b75aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71337051770304989982820101416877514036554838345643732146113606375572871692816 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.kmac_entropy_refresh.71337051770304989982820101416877514036554838345643732146113606375572871692816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.23341218519582016326868092859796515709197801531805256300178040592713806068204
Short name T683
Test name
Test status
Simulation time 8615085608 ps
CPU time 132.1 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:56:24 PM PST 23
Peak memory 248520 kb
Host smart-770f74e7-c77e-436a-b607-27f2448007d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23341218519582016326868092859796515709197801531805256300178040592713806068204 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.kmac_error.23341218519582016326868092859796515709197801531805256300178040592713806068204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.21487714639399964427369599838814606623040473783726256331201287437756417802726
Short name T955
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.2 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:54:18 PM PST 23
Peak memory 207480 kb
Host smart-518d9167-431d-4ebe-a58c-59ebd41c595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21487714639399964427369599838814606623040473783726256331201287437756417802726 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.kmac_key_error.21487714639399964427369599838814606623040473783726256331201287437756417802726 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.22211946032612672943825895837115095766774066507271122142982673698238798271518
Short name T1026
Test name
Test status
Simulation time 58171921 ps
CPU time 1.28 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 01:54:12 PM PST 23
Peak memory 215668 kb
Host smart-d396a19b-f7c8-4c9a-a945-ac9deb97eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22211946032612672943825895837115095766774066507271122142982673698238798271518 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.kmac_lc_escalation.22211946032612672943825895837115095766774066507271122142982673698238798271518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.26810470157670686727766386077318510866356271836021442354822009194076978646817
Short name T1062
Test name
Test status
Simulation time 45517522529 ps
CPU time 715.23 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 02:05:45 PM PST 23
Peak memory 288372 kb
Host smart-2a4b629d-8635-49e3-8467-a468d610371c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26810470157670686727766386077318510866356271836021442354822009194076978646817 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.268104701576706867277663860773185108663562718360214423548220091940769
78646817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.61165639988534752211879840937310547760407590325919305475219827600037798644741
Short name T709
Test name
Test status
Simulation time 7733092664 ps
CPU time 106.02 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 01:55:37 PM PST 23
Peak memory 228116 kb
Host smart-c9f260d9-b6ff-4fa2-b9ca-8a7590265597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61165639988534752211879840937310547760407590325919305475219827600037798644741 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.kmac_sideload.61165639988534752211879840937310547760407590325919305475219827600037798644741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.103443451213683759676236700460299204160714434373733205856702639107933889169932
Short name T425
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.22 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 01:54:18 PM PST 23
Peak memory 215960 kb
Host smart-0330f452-6d06-4e5a-b539-f5c7588a795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103443451213683759676236700460299204160714434373733205856702639107933889169932 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.kmac_smoke.103443451213683759676236700460299204160714434373733205856702639107933889169932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.38424308946482934441802784575661964015905489761104405463648203839244832369593
Short name T518
Test name
Test status
Simulation time 41434001626 ps
CPU time 628.84 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 02:04:43 PM PST 23
Peak memory 321600 kb
Host smart-3f797bf5-d88a-4510-8ad6-3bab03e8eeaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=38424308946482934441802784575661964015905489761104405463648203839244832369593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_st
ress_all.38424308946482934441802784575661964015905489761104405463648203839244832369593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.70409663967165200876928023442127404774391736070338905115186130720781673886136
Short name T182
Test name
Test status
Simulation time 298812853 ps
CPU time 4.35 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 01:54:01 PM PST 23
Peak memory 215800 kb
Host smart-6f31be52-acb5-4402-a64b-2fcac6f7f759
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70409663967165200876928023442127404774391736070338905
115186130720781673886136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac.70409663967165200876928023442127404774
391736070338905115186130720781673886136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.13497582282096214309539990218952727368931956260823854020183349035955725227973
Short name T260
Test name
Test status
Simulation time 289902210 ps
CPU time 4.18 seconds
Started Nov 22 01:54:25 PM PST 23
Finished Nov 22 01:54:32 PM PST 23
Peak memory 215804 kb
Host smart-84fe0b57-664f-4c4c-88aa-7148264e982e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13497582282096214309539990218952727368931956260823854
020183349035955725227973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.134975822820962143095399902189
52727368931956260823854020183349035955725227973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.65640701438449616040650062149619865278357338139080862282121879555656763816625
Short name T218
Test name
Test status
Simulation time 115269125226 ps
CPU time 1702.22 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 02:22:22 PM PST 23
Peak memory 390328 kb
Host smart-94404634-90d7-4d22-853e-a35c268d28fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=65640701438449616040650062149619865278357338139080862282121879555656763816625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_224.65640701438449616040650062149619865278357338139080862282121879555656763816625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.93041327212347381340650746920500561282096678449885903832207503211952262170574
Short name T832
Test name
Test status
Simulation time 107886220004 ps
CPU time 1640.73 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 02:21:37 PM PST 23
Peak memory 370156 kb
Host smart-88facb95-bf41-4218-aa44-31ded6842868
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=93041327212347381340650746920500561282096678449885903832207503211952262170574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_256.93041327212347381340650746920500561282096678449885903832207503211952262170574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.88183820240053622622673903775794237642051963479418982800811824082317557131604
Short name T33
Test name
Test status
Simulation time 83070954242 ps
CPU time 1273.59 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 02:15:19 PM PST 23
Peak memory 332660 kb
Host smart-d3d8d8fb-4388-4237-b3ec-1fe21b11cd85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=88183820240053622622673903775794237642051963479418982800811824082317557131604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_384.88183820240053622622673903775794237642051963479418982800811824082317557131604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.77261844176897745149366876042180700563185397673964851741959165767871160058050
Short name T139
Test name
Test status
Simulation time 58503507926 ps
CPU time 876.19 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 02:08:39 PM PST 23
Peak memory 295852 kb
Host smart-e74a17f0-11ac-4bd6-88bf-4a060f73ec98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77261844176897745149366876042180700563185397673964851741959165767871160058050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.kmac_test_vectors_sha3_512.77261844176897745149366876042180700563185397673964851741959165767871160058050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.70298597289709965812555622895480844280453866204275686435021167370179440319578
Short name T923
Test name
Test status
Simulation time 307766781661 ps
CPU time 4570.99 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 03:10:24 PM PST 23
Peak memory 653164 kb
Host smart-621583f2-6221-4082-9454-192c6eda8452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=70298597289709965812555622895480844280453866204275686435021167370179440319578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.kmac_test_vectors_shake_128.70298597289709965812555622895480844280453866204275686435021167370179440319578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.5634114795986535917655322670530798413834534342709245661272872429847511760585
Short name T894
Test name
Test status
Simulation time 258047411562 ps
CPU time 3621.29 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 02:54:29 PM PST 23
Peak memory 556232 kb
Host smart-5646ad4b-2e3f-4efa-ae6c-7b173366b0a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=5634114795986535917655322670530798413834534342709245661272872429847511760585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.kmac_test_vectors_shake_256.5634114795986535917655322670530798413834534342709245661272872429847511760585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.54321277354842584293298782544509853383140129571301304727567348359188094926660
Short name T461
Test name
Test status
Simulation time 21118646 ps
CPU time 0.72 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 01:53:47 PM PST 23
Peak memory 205268 kb
Host smart-95a121eb-4253-4674-926f-96357576ad00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54321277354842584293298782544509853383140129571301304727567348359188094926660 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.kmac_alert_test.54321277354842584293298782544509853383140129571301304727567348359188094926660 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.109895294718596817052650097589539530824689511706965663131500512159380716164765
Short name T341
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.81 seconds
Started Nov 22 01:54:25 PM PST 23
Finished Nov 22 01:55:46 PM PST 23
Peak memory 227344 kb
Host smart-96039a07-7a9f-4103-ab44-7f76fec9a36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109895294718596817052650097589539530824689511706965663131500512159380716164765 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.kmac_app.109895294718596817052650097589539530824689511706965663131500512159380716164765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.67441376363280762675772930573005158976305630919585701139549708539972344875588
Short name T920
Test name
Test status
Simulation time 14812750312 ps
CPU time 235.01 seconds
Started Nov 22 01:54:17 PM PST 23
Finished Nov 22 01:58:13 PM PST 23
Peak memory 225484 kb
Host smart-adfc1d68-dcaa-4d26-8b68-f30ff0d306c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67441376363280762675772930573005158976305630919585701139549708539972344875588 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.kmac_burst_write.67441376363280762675772930573005158976305630919585701139549708539972344875588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.86023599138645446201017679889983961398959679356445705583148799727077866175384
Short name T908
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.55 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 01:55:23 PM PST 23
Peak memory 227056 kb
Host smart-b7d10f12-06bb-4434-9cd6-1cc5edb23feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86023599138645446201017679889983961398959679356445705583148799727077866175384 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.kmac_entropy_refresh.86023599138645446201017679889983961398959679356445705583148799727077866175384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.22117826287940334884290577264254042373421530471845803179211185696764329221280
Short name T1002
Test name
Test status
Simulation time 8615085608 ps
CPU time 132.37 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 01:56:04 PM PST 23
Peak memory 248636 kb
Host smart-ede4f574-d29e-4c37-acd2-7cabbb91cf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22117826287940334884290577264254042373421530471845803179211185696764329221280 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.kmac_error.22117826287940334884290577264254042373421530471845803179211185696764329221280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.50550705831789507294877850697261227498071164908767164447631112508541275549646
Short name T393
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.25 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 01:53:58 PM PST 23
Peak memory 207540 kb
Host smart-5b7737f8-de4f-483a-a1c3-5a50a6d4281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50550705831789507294877850697261227498071164908767164447631112508541275549646 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.kmac_key_error.50550705831789507294877850697261227498071164908767164447631112508541275549646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.91117162807046775558876915124197664128549008414413051524144753346846328101686
Short name T263
Test name
Test status
Simulation time 58171921 ps
CPU time 1.25 seconds
Started Nov 22 01:54:07 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 215680 kb
Host smart-bb78f5cb-8655-4926-aa94-2562afec7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91117162807046775558876915124197664128549008414413051524144753346846328101686 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.kmac_lc_escalation.91117162807046775558876915124197664128549008414413051524144753346846328101686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.53358033578880303007975687626988367877141051055716406423144452843466100492788
Short name T1004
Test name
Test status
Simulation time 45517522529 ps
CPU time 713.9 seconds
Started Nov 22 01:54:09 PM PST 23
Finished Nov 22 02:06:04 PM PST 23
Peak memory 288344 kb
Host smart-46ea904d-6ca5-476d-8363-4d2b060a5a22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53358033578880303007975687626988367877141051055716406423144452843466100492788 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.533580335788803030079756876269883678771410510557164064231444528434661
00492788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.36442600979854449963085744861554103832310052474567543728402517888368031657957
Short name T378
Test name
Test status
Simulation time 7733092664 ps
CPU time 109.59 seconds
Started Nov 22 01:54:20 PM PST 23
Finished Nov 22 01:56:14 PM PST 23
Peak memory 228048 kb
Host smart-1b9a672a-e7e6-42f4-a004-867101d1f964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36442600979854449963085744861554103832310052474567543728402517888368031657957 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.kmac_sideload.36442600979854449963085744861554103832310052474567543728402517888368031657957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.64732845217654888101494982686529923774247310234099821181783094576759532565981
Short name T144
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.17 seconds
Started Nov 22 01:54:09 PM PST 23
Finished Nov 22 01:54:28 PM PST 23
Peak memory 215960 kb
Host smart-a04eb614-af4f-4869-82e1-cf64f16457d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64732845217654888101494982686529923774247310234099821181783094576759532565981 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.kmac_smoke.64732845217654888101494982686529923774247310234099821181783094576759532565981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.110623343307500744357108303264003297196400177867056377732398699333211470971566
Short name T597
Test name
Test status
Simulation time 41434001626 ps
CPU time 599.94 seconds
Started Nov 22 01:53:44 PM PST 23
Finished Nov 22 02:03:46 PM PST 23
Peak memory 321760 kb
Host smart-15f1df2b-e265-4a39-962d-bd467bd22921
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=110623343307500744357108303264003297196400177867056377732398699333211470971566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_s
tress_all.110623343307500744357108303264003297196400177867056377732398699333211470971566 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.75067318747256482954807232344162834140096415584488095407545524203008192016209
Short name T474
Test name
Test status
Simulation time 298812853 ps
CPU time 4.75 seconds
Started Nov 22 01:54:03 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 215848 kb
Host smart-150b7615-4764-4e43-b513-96a285abe3ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75067318747256482954807232344162834140096415584488095
407545524203008192016209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac.75067318747256482954807232344162834140
096415584488095407545524203008192016209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.67843979608395743237188132897938732016396205660626643505928815607915277686969
Short name T537
Test name
Test status
Simulation time 289902210 ps
CPU time 4.16 seconds
Started Nov 22 01:53:58 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 215840 kb
Host smart-8f10598c-8e3c-43f9-8e53-b78cd8aeee1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67843979608395743237188132897938732016396205660626643
505928815607915277686969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.678439796083957432371881328979
38732016396205660626643505928815607915277686969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.10681521976230831241860974276653605643829453642107208224597173104710482194702
Short name T552
Test name
Test status
Simulation time 115269125226 ps
CPU time 1744.13 seconds
Started Nov 22 01:54:23 PM PST 23
Finished Nov 22 02:23:31 PM PST 23
Peak memory 390360 kb
Host smart-c0da8c6a-0b4b-480c-a456-63420c61f9d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=10681521976230831241860974276653605643829453642107208224597173104710482194702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.kmac_test_vectors_sha3_224.10681521976230831241860974276653605643829453642107208224597173104710482194702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.11021718961503953022553825850280254169070407726103652896649998154916870308357
Short name T694
Test name
Test status
Simulation time 107886220004 ps
CPU time 1632 seconds
Started Nov 22 01:54:09 PM PST 23
Finished Nov 22 02:21:23 PM PST 23
Peak memory 370176 kb
Host smart-e3cbf712-a3f5-4882-a2ac-310d7eafd96e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11021718961503953022553825850280254169070407726103652896649998154916870308357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.kmac_test_vectors_sha3_256.11021718961503953022553825850280254169070407726103652896649998154916870308357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.102036562857893570093887823955395373653956613057097440927369800180021666443323
Short name T805
Test name
Test status
Simulation time 83070954242 ps
CPU time 1282.26 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 02:15:19 PM PST 23
Peak memory 332892 kb
Host smart-e1ae2dc8-339e-4c11-9e64-903d442a4771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=102036562857893570093887823955395373653956613057097440927369800180021666443323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.kmac_test_vectors_sha3_384.102036562857893570093887823955395373653956613057097440927369800180021666443323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.98861688085279475545004005107708788173185048415459596587656917157340935691436
Short name T990
Test name
Test status
Simulation time 58503507926 ps
CPU time 927.62 seconds
Started Nov 22 01:54:24 PM PST 23
Finished Nov 22 02:09:54 PM PST 23
Peak memory 295884 kb
Host smart-9f5a958b-890b-4790-8d35-e3a6d4a84d19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=98861688085279475545004005107708788173185048415459596587656917157340935691436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.kmac_test_vectors_sha3_512.98861688085279475545004005107708788173185048415459596587656917157340935691436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.80524831093805662344074796501765562007640457616115480711002470505018700016136
Short name T413
Test name
Test status
Simulation time 307766781661 ps
CPU time 4421.21 seconds
Started Nov 22 01:54:21 PM PST 23
Finished Nov 22 03:08:08 PM PST 23
Peak memory 653112 kb
Host smart-12ee5f4f-7f35-4a29-9ad8-c0b8beac2ebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=80524831093805662344074796501765562007640457616115480711002470505018700016136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.kmac_test_vectors_shake_128.80524831093805662344074796501765562007640457616115480711002470505018700016136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.49133631329281555273080251740567497578698053771097493096147602497236430824921
Short name T1021
Test name
Test status
Simulation time 258047411562 ps
CPU time 3730.8 seconds
Started Nov 22 01:54:24 PM PST 23
Finished Nov 22 02:56:38 PM PST 23
Peak memory 556276 kb
Host smart-c4aaf082-448a-40e7-b2be-cf2e15ee4c09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=49133631329281555273080251740567497578698053771097493096147602497236430824921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.kmac_test_vectors_shake_256.49133631329281555273080251740567497578698053771097493096147602497236430824921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.42175014176517382565446790882739027258631330047181634962748982022190646008544
Short name T135
Test name
Test status
Simulation time 21118646 ps
CPU time 0.72 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 01:54:04 PM PST 23
Peak memory 205236 kb
Host smart-7683dbb6-638e-42ed-b0c5-4298e684f74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175014176517382565446790882739027258631330047181634962748982022190646008544 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.kmac_alert_test.42175014176517382565446790882739027258631330047181634962748982022190646008544 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.99276184544552252770216892219096317871102072267576301509366974461570571057124
Short name T466
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.97 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 01:55:14 PM PST 23
Peak memory 227352 kb
Host smart-82443dd8-f400-402e-b24f-0dc589900edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99276184544552252770216892219096317871102072267576301509366974461570571057124 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.kmac_app.99276184544552252770216892219096317871102072267576301509366974461570571057124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.43805609708258998115732087457259615264853916883214912139331580206793981523149
Short name T381
Test name
Test status
Simulation time 14812750312 ps
CPU time 239.03 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 01:57:50 PM PST 23
Peak memory 225572 kb
Host smart-2fc020c4-58c4-438b-80d1-194080cc8071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43805609708258998115732087457259615264853916883214912139331580206793981523149 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.kmac_burst_write.43805609708258998115732087457259615264853916883214912139331580206793981523149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.22773761210209103208955473789155623373211161409617984088819305389536125713904
Short name T731
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.79 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 01:55:13 PM PST 23
Peak memory 226976 kb
Host smart-f3aeb0b8-985b-4d4e-9e98-e5e697d5bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22773761210209103208955473789155623373211161409617984088819305389536125713904 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.kmac_entropy_refresh.22773761210209103208955473789155623373211161409617984088819305389536125713904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.69479032664961913150045156065598469544545743644928149509290249733258818860506
Short name T952
Test name
Test status
Simulation time 8615085608 ps
CPU time 126.01 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:56:19 PM PST 23
Peak memory 248544 kb
Host smart-d976700b-6bb9-4754-9b38-6ac1af33d8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69479032664961913150045156065598469544545743644928149509290249733258818860506 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.kmac_error.69479032664961913150045156065598469544545743644928149509290249733258818860506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.5873697661740951996831612338295346094085633488681833522723875895842401499036
Short name T1059
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.3 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:54:19 PM PST 23
Peak memory 207548 kb
Host smart-bfd2c244-ad8c-40f0-b23f-74aa46b1ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5873697661740951996831612338295346094085633488681833522723875895842401499036 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.kmac_key_error.5873697661740951996831612338295346094085633488681833522723875895842401499036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.31056317005986261581924371191258140084580821501984635276047175538664278871094
Short name T23
Test name
Test status
Simulation time 58171921 ps
CPU time 1.26 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 215644 kb
Host smart-a4844814-323b-4bee-a081-0bac7acedcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31056317005986261581924371191258140084580821501984635276047175538664278871094 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.kmac_lc_escalation.31056317005986261581924371191258140084580821501984635276047175538664278871094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.28223843224635118298984727908908490702634678421789126120187088997780316463520
Short name T895
Test name
Test status
Simulation time 45517522529 ps
CPU time 693.74 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 02:05:31 PM PST 23
Peak memory 288248 kb
Host smart-06c0a422-2c52-443c-805e-5f0738597b59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223843224635118298984727908908490702634678421789126120187088997780316463520 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.282238432246351182989847279089084907026346784217891261201870889977803
16463520 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.85822581115524843851417198296326781330302272414466044305633073447129197010761
Short name T563
Test name
Test status
Simulation time 7733092664 ps
CPU time 110.75 seconds
Started Nov 22 01:53:49 PM PST 23
Finished Nov 22 01:55:41 PM PST 23
Peak memory 228172 kb
Host smart-dafad42c-2338-46bc-aded-3c949076b18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85822581115524843851417198296326781330302272414466044305633073447129197010761 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.kmac_sideload.85822581115524843851417198296326781330302272414466044305633073447129197010761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.80693067156032690935719755718670677106321462402559499661470882877898616983935
Short name T124
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.9 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 215980 kb
Host smart-76bbe9ff-7d6c-47e4-9f4f-d158e4b3d4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80693067156032690935719755718670677106321462402559499661470882877898616983935 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.kmac_smoke.80693067156032690935719755718670677106321462402559499661470882877898616983935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.30946074833975682374400488207727924941808141718868092944166635740614784991505
Short name T654
Test name
Test status
Simulation time 41434001626 ps
CPU time 618.23 seconds
Started Nov 22 01:54:06 PM PST 23
Finished Nov 22 02:04:26 PM PST 23
Peak memory 321660 kb
Host smart-237039da-6c07-4dee-a870-03ae533a97a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=30946074833975682374400488207727924941808141718868092944166635740614784991505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_st
ress_all.30946074833975682374400488207727924941808141718868092944166635740614784991505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.19629349632570404043827297962826980124965439593922606732385410276667112982100
Short name T361
Test name
Test status
Simulation time 298812853 ps
CPU time 4.13 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 01:54:10 PM PST 23
Peak memory 215596 kb
Host smart-e7db0401-ec13-4f15-8e2d-a8f6ef0c7cb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629349632570404043827297962826980124965439593922606
732385410276667112982100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac.19629349632570404043827297962826980124
965439593922606732385410276667112982100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.42054838261929134645830883674559960399782352791662674145156582149908298287042
Short name T706
Test name
Test status
Simulation time 289902210 ps
CPU time 4.08 seconds
Started Nov 22 01:54:16 PM PST 23
Finished Nov 22 01:54:21 PM PST 23
Peak memory 215732 kb
Host smart-efe6a612-8515-4a74-a634-b7ed730a1043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42054838261929134645830883674559960399782352791662674
145156582149908298287042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac_xof.420548382619291346458308836745
59960399782352791662674145156582149908298287042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.90799571857186182288618946751803790481538374547108950267108573441718694308547
Short name T336
Test name
Test status
Simulation time 115269125226 ps
CPU time 1794.08 seconds
Started Nov 22 01:53:45 PM PST 23
Finished Nov 22 02:23:41 PM PST 23
Peak memory 389524 kb
Host smart-8229adfd-0d8a-4c1d-a2ac-fc6206e0727f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90799571857186182288618946751803790481538374547108950267108573441718694308547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.kmac_test_vectors_sha3_224.90799571857186182288618946751803790481538374547108950267108573441718694308547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.90486030026464179948667724837028578843427472135592500451351764923372813075743
Short name T887
Test name
Test status
Simulation time 107886220004 ps
CPU time 1583.16 seconds
Started Nov 22 01:53:50 PM PST 23
Finished Nov 22 02:20:15 PM PST 23
Peak memory 370184 kb
Host smart-b619d974-e950-4fea-9dff-7f8857a4f952
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90486030026464179948667724837028578843427472135592500451351764923372813075743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.kmac_test_vectors_sha3_256.90486030026464179948667724837028578843427472135592500451351764923372813075743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.56334927263433203341836999390900003186185383071277876049589116580407599746976
Short name T714
Test name
Test status
Simulation time 83070954242 ps
CPU time 1214.86 seconds
Started Nov 22 01:54:06 PM PST 23
Finished Nov 22 02:14:22 PM PST 23
Peak memory 332912 kb
Host smart-bbe202f5-cff7-4ec3-9a9b-652befc03169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=56334927263433203341836999390900003186185383071277876049589116580407599746976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.kmac_test_vectors_sha3_384.56334927263433203341836999390900003186185383071277876049589116580407599746976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.57127726022370197863298889971613453287006282446939191568399670056830900347525
Short name T830
Test name
Test status
Simulation time 58503507926 ps
CPU time 886.44 seconds
Started Nov 22 01:53:56 PM PST 23
Finished Nov 22 02:08:43 PM PST 23
Peak memory 295912 kb
Host smart-b745b3fb-6f40-4b63-a31a-c79b73ad9c64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57127726022370197863298889971613453287006282446939191568399670056830900347525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.kmac_test_vectors_sha3_512.57127726022370197863298889971613453287006282446939191568399670056830900347525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.1344040434870618650316895265212443591528589254024584894416597532479234741652
Short name T738
Test name
Test status
Simulation time 307766781661 ps
CPU time 4330.42 seconds
Started Nov 22 01:54:18 PM PST 23
Finished Nov 22 03:06:31 PM PST 23
Peak memory 653004 kb
Host smart-346fe0c3-8fe5-48a3-83b4-a32789b8c832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1344040434870618650316895265212443591528589254024584894416597532479234741652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.kmac_test_vectors_shake_128.1344040434870618650316895265212443591528589254024584894416597532479234741652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.33455210818268273822739551030307963772966958230045840180024207869884968725776
Short name T293
Test name
Test status
Simulation time 258047411562 ps
CPU time 3683.47 seconds
Started Nov 22 01:53:51 PM PST 23
Finished Nov 22 02:55:16 PM PST 23
Peak memory 556296 kb
Host smart-f0c25f2f-3de1-438b-82e7-ba5545f0173c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=33455210818268273822739551030307963772966958230045840180024207869884968725776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.kmac_test_vectors_shake_256.33455210818268273822739551030307963772966958230045840180024207869884968725776 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.47159552749220869342091028486076131737379695565556397857571187318419323573304
Short name T147
Test name
Test status
Simulation time 21118646 ps
CPU time 0.72 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 01:54:17 PM PST 23
Peak memory 205236 kb
Host smart-b96d6d38-f030-4ba4-9f72-7f99b4d31b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47159552749220869342091028486076131737379695565556397857571187318419323573304 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.kmac_alert_test.47159552749220869342091028486076131737379695565556397857571187318419323573304 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.73545811366997841740925318293933337026465547864176124632462910035142154011389
Short name T428
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.6 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 01:55:30 PM PST 23
Peak memory 227376 kb
Host smart-a2ba7867-f467-4ed8-b76f-a3117f8ff922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73545811366997841740925318293933337026465547864176124632462910035142154011389 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.kmac_app.73545811366997841740925318293933337026465547864176124632462910035142154011389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.34354003170986177238464926337914104511985049675912813719287137819729371759538
Short name T674
Test name
Test status
Simulation time 14812750312 ps
CPU time 242.78 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:58:17 PM PST 23
Peak memory 225456 kb
Host smart-02d86e1f-e0d9-4f39-98d3-cd37d22c922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34354003170986177238464926337914104511985049675912813719287137819729371759538 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.kmac_burst_write.34354003170986177238464926337914104511985049675912813719287137819729371759538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.92176243653606363886747627498667701970001773252565120755687269444221443967506
Short name T1070
Test name
Test status
Simulation time 6743332725 ps
CPU time 75.35 seconds
Started Nov 22 01:54:19 PM PST 23
Finished Nov 22 01:55:36 PM PST 23
Peak memory 226932 kb
Host smart-48b54578-9f48-4eda-b422-6aab33e2c154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92176243653606363886747627498667701970001773252565120755687269444221443967506 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.kmac_entropy_refresh.92176243653606363886747627498667701970001773252565120755687269444221443967506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.16174512627359318884492698098324792341972853241132724623961858733156900947194
Short name T682
Test name
Test status
Simulation time 8615085608 ps
CPU time 125.9 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 01:56:00 PM PST 23
Peak memory 248544 kb
Host smart-4b251609-1ec4-461b-85b5-32c16f94cd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16174512627359318884492698098324792341972853241132724623961858733156900947194 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.kmac_error.16174512627359318884492698098324792341972853241132724623961858733156900947194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.105900131608480970684419355708581641598587312102656624040237155326739254911732
Short name T59
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.24 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:54:19 PM PST 23
Peak memory 207440 kb
Host smart-081eba1e-ba8e-4b22-9e37-93b2d902d727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105900131608480970684419355708581641598587312102656624040237155326739254911732 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.kmac_key_error.105900131608480970684419355708581641598587312102656624040237155326739254911732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.97723602658102630114970368021168641102591699839861004930590994754531439521132
Short name T186
Test name
Test status
Simulation time 58171921 ps
CPU time 1.22 seconds
Started Nov 22 01:53:59 PM PST 23
Finished Nov 22 01:54:02 PM PST 23
Peak memory 215748 kb
Host smart-6d04a598-2fe4-4382-8129-493024e86d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97723602658102630114970368021168641102591699839861004930590994754531439521132 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.kmac_lc_escalation.97723602658102630114970368021168641102591699839861004930590994754531439521132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.20137442175045895591664691703128315824554584060438952172542794213126563087039
Short name T546
Test name
Test status
Simulation time 45517522529 ps
CPU time 716.3 seconds
Started Nov 22 01:54:07 PM PST 23
Finished Nov 22 02:06:04 PM PST 23
Peak memory 288288 kb
Host smart-d9b33641-b319-4e7d-ad6e-675d19fc476c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137442175045895591664691703128315824554584060438952172542794213126563087039 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.201374421750458955916646917031283158245545840604389521725427942131265
63087039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.49045689502777742882367365797707683142645824548485905910579035679442698541011
Short name T294
Test name
Test status
Simulation time 7733092664 ps
CPU time 110.14 seconds
Started Nov 22 01:53:52 PM PST 23
Finished Nov 22 01:55:43 PM PST 23
Peak memory 228056 kb
Host smart-dca1ebdb-2b09-4c4d-a58d-bd01d88cfa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49045689502777742882367365797707683142645824548485905910579035679442698541011 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.kmac_sideload.49045689502777742882367365797707683142645824548485905910579035679442698541011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.104236498249099289898794756726727077931331784462071446294821645388150973504458
Short name T225
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.38 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 01:54:24 PM PST 23
Peak memory 215752 kb
Host smart-3780d460-9591-437a-8917-faa957c76b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104236498249099289898794756726727077931331784462071446294821645388150973504458 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.kmac_smoke.104236498249099289898794756726727077931331784462071446294821645388150973504458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.111006033355709307762775553571783427478781998712877603549909828090802191345131
Short name T963
Test name
Test status
Simulation time 41434001626 ps
CPU time 636.67 seconds
Started Nov 22 01:54:23 PM PST 23
Finished Nov 22 02:05:03 PM PST 23
Peak memory 321684 kb
Host smart-552436b1-467f-49c0-9f17-58e75a99860b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=111006033355709307762775553571783427478781998712877603549909828090802191345131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_s
tress_all.111006033355709307762775553571783427478781998712877603549909828090802191345131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.86235218718841692799706659904892584627907576005785612415570449628120203505166
Short name T407
Test name
Test status
Simulation time 298812853 ps
CPU time 4.45 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 01:54:11 PM PST 23
Peak memory 215764 kb
Host smart-dbb8a271-49c8-4238-b3c4-bd9978ca221f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86235218718841692799706659904892584627907576005785612
415570449628120203505166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac.86235218718841692799706659904892584627
907576005785612415570449628120203505166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.33832788463145357257549380136730888679928192627273207273281023495040154234601
Short name T346
Test name
Test status
Simulation time 289902210 ps
CPU time 4.13 seconds
Started Nov 22 01:53:54 PM PST 23
Finished Nov 22 01:53:59 PM PST 23
Peak memory 215808 kb
Host smart-70dc8c08-2417-4192-9b73-a82ca7d83c93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33832788463145357257549380136730888679928192627273207
273281023495040154234601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.338327884631453572575493801367
30888679928192627273207273281023495040154234601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.77450733378690871854390882100617213537938667228528238193554739745847329066829
Short name T408
Test name
Test status
Simulation time 115269125226 ps
CPU time 1771.85 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 02:23:46 PM PST 23
Peak memory 390444 kb
Host smart-17aac311-6c37-4e83-9c2b-ffd16a00e3fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77450733378690871854390882100617213537938667228528238193554739745847329066829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.kmac_test_vectors_sha3_224.77450733378690871854390882100617213537938667228528238193554739745847329066829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.13786218797831281837506139334345883176246514382058512704540732081368744372127
Short name T607
Test name
Test status
Simulation time 107886220004 ps
CPU time 1597.07 seconds
Started Nov 22 01:53:52 PM PST 23
Finished Nov 22 02:20:31 PM PST 23
Peak memory 370048 kb
Host smart-4e31f7a8-207e-4615-a0a2-7d7d972b3804
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=13786218797831281837506139334345883176246514382058512704540732081368744372127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.kmac_test_vectors_sha3_256.13786218797831281837506139334345883176246514382058512704540732081368744372127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.38813258456178965521027259298398547817147512234661623541532843122177850284028
Short name T320
Test name
Test status
Simulation time 83070954242 ps
CPU time 1256.26 seconds
Started Nov 22 01:53:55 PM PST 23
Finished Nov 22 02:14:53 PM PST 23
Peak memory 332916 kb
Host smart-7d02919f-fe47-4cc3-a1ef-1b6a99749640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38813258456178965521027259298398547817147512234661623541532843122177850284028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.kmac_test_vectors_sha3_384.38813258456178965521027259298398547817147512234661623541532843122177850284028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.90681239910141949781067031911478529667636011949284352976776800251743722416586
Short name T388
Test name
Test status
Simulation time 58503507926 ps
CPU time 864.86 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 02:08:29 PM PST 23
Peak memory 295816 kb
Host smart-83524f35-2f0c-4409-baf4-ad5d9fad0ecc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90681239910141949781067031911478529667636011949284352976776800251743722416586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.kmac_test_vectors_sha3_512.90681239910141949781067031911478529667636011949284352976776800251743722416586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.86876056529636444352464092147569852007653459079196357942965284627479647418093
Short name T802
Test name
Test status
Simulation time 307766781661 ps
CPU time 4518.34 seconds
Started Nov 22 01:53:46 PM PST 23
Finished Nov 22 03:09:06 PM PST 23
Peak memory 653204 kb
Host smart-fd64db5b-6b73-4a47-b610-da121949b804
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=86876056529636444352464092147569852007653459079196357942965284627479647418093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.kmac_test_vectors_shake_128.86876056529636444352464092147569852007653459079196357942965284627479647418093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.59711710764812755308362662059179162662208641030922344378326622513954929739048
Short name T212
Test name
Test status
Simulation time 258047411562 ps
CPU time 3659.95 seconds
Started Nov 22 01:54:19 PM PST 23
Finished Nov 22 02:55:21 PM PST 23
Peak memory 556200 kb
Host smart-89b4a51c-fbdb-4082-bb53-d48a8458e8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=59711710764812755308362662059179162662208641030922344378326622513954929739048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.kmac_test_vectors_shake_256.59711710764812755308362662059179162662208641030922344378326622513954929739048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.103605434082448827150496392567081315308400538938902821729611591220441762015329
Short name T55
Test name
Test status
Simulation time 21118646 ps
CPU time 0.76 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 01:54:11 PM PST 23
Peak memory 205244 kb
Host smart-f34c75a9-4fdd-41ea-a4f4-ba6c9a5e5aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103605434082448827150496392567081315308400538938902821729611591220441762015329 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.103605434082448827150496392567081315308400538938902821729611591220441762015329 +enable_masking=0
+sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.64222106829786506751669277938369562439528200253815223519883715940198795306124
Short name T601
Test name
Test status
Simulation time 5659537824 ps
CPU time 75.09 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:55:28 PM PST 23
Peak memory 227352 kb
Host smart-0b848aae-58f1-4066-b792-fc5fee956f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64222106829786506751669277938369562439528200253815223519883715940198795306124 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.kmac_app.64222106829786506751669277938369562439528200253815223519883715940198795306124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.103468287716725090293343449212818279932321088543183931327804252547342228129144
Short name T620
Test name
Test status
Simulation time 14812750312 ps
CPU time 246.13 seconds
Started Nov 22 01:54:06 PM PST 23
Finished Nov 22 01:58:13 PM PST 23
Peak memory 225516 kb
Host smart-9d7a7660-a712-4a20-8b28-bd4cf7c9b75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103468287716725090293343449212818279932321088543183931327804252547342228129144 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.kmac_burst_write.103468287716725090293343449212818279932321088543183931327804252547342228129144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.37734952145320940786744120896380325710245664323032108327869740318666889385314
Short name T409
Test name
Test status
Simulation time 6743332725 ps
CPU time 74.48 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:55:41 PM PST 23
Peak memory 226804 kb
Host smart-81095952-8ed3-47a3-a44e-bdba1029fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37734952145320940786744120896380325710245664323032108327869740318666889385314 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.kmac_entropy_refresh.37734952145320940786744120896380325710245664323032108327869740318666889385314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.99250044698763936772626486170948600950412213403867106262653307460377105166406
Short name T52
Test name
Test status
Simulation time 8615085608 ps
CPU time 131.15 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 01:56:15 PM PST 23
Peak memory 248588 kb
Host smart-03f9a0a5-94e7-4f80-8a8e-5f78a1169bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99250044698763936772626486170948600950412213403867106262653307460377105166406 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.kmac_error.99250044698763936772626486170948600950412213403867106262653307460377105166406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.107877317584279659496253631537202691506652790649104913412847059900214655218880
Short name T478
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.24 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 01:54:19 PM PST 23
Peak memory 207540 kb
Host smart-7c540339-e0f0-4293-b767-45f7d1cdfe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107877317584279659496253631537202691506652790649104913412847059900214655218880 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.kmac_key_error.107877317584279659496253631537202691506652790649104913412847059900214655218880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.39708624039028789677832127983514881628414849491514134537319434475999605065614
Short name T24
Test name
Test status
Simulation time 58171921 ps
CPU time 1.27 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 01:54:12 PM PST 23
Peak memory 215716 kb
Host smart-e9511b74-986b-4a2b-a4f3-7505f6d8caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39708624039028789677832127983514881628414849491514134537319434475999605065614 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.kmac_lc_escalation.39708624039028789677832127983514881628414849491514134537319434475999605065614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.27230244950180607727270277209058385700705155532827264804361747592234655094707
Short name T1035
Test name
Test status
Simulation time 45517522529 ps
CPU time 709.47 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 02:06:02 PM PST 23
Peak memory 288348 kb
Host smart-7f262e3b-6e3e-4b1f-ac67-c507886294fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27230244950180607727270277209058385700705155532827264804361747592234655094707 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.272302449501806077272702772090583857007051555328272648043617475922346
55094707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.44493011464409813992927079192993210737324845081019181404384775342015316849043
Short name T942
Test name
Test status
Simulation time 7733092664 ps
CPU time 113.92 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 01:56:08 PM PST 23
Peak memory 228116 kb
Host smart-bddf19ac-c131-4e78-b6d1-348d360e86ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44493011464409813992927079192993210737324845081019181404384775342015316849043 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.kmac_sideload.44493011464409813992927079192993210737324845081019181404384775342015316849043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.108412491583330171397459246177901899927881117093632005968740942187382898047005
Short name T721
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.45 seconds
Started Nov 22 01:53:53 PM PST 23
Finished Nov 22 01:54:13 PM PST 23
Peak memory 215948 kb
Host smart-4e9e145e-ea50-47ec-a4d7-df29cf094c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108412491583330171397459246177901899927881117093632005968740942187382898047005 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.kmac_smoke.108412491583330171397459246177901899927881117093632005968740942187382898047005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.39323195933764581394948114707057523494141693436779845999423343916196150116640
Short name T816
Test name
Test status
Simulation time 41434001626 ps
CPU time 610.16 seconds
Started Nov 22 01:54:00 PM PST 23
Finished Nov 22 02:04:11 PM PST 23
Peak memory 321760 kb
Host smart-c1baf669-de81-4ed4-a6ff-bc8143f45d58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=39323195933764581394948114707057523494141693436779845999423343916196150116640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_st
ress_all.39323195933764581394948114707057523494141693436779845999423343916196150116640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.81050902693437163668955183753475865103635354371943317308025329265250888753381
Short name T959
Test name
Test status
Simulation time 298812853 ps
CPU time 4.31 seconds
Started Nov 22 01:54:17 PM PST 23
Finished Nov 22 01:54:23 PM PST 23
Peak memory 215764 kb
Host smart-765393c1-496c-4419-b23f-955d4c195e11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81050902693437163668955183753475865103635354371943317
308025329265250888753381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac.81050902693437163668955183753475865103
635354371943317308025329265250888753381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.49712929814271305786515440966296726193966244187167045670201354667277635882036
Short name T559
Test name
Test status
Simulation time 289902210 ps
CPU time 4.07 seconds
Started Nov 22 01:53:59 PM PST 23
Finished Nov 22 01:54:04 PM PST 23
Peak memory 215772 kb
Host smart-79d89915-efee-47ca-8894-dbbbc919be78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49712929814271305786515440966296726193966244187167045
670201354667277635882036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac_xof.497129298142713057865154409662
96726193966244187167045670201354667277635882036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.88111444730930899656971456011097533131761188001880814950593113319007747087382
Short name T350
Test name
Test status
Simulation time 115269125226 ps
CPU time 1787.54 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 02:24:04 PM PST 23
Peak memory 390424 kb
Host smart-a42c70b8-8f91-4429-82f0-80860f3a4f40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=88111444730930899656971456011097533131761188001880814950593113319007747087382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.kmac_test_vectors_sha3_224.88111444730930899656971456011097533131761188001880814950593113319007747087382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.24817203639723785343873355631815424458809359987651757119142191384167310509055
Short name T900
Test name
Test status
Simulation time 107886220004 ps
CPU time 1665.67 seconds
Started Nov 22 01:54:04 PM PST 23
Finished Nov 22 02:21:50 PM PST 23
Peak memory 370088 kb
Host smart-93ab8bef-078f-4ead-b588-0fee7af86fc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=24817203639723785343873355631815424458809359987651757119142191384167310509055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.kmac_test_vectors_sha3_256.24817203639723785343873355631815424458809359987651757119142191384167310509055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.43275533321824080344148497832401747767775708185419933320079195742598313940289
Short name T504
Test name
Test status
Simulation time 83070954242 ps
CPU time 1196.81 seconds
Started Nov 22 01:54:20 PM PST 23
Finished Nov 22 02:14:23 PM PST 23
Peak memory 332848 kb
Host smart-1a1debd1-2b28-4d3c-899e-2ef8ea55819c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=43275533321824080344148497832401747767775708185419933320079195742598313940289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.kmac_test_vectors_sha3_384.43275533321824080344148497832401747767775708185419933320079195742598313940289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.41743743613480920389680096251007520297223649624857642856810660611588027349926
Short name T1054
Test name
Test status
Simulation time 58503507926 ps
CPU time 867.22 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 02:08:41 PM PST 23
Peak memory 295908 kb
Host smart-1f622a8b-db90-4766-84fc-ab2f21575cc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=41743743613480920389680096251007520297223649624857642856810660611588027349926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.kmac_test_vectors_sha3_512.41743743613480920389680096251007520297223649624857642856810660611588027349926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.97384729609448657495949625881985022302878010733173667425336982324358596912669
Short name T385
Test name
Test status
Simulation time 307766781661 ps
CPU time 4481.49 seconds
Started Nov 22 01:54:23 PM PST 23
Finished Nov 22 03:09:09 PM PST 23
Peak memory 653232 kb
Host smart-fbca6bf1-d6fc-4fbf-811b-a34713984b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=97384729609448657495949625881985022302878010733173667425336982324358596912669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.kmac_test_vectors_shake_128.97384729609448657495949625881985022302878010733173667425336982324358596912669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.39125421427350003215439527666030626730229521656474865398960985252465068953643
Short name T410
Test name
Test status
Simulation time 258047411562 ps
CPU time 3677.35 seconds
Started Nov 22 01:54:02 PM PST 23
Finished Nov 22 02:55:21 PM PST 23
Peak memory 556200 kb
Host smart-498f33c3-ba69-4045-a06a-3495e77fe26b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=39125421427350003215439527666030626730229521656474865398960985252465068953643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.kmac_test_vectors_shake_256.39125421427350003215439527666030626730229521656474865398960985252465068953643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.8898448202626462167633303980934358705257608096771130776871539024945313718001
Short name T54
Test name
Test status
Simulation time 21118646 ps
CPU time 0.76 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:54:13 PM PST 23
Peak memory 205180 kb
Host smart-740964f8-7a87-42f9-a0e8-949fe3c30da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8898448202626462167633303980934358705257608096771130776871539024945313718001 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.kmac_alert_test.8898448202626462167633303980934358705257608096771130776871539024945313718001 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.37739059789814208531955009788540246682458777741364278065510222253523233225877
Short name T534
Test name
Test status
Simulation time 5659537824 ps
CPU time 78.23 seconds
Started Nov 22 01:54:18 PM PST 23
Finished Nov 22 01:55:37 PM PST 23
Peak memory 227356 kb
Host smart-1f3d9a68-4f49-411e-97bb-6a10be1571ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37739059789814208531955009788540246682458777741364278065510222253523233225877 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.kmac_app.37739059789814208531955009788540246682458777741364278065510222253523233225877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.90457926874815757201644256674926998221398251400864782192491109154629508150265
Short name T1041
Test name
Test status
Simulation time 14812750312 ps
CPU time 243.12 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:58:30 PM PST 23
Peak memory 225540 kb
Host smart-951973db-0e66-44e8-b354-0e3105b57680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90457926874815757201644256674926998221398251400864782192491109154629508150265 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.kmac_burst_write.90457926874815757201644256674926998221398251400864782192491109154629508150265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.115693668121076036597204089444987719177867404470247746288255766299690210685864
Short name T406
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.32 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:55:39 PM PST 23
Peak memory 227048 kb
Host smart-bacf774e-2a1b-4e69-888f-58a688f2cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115693668121076036597204089444987719177867404470247746288255766299690210685864 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_entropy_refresh.115693668121076036597204089444987719177867404470247746288255766299690210685864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.14170934244563182035509104894957677596936997163979081180249302055917929006659
Short name T284
Test name
Test status
Simulation time 8615085608 ps
CPU time 130.35 seconds
Started Nov 22 01:54:11 PM PST 23
Finished Nov 22 01:56:22 PM PST 23
Peak memory 248612 kb
Host smart-3decd113-77fb-4766-9586-03355450e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14170934244563182035509104894957677596936997163979081180249302055917929006659 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.kmac_error.14170934244563182035509104894957677596936997163979081180249302055917929006659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.36981954742849447522468597120536613407736122269840665251044660967621419086688
Short name T915
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.25 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:54:32 PM PST 23
Peak memory 207584 kb
Host smart-3e62c5ef-3131-452b-afc8-81db04c3a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36981954742849447522468597120536613407736122269840665251044660967621419086688 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.kmac_key_error.36981954742849447522468597120536613407736122269840665251044660967621419086688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.104518151574409895179733947878383645487371749547855032330163146363664182517086
Short name T287
Test name
Test status
Simulation time 58171921 ps
CPU time 1.27 seconds
Started Nov 22 01:54:21 PM PST 23
Finished Nov 22 01:54:28 PM PST 23
Peak memory 215752 kb
Host smart-223085d3-6d98-4dc0-91de-1b9084620da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104518151574409895179733947878383645487371749547855032330163146363664182517086 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.kmac_lc_escalation.104518151574409895179733947878383645487371749547855032330163146363664182517086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.99887879312903981502335735610132410358411376578455661510373092543999299887475
Short name T250
Test name
Test status
Simulation time 45517522529 ps
CPU time 700.52 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 02:06:07 PM PST 23
Peak memory 288312 kb
Host smart-fd57e7dc-6882-433f-84f4-bdc2c12d19ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99887879312903981502335735610132410358411376578455661510373092543999299887475 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.998878793129039815023357356101324103584113765784556615103730925439992
99887475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.40689699922967052028015805655270531753997614035289437692628911105688102125939
Short name T264
Test name
Test status
Simulation time 7733092664 ps
CPU time 111.47 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:56:18 PM PST 23
Peak memory 227944 kb
Host smart-6ea85724-1268-4371-96b7-f41229311259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40689699922967052028015805655270531753997614035289437692628911105688102125939 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.kmac_sideload.40689699922967052028015805655270531753997614035289437692628911105688102125939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.88195524788458867229030322548094277119141670114911983796468381339320233564494
Short name T940
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.83 seconds
Started Nov 22 01:54:19 PM PST 23
Finished Nov 22 01:54:38 PM PST 23
Peak memory 215988 kb
Host smart-9cabc0dc-8c3f-45a7-a7a5-b8b899260826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88195524788458867229030322548094277119141670114911983796468381339320233564494 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.kmac_smoke.88195524788458867229030322548094277119141670114911983796468381339320233564494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.45161883104049873878569454769478016159270913127875519587516331668508534264290
Short name T39
Test name
Test status
Simulation time 41434001626 ps
CPU time 603.67 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 02:04:13 PM PST 23
Peak memory 321680 kb
Host smart-fdec4606-5412-4533-8ab7-9b8de6c7d126
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=45161883104049873878569454769478016159270913127875519587516331668508534264290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_st
ress_all.45161883104049873878569454769478016159270913127875519587516331668508534264290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.7465411705153228492874963759078668165941911615703522926262051557842596692913
Short name T131
Test name
Test status
Simulation time 298812853 ps
CPU time 4.5 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:54:31 PM PST 23
Peak memory 215812 kb
Host smart-ea7c3612-8343-46cc-afb8-687667c4d3dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74654117051532284928749637590786681659419116157035229
26262051557842596692913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac.746541170515322849287496375907866816594
1911615703522926262051557842596692913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.44471205007801349960482092046214596662319873236671549985041954610311297622576
Short name T1018
Test name
Test status
Simulation time 289902210 ps
CPU time 4.29 seconds
Started Nov 22 01:54:15 PM PST 23
Finished Nov 22 01:54:21 PM PST 23
Peak memory 215808 kb
Host smart-cb092a5a-cc11-46c3-87de-30bac2b1bb7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44471205007801349960482092046214596662319873236671549
985041954610311297622576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac_xof.444712050078013499604820920462
14596662319873236671549985041954610311297622576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2656102568698575047973916975615210700629875683026802660603886783213857174341
Short name T662
Test name
Test status
Simulation time 115269125226 ps
CPU time 1794.37 seconds
Started Nov 22 01:54:12 PM PST 23
Finished Nov 22 02:24:08 PM PST 23
Peak memory 390448 kb
Host smart-abfbc18c-e612-4e47-8222-aa7f7849a293
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2656102568698575047973916975615210700629875683026802660603886783213857174341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
kmac_test_vectors_sha3_224.2656102568698575047973916975615210700629875683026802660603886783213857174341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.107235697175414835281506607425315787085693825881567230694901986806981708922039
Short name T622
Test name
Test status
Simulation time 107886220004 ps
CPU time 1571.33 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 02:20:25 PM PST 23
Peak memory 370156 kb
Host smart-5a37f1c2-151e-4552-8816-c81009a37ea2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=107235697175414835281506607425315787085693825881567230694901986806981708922039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.kmac_test_vectors_sha3_256.107235697175414835281506607425315787085693825881567230694901986806981708922039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.83524809596817630891242239103840203707492510450902639782000060437019693018568
Short name T693
Test name
Test status
Simulation time 83070954242 ps
CPU time 1296.73 seconds
Started Nov 22 01:54:21 PM PST 23
Finished Nov 22 02:16:04 PM PST 23
Peak memory 332928 kb
Host smart-6a5f3c0a-3bd9-4682-9a98-40c8fbbea474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=83524809596817630891242239103840203707492510450902639782000060437019693018568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.kmac_test_vectors_sha3_384.83524809596817630891242239103840203707492510450902639782000060437019693018568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.90839032215436056698628087410645072479405803125032932315182348424854269587810
Short name T305
Test name
Test status
Simulation time 58503507926 ps
CPU time 892.41 seconds
Started Nov 22 01:54:10 PM PST 23
Finished Nov 22 02:09:03 PM PST 23
Peak memory 295944 kb
Host smart-9e3b9d4a-fe48-4d90-af46-44ebb29e2152
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90839032215436056698628087410645072479405803125032932315182348424854269587810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.kmac_test_vectors_sha3_512.90839032215436056698628087410645072479405803125032932315182348424854269587810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.47544123969161569704350824261994462641828765213715953028932299623270899050594
Short name T673
Test name
Test status
Simulation time 307766781661 ps
CPU time 4414.85 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 03:08:02 PM PST 23
Peak memory 653272 kb
Host smart-1bccdfe0-f01e-4783-9dcc-c51bc9fbeb86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=47544123969161569704350824261994462641828765213715953028932299623270899050594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.kmac_test_vectors_shake_128.47544123969161569704350824261994462641828765213715953028932299623270899050594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.9264693534910871938806071821206494360937931562209377754043872781569106911753
Short name T608
Test name
Test status
Simulation time 258047411562 ps
CPU time 3633.96 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 02:54:48 PM PST 23
Peak memory 556360 kb
Host smart-faf43401-a52c-4581-acc7-10345fa0f980
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=9264693534910871938806071821206494360937931562209377754043872781569106911753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.kmac_test_vectors_shake_256.9264693534910871938806071821206494360937931562209377754043872781569106911753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.71311809526019456768120434855376579277299675090111058483766138082873996854773
Short name T970
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:54:18 PM PST 23
Finished Nov 22 01:54:21 PM PST 23
Peak memory 205212 kb
Host smart-bddb986d-e8de-45fc-923d-4e86ac698ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71311809526019456768120434855376579277299675090111058483766138082873996854773 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.kmac_alert_test.71311809526019456768120434855376579277299675090111058483766138082873996854773 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.98658876630616316913989250492607730122380956923776558956827603753558670011677
Short name T46
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.49 seconds
Started Nov 22 01:54:16 PM PST 23
Finished Nov 22 01:55:31 PM PST 23
Peak memory 227392 kb
Host smart-d3647f20-8d2e-4fc5-aa43-f570bd7041de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98658876630616316913989250492607730122380956923776558956827603753558670011677 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.kmac_app.98658876630616316913989250492607730122380956923776558956827603753558670011677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.74358588830126096083220106920243044743447750452527000619242733588656945213830
Short name T204
Test name
Test status
Simulation time 14812750312 ps
CPU time 254.68 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:58:41 PM PST 23
Peak memory 225560 kb
Host smart-60cbe411-8bec-4c6b-8cd3-d046b9029c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74358588830126096083220106920243044743447750452527000619242733588656945213830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.kmac_burst_write.74358588830126096083220106920243044743447750452527000619242733588656945213830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.72507361909693282046209651361029805157907331077816909966325645678609316132745
Short name T173
Test name
Test status
Simulation time 6743332725 ps
CPU time 72 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 01:55:50 PM PST 23
Peak memory 226976 kb
Host smart-fc555d8f-0b67-465f-bf57-6497d50e2f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72507361909693282046209651361029805157907331077816909966325645678609316132745 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.kmac_entropy_refresh.72507361909693282046209651361029805157907331077816909966325645678609316132745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.45004058440593545303665105754926768023923970061340951006045177630980029467100
Short name T257
Test name
Test status
Simulation time 8615085608 ps
CPU time 132.43 seconds
Started Nov 22 01:54:35 PM PST 23
Finished Nov 22 01:56:48 PM PST 23
Peak memory 248628 kb
Host smart-4c09bcf4-299c-4e6e-aa60-f5e6787d702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45004058440593545303665105754926768023923970061340951006045177630980029467100 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.kmac_error.45004058440593545303665105754926768023923970061340951006045177630980029467100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.29610024201277886637709858122477350060788430803691244160007697938330641309731
Short name T735
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.27 seconds
Started Nov 22 01:54:22 PM PST 23
Finished Nov 22 01:54:32 PM PST 23
Peak memory 207600 kb
Host smart-c95c1ea9-1df0-48a5-8481-a10102daefaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29610024201277886637709858122477350060788430803691244160007697938330641309731 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.kmac_key_error.29610024201277886637709858122477350060788430803691244160007697938330641309731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.24339274888785232977438674893511372553091541876238752412776913888501721452823
Short name T275
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:54:21 PM PST 23
Finished Nov 22 01:54:28 PM PST 23
Peak memory 215584 kb
Host smart-764e776a-22ed-4505-a8e4-d13586322198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24339274888785232977438674893511372553091541876238752412776913888501721452823 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.kmac_lc_escalation.24339274888785232977438674893511372553091541876238752412776913888501721452823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.39934485988913591761089194331827042582068867661160765169076158581106777956807
Short name T585
Test name
Test status
Simulation time 45517522529 ps
CPU time 742.33 seconds
Started Nov 22 01:54:08 PM PST 23
Finished Nov 22 02:06:32 PM PST 23
Peak memory 288264 kb
Host smart-dd3af17b-fa7d-4c73-8bd8-54260f3d7ce4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39934485988913591761089194331827042582068867661160765169076158581106777956807 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.399344859889135917610891943318270425820688676611607651690761585811067
77956807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.28704705522097904999655810323834710842460809197133970110017130622682596891259
Short name T993
Test name
Test status
Simulation time 7733092664 ps
CPU time 108.98 seconds
Started Nov 22 01:54:20 PM PST 23
Finished Nov 22 01:56:14 PM PST 23
Peak memory 228136 kb
Host smart-c70d582d-736f-461a-b9c4-150270e2b9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28704705522097904999655810323834710842460809197133970110017130622682596891259 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.kmac_sideload.28704705522097904999655810323834710842460809197133970110017130622682596891259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.94504598158261712674931613484806950286500881518877630103172020075446483167334
Short name T278
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.58 seconds
Started Nov 22 01:54:20 PM PST 23
Finished Nov 22 01:54:43 PM PST 23
Peak memory 215956 kb
Host smart-c7b9d6ae-9b3d-40c1-8d88-8b61a1dc5937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94504598158261712674931613484806950286500881518877630103172020075446483167334 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.kmac_smoke.94504598158261712674931613484806950286500881518877630103172020075446483167334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.105037885682600095989754836414539355823838707561445472755034461516964151543914
Short name T799
Test name
Test status
Simulation time 41434001626 ps
CPU time 593.73 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 02:04:32 PM PST 23
Peak memory 321700 kb
Host smart-aad9a66f-d7c6-41de-a8e1-c665e878181a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=105037885682600095989754836414539355823838707561445472755034461516964151543914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_s
tress_all.105037885682600095989754836414539355823838707561445472755034461516964151543914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.75440354545739717382155807725151143317026127318975049148563360636879358992934
Short name T633
Test name
Test status
Simulation time 298812853 ps
CPU time 4.43 seconds
Started Nov 22 01:54:31 PM PST 23
Finished Nov 22 01:54:36 PM PST 23
Peak memory 215812 kb
Host smart-9c46be87-8309-4423-899d-2610b19b70b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75440354545739717382155807725151143317026127318975049
148563360636879358992934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac.75440354545739717382155807725151143317
026127318975049148563360636879358992934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.45649419383245491611333882067587017130781755647454660040060330516775680112822
Short name T833
Test name
Test status
Simulation time 289902210 ps
CPU time 4.13 seconds
Started Nov 22 01:54:40 PM PST 23
Finished Nov 22 01:54:45 PM PST 23
Peak memory 215788 kb
Host smart-71b36730-253d-4dab-a877-fabe726c1ca9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45649419383245491611333882067587017130781755647454660
040060330516775680112822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.456494193832454916113338820675
87017130781755647454660040060330516775680112822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.45594944872358001007776980950699512833159351137285965260204886972305119368539
Short name T175
Test name
Test status
Simulation time 115269125226 ps
CPU time 1693.27 seconds
Started Nov 22 01:54:05 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 390440 kb
Host smart-c9770de2-38b8-46ea-85b6-c1d278cae7d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45594944872358001007776980950699512833159351137285965260204886972305119368539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.kmac_test_vectors_sha3_224.45594944872358001007776980950699512833159351137285965260204886972305119368539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1286428659636275870131675174679747369470128873726178108306258574348752126131
Short name T834
Test name
Test status
Simulation time 107886220004 ps
CPU time 1634.22 seconds
Started Nov 22 01:54:46 PM PST 23
Finished Nov 22 02:22:02 PM PST 23
Peak memory 370168 kb
Host smart-79897c17-d837-4290-a12a-8ca55dcca971
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1286428659636275870131675174679747369470128873726178108306258574348752126131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
kmac_test_vectors_sha3_256.1286428659636275870131675174679747369470128873726178108306258574348752126131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.1988435997181610391988894716978517933365439437102068177324570947566636476382
Short name T881
Test name
Test status
Simulation time 83070954242 ps
CPU time 1253.61 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 02:15:28 PM PST 23
Peak memory 332912 kb
Host smart-5c01f3e1-7bd6-43a8-a4b4-a28719b1129d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1988435997181610391988894716978517933365439437102068177324570947566636476382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
kmac_test_vectors_sha3_384.1988435997181610391988894716978517933365439437102068177324570947566636476382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.101081627805194807513913062778287415353311547428513038558893557253490819684642
Short name T453
Test name
Test status
Simulation time 58503507926 ps
CPU time 922.16 seconds
Started Nov 22 01:54:25 PM PST 23
Finished Nov 22 02:09:51 PM PST 23
Peak memory 295908 kb
Host smart-d1b2d17f-0024-4be5-a01d-75ac72b40ea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=101081627805194807513913062778287415353311547428513038558893557253490819684642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.kmac_test_vectors_sha3_512.101081627805194807513913062778287415353311547428513038558893557253490819684642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.30742059289359066076638411015878859423429085272635770141286255885667672835290
Short name T332
Test name
Test status
Simulation time 307766781661 ps
CPU time 4533.26 seconds
Started Nov 22 01:54:31 PM PST 23
Finished Nov 22 03:10:05 PM PST 23
Peak memory 653192 kb
Host smart-ddf4baf1-99d7-421b-9044-8396877fd53f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=30742059289359066076638411015878859423429085272635770141286255885667672835290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.kmac_test_vectors_shake_128.30742059289359066076638411015878859423429085272635770141286255885667672835290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.4462114097028056723578322010518806994166493718186538718878545944112032922483
Short name T400
Test name
Test status
Simulation time 258047411562 ps
CPU time 3640.88 seconds
Started Nov 22 01:54:39 PM PST 23
Finished Nov 22 02:55:21 PM PST 23
Peak memory 556320 kb
Host smart-af5a7358-0506-4bdf-8e75-7a87a625d8bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4462114097028056723578322010518806994166493718186538718878545944112032922483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.kmac_test_vectors_shake_256.4462114097028056723578322010518806994166493718186538718878545944112032922483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.75156516089387105334973813825586945016467127982517056425772298202492623252596
Short name T245
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 205252 kb
Host smart-74bf8b2f-6161-42be-ae44-1e9f54afae8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75156516089387105334973813825586945016467127982517056425772298202492623252596 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.kmac_alert_test.75156516089387105334973813825586945016467127982517056425772298202492623252596 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.12874553621672108677658709994026024139818584767772516090679386223791345454493
Short name T452
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.42 seconds
Started Nov 22 01:54:43 PM PST 23
Finished Nov 22 01:56:01 PM PST 23
Peak memory 227388 kb
Host smart-e0d24709-b907-41ab-ad06-01bc368e07e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12874553621672108677658709994026024139818584767772516090679386223791345454493 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.kmac_app.12874553621672108677658709994026024139818584767772516090679386223791345454493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.55670914092067377632905987082857151131711202209400950028053064229422630694796
Short name T787
Test name
Test status
Simulation time 14812750312 ps
CPU time 248.65 seconds
Started Nov 22 01:54:13 PM PST 23
Finished Nov 22 01:58:22 PM PST 23
Peak memory 225568 kb
Host smart-60e5b2c1-09df-4c7f-890c-64dffadf28e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55670914092067377632905987082857151131711202209400950028053064229422630694796 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.kmac_burst_write.55670914092067377632905987082857151131711202209400950028053064229422630694796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.18322899168350067773203457299647109060864308838036907738603554081084648273587
Short name T542
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.4 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 01:55:51 PM PST 23
Peak memory 226980 kb
Host smart-b79f2232-5292-4e3a-afe7-6ec1455bbdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18322899168350067773203457299647109060864308838036907738603554081084648273587 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.kmac_entropy_refresh.18322899168350067773203457299647109060864308838036907738603554081084648273587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.63595407943011012379362371571001478436798373816295548857153491424254466475364
Short name T768
Test name
Test status
Simulation time 8615085608 ps
CPU time 129.91 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 01:56:47 PM PST 23
Peak memory 248672 kb
Host smart-751ab04b-c943-40c1-8a9e-d2a724cd3f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63595407943011012379362371571001478436798373816295548857153491424254466475364 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.kmac_error.63595407943011012379362371571001478436798373816295548857153491424254466475364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.40244804477197862428596601811754449769899693394766474950015832388316845261134
Short name T438
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.3 seconds
Started Nov 22 01:54:45 PM PST 23
Finished Nov 22 01:54:51 PM PST 23
Peak memory 207528 kb
Host smart-1975b941-d19b-4739-9870-58d0ae2871bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40244804477197862428596601811754449769899693394766474950015832388316845261134 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.kmac_key_error.40244804477197862428596601811754449769899693394766474950015832388316845261134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.31046860564096767647764576823600447460789676824336938076342891589002573001183
Short name T316
Test name
Test status
Simulation time 58171921 ps
CPU time 1.2 seconds
Started Nov 22 01:54:46 PM PST 23
Finished Nov 22 01:54:48 PM PST 23
Peak memory 215636 kb
Host smart-f32a4cb0-1325-40ed-a486-2a099f223dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31046860564096767647764576823600447460789676824336938076342891589002573001183 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.kmac_lc_escalation.31046860564096767647764576823600447460789676824336938076342891589002573001183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.55908805551187094391630930651681452424251270365122282360005534188324880828765
Short name T814
Test name
Test status
Simulation time 45517522529 ps
CPU time 723.84 seconds
Started Nov 22 01:54:20 PM PST 23
Finished Nov 22 02:06:28 PM PST 23
Peak memory 288380 kb
Host smart-fc5e7f9f-51c4-488c-bc9a-5ee715e529a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55908805551187094391630930651681452424251270365122282360005534188324880828765 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.559088055511870943916309306516814524242512703651222823600055341883248
80828765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.35757935496003551285153288783661130724407472764951647207560920022733154061417
Short name T978
Test name
Test status
Simulation time 7733092664 ps
CPU time 117.15 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 01:56:31 PM PST 23
Peak memory 228160 kb
Host smart-8467893c-736b-434a-8e54-1a5c40b5e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35757935496003551285153288783661130724407472764951647207560920022733154061417 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.kmac_sideload.35757935496003551285153288783661130724407472764951647207560920022733154061417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.15639185803333636838514827311293731479835284884311022694778378443050622330838
Short name T862
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.65 seconds
Started Nov 22 01:54:27 PM PST 23
Finished Nov 22 01:54:49 PM PST 23
Peak memory 215952 kb
Host smart-066a67ca-6020-4a33-98d2-8ef0499cb3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15639185803333636838514827311293731479835284884311022694778378443050622330838 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.kmac_smoke.15639185803333636838514827311293731479835284884311022694778378443050622330838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.28602219817701363766893217855103109338503624386955196023504145516385896471437
Short name T261
Test name
Test status
Simulation time 41434001626 ps
CPU time 591.61 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 02:04:42 PM PST 23
Peak memory 321712 kb
Host smart-2d34e49b-aeb6-4fdf-a831-0e2b46119a6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=28602219817701363766893217855103109338503624386955196023504145516385896471437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_st
ress_all.28602219817701363766893217855103109338503624386955196023504145516385896471437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.96806014834414784367292572912899009001337637072645864232262093600864922806344
Short name T961
Test name
Test status
Simulation time 298812853 ps
CPU time 4.38 seconds
Started Nov 22 01:54:29 PM PST 23
Finished Nov 22 01:54:35 PM PST 23
Peak memory 215744 kb
Host smart-58742111-f51e-4c2d-b185-705cc1e955c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96806014834414784367292572912899009001337637072645864
232262093600864922806344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac.96806014834414784367292572912899009001
337637072645864232262093600864922806344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.35307365356702850598363968756059112873998326972970475502889803540646503149768
Short name T211
Test name
Test status
Simulation time 289902210 ps
CPU time 4.36 seconds
Started Nov 22 01:54:32 PM PST 23
Finished Nov 22 01:54:37 PM PST 23
Peak memory 215824 kb
Host smart-f4822f45-2263-46f8-acb0-cc1c6ea050a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35307365356702850598363968756059112873998326972970475
502889803540646503149768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.353073653567028505983639687560
59112873998326972970475502889803540646503149768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.89635624882438439451586406156832112205615688167608292611353077876371677158799
Short name T390
Test name
Test status
Simulation time 115269125226 ps
CPU time 1668.59 seconds
Started Nov 22 01:54:34 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 390356 kb
Host smart-e7a31eba-41f4-4cc8-ae88-f8b2521c244d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89635624882438439451586406156832112205615688167608292611353077876371677158799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.kmac_test_vectors_sha3_224.89635624882438439451586406156832112205615688167608292611353077876371677158799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.17695457285776779843052878359897905983258910333993834949787003838055054012785
Short name T677
Test name
Test status
Simulation time 107886220004 ps
CPU time 1562.41 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 02:20:37 PM PST 23
Peak memory 370152 kb
Host smart-26ef9cc2-7317-4555-a06f-39b6ca4e8cc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=17695457285776779843052878359897905983258910333993834949787003838055054012785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.kmac_test_vectors_sha3_256.17695457285776779843052878359897905983258910333993834949787003838055054012785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.34323549713123180120666080307612761584739833267469718445379686242407727350824
Short name T394
Test name
Test status
Simulation time 83070954242 ps
CPU time 1243.39 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 02:15:17 PM PST 23
Peak memory 332912 kb
Host smart-c35e64a2-e277-4d55-99a9-55d764cec280
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=34323549713123180120666080307612761584739833267469718445379686242407727350824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.kmac_test_vectors_sha3_384.34323549713123180120666080307612761584739833267469718445379686242407727350824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.91073733282472317751331477146617499752612996570738869405025764147709261809029
Short name T183
Test name
Test status
Simulation time 58503507926 ps
CPU time 886.92 seconds
Started Nov 22 01:54:32 PM PST 23
Finished Nov 22 02:09:20 PM PST 23
Peak memory 296004 kb
Host smart-87836556-2302-4aca-b52a-3e5002dd5f0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=91073733282472317751331477146617499752612996570738869405025764147709261809029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.kmac_test_vectors_sha3_512.91073733282472317751331477146617499752612996570738869405025764147709261809029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.63503420011115770703954520812552130089839963901649012491826721867044340956178
Short name T668
Test name
Test status
Simulation time 307766781661 ps
CPU time 4517.86 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 03:09:56 PM PST 23
Peak memory 653200 kb
Host smart-ec579850-43e7-41f9-b14b-0e7cd6e7010c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=63503420011115770703954520812552130089839963901649012491826721867044340956178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.kmac_test_vectors_shake_128.63503420011115770703954520812552130089839963901649012491826721867044340956178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.113963553515159086940254078538717223667940979483552327939686154057082858987093
Short name T281
Test name
Test status
Simulation time 258047411562 ps
CPU time 3750.8 seconds
Started Nov 22 01:54:30 PM PST 23
Finished Nov 22 02:57:02 PM PST 23
Peak memory 556300 kb
Host smart-f5638b40-8e78-49e6-98e8-1a1623d9f340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=113963553515159086940254078538717223667940979483552327939686154057082858987093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.kmac_test_vectors_shake_256.113963553515159086940254078538717223667940979483552327939686154057082858987093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.75900130372302542253971875900449752208341094233863922431332074558304210740138
Short name T1039
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:53:36 PM PST 23
Finished Nov 22 01:53:38 PM PST 23
Peak memory 205224 kb
Host smart-90917a8f-1f9a-4762-8913-7f7eed7aacf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75900130372302542253971875900449752208341094233863922431332074558304210740138 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.kmac_alert_test.75900130372302542253971875900449752208341094233863922431332074558304210740138 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.113525189115731980179395214450152715483075342334142175011175020917879271452396
Short name T176
Test name
Test status
Simulation time 5659537824 ps
CPU time 76.01 seconds
Started Nov 22 01:52:51 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 227328 kb
Host smart-e9ee46ac-6c8e-4f18-8744-0753a35c0684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113525189115731980179395214450152715483075342334142175011175020917879271452396 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.kmac_app.113525189115731980179395214450152715483075342334142175011175020917879271452396 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.87646886777812235065465952032983506440543758574878493615126163422255110739414
Short name T267
Test name
Test status
Simulation time 7615861459 ps
CPU time 83.94 seconds
Started Nov 22 01:52:51 PM PST 23
Finished Nov 22 01:54:17 PM PST 23
Peak memory 225912 kb
Host smart-140706f6-aeaf-4017-b767-8ae1ac8f43db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87646886777812235065465952032983506440543758574878493615126163422255110739414 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_app_with_partial_data.87646886777812235065465952032983506440543758574878493615126163422255110739414 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.68592462134813279448231444672090107071997884093609195190135483152518025075608
Short name T879
Test name
Test status
Simulation time 14812750312 ps
CPU time 246.18 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:56:52 PM PST 23
Peak memory 225496 kb
Host smart-9becf123-f164-4efa-84f4-9ccfa312662b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68592462134813279448231444672090107071997884093609195190135483152518025075608 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.kmac_burst_write.68592462134813279448231444672090107071997884093609195190135483152518025075608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.83058536111427304088746288419140758360156415653468385232153114250768579146901
Short name T1051
Test name
Test status
Simulation time 2342046507 ps
CPU time 34.44 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 01:53:29 PM PST 23
Peak memory 223844 kb
Host smart-4603a613-2ff5-44c8-998d-65a862c2c2e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=83058536111427304088746288419140758360156415653468385232153114250768579146901 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.kmac_edn_timeout_error.83058536111427304088746288419140758360156415653468385232153114250768579146901 +enable_masking=0
+sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.21425750909173466833053101037894314396523047485470044981362425632798519489640
Short name T789
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.01 seconds
Started Nov 22 01:53:03 PM PST 23
Finished Nov 22 01:53:34 PM PST 23
Peak memory 223884 kb
Host smart-e8d90b66-7cb1-4293-8daf-c5db8b4f0972
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=21425750909173466833053101037894314396523047485470044981362425632798519489640 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.21425750909173466833053101037894314396523047485470044981362425632798519489640 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.56640987630512687039778911984416751094127035929343984057260280743300293646042
Short name T430
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.09 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 01:53:42 PM PST 23
Peak memory 216960 kb
Host smart-bff7304a-b299-46d7-ba2b-d11ead07e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56640987630512687039778911984416751094127035929343984057260280743300293646042 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.kmac_entropy_ready_error.56640987630512687039778911984416751094127035929343984057260280743300293646042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.74491391377624846277602954288574694364960987611766532502898115456210540585799
Short name T815
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.73 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:54:05 PM PST 23
Peak memory 226980 kb
Host smart-a243be9a-86d4-4ec1-96c6-0cafec411aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74491391377624846277602954288574694364960987611766532502898115456210540585799 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.kmac_entropy_refresh.74491391377624846277602954288574694364960987611766532502898115456210540585799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.19263618574517304493249659369751832979448279780119165720735720723310074707498
Short name T525
Test name
Test status
Simulation time 8615085608 ps
CPU time 129.83 seconds
Started Nov 22 01:52:52 PM PST 23
Finished Nov 22 01:55:04 PM PST 23
Peak memory 248600 kb
Host smart-f5ba5823-5ad8-4ac3-9334-a7aafa38c11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19263618574517304493249659369751832979448279780119165720735720723310074707498 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.kmac_error.19263618574517304493249659369751832979448279780119165720735720723310074707498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.71108242034659536656586137407005757502065615263758769170729427677704567880273
Short name T329
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.3 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 207556 kb
Host smart-56662330-80b7-4272-89e5-3f0e2a0424b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71108242034659536656586137407005757502065615263758769170729427677704567880273 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.kmac_key_error.71108242034659536656586137407005757502065615263758769170729427677704567880273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.50358032738452881238368442508634484977232546880448954449286800514512399196603
Short name T437
Test name
Test status
Simulation time 58171921 ps
CPU time 1.21 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 01:53:25 PM PST 23
Peak memory 215676 kb
Host smart-389ccd11-001b-4adf-96ec-b90513ac03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50358032738452881238368442508634484977232546880448954449286800514512399196603 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.kmac_lc_escalation.50358032738452881238368442508634484977232546880448954449286800514512399196603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.26657551898177739448050307946986261761247440118364043028212175141416402669341
Short name T904
Test name
Test status
Simulation time 45517522529 ps
CPU time 700.13 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 02:04:31 PM PST 23
Peak memory 288332 kb
Host smart-d8e73253-5788-4217-b2b1-82c7abd2e118
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26657551898177739448050307946986261761247440118364043028212175141416402669341 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.2665755189817773944805030794698626176124744011836404302821217514141640
2669341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.43254074947282215544620039067573195030936330780823848623243132984583811678855
Short name T240
Test name
Test status
Simulation time 5640716546 ps
CPU time 70.77 seconds
Started Nov 22 01:52:54 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 227696 kb
Host smart-bba02caa-f717-40f6-a91b-ef575c0b24d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43254074947282215544620039067573195030936330780823848623243132984583811678855 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.kmac_mubi.43254074947282215544620039067573195030936330780823848623243132984583811678855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.9699740691301480446127779782576809309768684880882628519657244581816958502906
Short name T68
Test name
Test status
Simulation time 4127675079 ps
CPU time 31.66 seconds
Started Nov 22 01:52:46 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 248948 kb
Host smart-197c960d-2384-438e-9379-b498f5ed6cf5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9699740691301480446127779782576809309768684880882628519657244581816958502906 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.kmac_sec_cm.9699740691301480446127779782576809309768684880882628519657244581816958502906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.5695119405219161558373881368955076629831455289446519936582041067278473761094
Short name T162
Test name
Test status
Simulation time 7733092664 ps
CPU time 113.42 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 01:54:48 PM PST 23
Peak memory 228112 kb
Host smart-9ce8224d-203d-4765-93e1-96dabe02bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5695119405219161558373881368955076629831455289446519936582041067278473761094 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.kmac_sideload.5695119405219161558373881368955076629831455289446519936582041067278473761094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.54089661081270682872750456024684782123735199676732408994239541050914435282377
Short name T539
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.34 seconds
Started Nov 22 01:52:56 PM PST 23
Finished Nov 22 01:53:15 PM PST 23
Peak memory 215988 kb
Host smart-453cdc5f-0cd2-4200-908f-b698fec170b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54089661081270682872750456024684782123735199676732408994239541050914435282377 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.kmac_smoke.54089661081270682872750456024684782123735199676732408994239541050914435282377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.54162888308339026784829831617578842244085682301860372694068007741222658325675
Short name T854
Test name
Test status
Simulation time 41434001626 ps
CPU time 629.07 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 02:03:48 PM PST 23
Peak memory 321728 kb
Host smart-c0856791-6a53-4985-9d30-07e7bebcb27c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=54162888308339026784829831617578842244085682301860372694068007741222658325675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_str
ess_all.54162888308339026784829831617578842244085682301860372694068007741222658325675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.111755339366536728793187015854575549948831814588552854180164899043469434965605
Short name T882
Test name
Test status
Simulation time 298812853 ps
CPU time 4.31 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:52:56 PM PST 23
Peak memory 215844 kb
Host smart-cd2d3bad-217e-4ecb-b2d2-a8d7d0609779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175533936653672879318701585457554994883181458855285
4180164899043469434965605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.11175533936653672879318701585457554994
8831814588552854180164899043469434965605 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.34777395166996828509423059936488884052304054959268163743306190569993628248002
Short name T32
Test name
Test status
Simulation time 289902210 ps
CPU time 4.01 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 01:52:57 PM PST 23
Peak memory 215784 kb
Host smart-fcd19c1e-5151-49c2-acd5-dff55b963941
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34777395166996828509423059936488884052304054959268163
743306190569993628248002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3477739516699682850942305993648
8884052304054959268163743306190569993628248002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.53711456454206812156256410207080370021038657940276243146170405765491434830729
Short name T630
Test name
Test status
Simulation time 115269125226 ps
CPU time 1674.55 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 02:20:44 PM PST 23
Peak memory 390348 kb
Host smart-8b6c2597-983b-4c15-9ffe-7ecf9b30273b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=53711456454206812156256410207080370021038657940276243146170405765491434830729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
kmac_test_vectors_sha3_224.53711456454206812156256410207080370021038657940276243146170405765491434830729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.61934507393385941897732271547259959140650208673317536263521834450619416896559
Short name T280
Test name
Test status
Simulation time 107886220004 ps
CPU time 1619.38 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 02:19:52 PM PST 23
Peak memory 370080 kb
Host smart-d29b7ca9-74b6-45dc-ac47-f322e46b232d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61934507393385941897732271547259959140650208673317536263521834450619416896559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
kmac_test_vectors_sha3_256.61934507393385941897732271547259959140650208673317536263521834450619416896559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.16771815914696149684554347956412175043979148633518264123717641616429393296039
Short name T304
Test name
Test status
Simulation time 83070954242 ps
CPU time 1229.25 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 02:13:22 PM PST 23
Peak memory 332880 kb
Host smart-18352672-0286-4332-a5e7-cabc0ecf97c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16771815914696149684554347956412175043979148633518264123717641616429393296039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
kmac_test_vectors_sha3_384.16771815914696149684554347956412175043979148633518264123717641616429393296039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.90304717245026298321246517824064409710869456970123334150870261583380503395507
Short name T286
Test name
Test status
Simulation time 58503507926 ps
CPU time 859.81 seconds
Started Nov 22 01:52:46 PM PST 23
Finished Nov 22 02:07:10 PM PST 23
Peak memory 295836 kb
Host smart-47fed3f4-d5d4-48b8-9d52-dbd9dee589f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=90304717245026298321246517824064409710869456970123334150870261583380503395507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
kmac_test_vectors_sha3_512.90304717245026298321246517824064409710869456970123334150870261583380503395507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.42391784258431795334071964554876794472912306440466516914747501448037188659900
Short name T983
Test name
Test status
Simulation time 307766781661 ps
CPU time 4533.09 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 03:08:25 PM PST 23
Peak memory 653164 kb
Host smart-0cd5af79-6a7a-489e-b7f8-e62b6ad0bfeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=42391784258431795334071964554876794472912306440466516914747501448037188659900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.kmac_test_vectors_shake_128.42391784258431795334071964554876794472912306440466516914747501448037188659900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.23925283647446120069050200957376991413319055279966277465210867652566883355151
Short name T533
Test name
Test status
Simulation time 258047411562 ps
CPU time 3661.34 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 02:53:54 PM PST 23
Peak memory 556368 kb
Host smart-80d0c775-a387-4c19-ac78-cd3cb372d580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=23925283647446120069050200957376991413319055279966277465210867652566883355151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.kmac_test_vectors_shake_256.23925283647446120069050200957376991413319055279966277465210867652566883355151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.92939463550512265533082360256960278955065230193419090488262147166143085695440
Short name T688
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:54:53 PM PST 23
Peak memory 205256 kb
Host smart-7dfc75d7-a286-415a-80a3-f64ebf8a5240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92939463550512265533082360256960278955065230193419090488262147166143085695440 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.kmac_alert_test.92939463550512265533082360256960278955065230193419090488262147166143085695440 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.42566120521155456583137686683022456930118530885017214675416457631782480923037
Short name T1046
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.86 seconds
Started Nov 22 01:54:34 PM PST 23
Finished Nov 22 01:55:49 PM PST 23
Peak memory 227348 kb
Host smart-ff835a0d-f07a-48ee-ac2d-54af6d2ca0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42566120521155456583137686683022456930118530885017214675416457631782480923037 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.kmac_app.42566120521155456583137686683022456930118530885017214675416457631782480923037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.61997485482301350969833748360621159286305135448859817314122397991134286237320
Short name T907
Test name
Test status
Simulation time 14812750312 ps
CPU time 244.06 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 225576 kb
Host smart-f6f0acdf-0c6c-4134-9ebb-9ccfa31d2770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61997485482301350969833748360621159286305135448859817314122397991134286237320 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.kmac_burst_write.61997485482301350969833748360621159286305135448859817314122397991134286237320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.98099464619961983566671114820342463551989396086631192518844103803607185355644
Short name T697
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.73 seconds
Started Nov 22 01:54:32 PM PST 23
Finished Nov 22 01:55:46 PM PST 23
Peak memory 226896 kb
Host smart-fafe42c5-990a-4999-8fb5-a29d3219433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98099464619961983566671114820342463551989396086631192518844103803607185355644 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.kmac_entropy_refresh.98099464619961983566671114820342463551989396086631192518844103803607185355644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.44207567047249707669918790517742579241431587308867597317459218890787052646160
Short name T561
Test name
Test status
Simulation time 8615085608 ps
CPU time 131.13 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 01:57:06 PM PST 23
Peak memory 248612 kb
Host smart-32e2a7db-be69-4477-b84a-f95a2c48476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44207567047249707669918790517742579241431587308867597317459218890787052646160 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.kmac_error.44207567047249707669918790517742579241431587308867597317459218890787052646160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.49157272930283573890311807089000369971254950726730235666743377308799022162653
Short name T669
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.13 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 01:54:42 PM PST 23
Peak memory 207532 kb
Host smart-b5e9f1d1-4342-4dc4-b10b-6e42a437fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49157272930283573890311807089000369971254950726730235666743377308799022162653 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.kmac_key_error.49157272930283573890311807089000369971254950726730235666743377308799022162653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.38915128386815884505013537254094054916372516317921709312022214518354956718202
Short name T853
Test name
Test status
Simulation time 58171921 ps
CPU time 1.29 seconds
Started Nov 22 01:54:32 PM PST 23
Finished Nov 22 01:54:34 PM PST 23
Peak memory 215708 kb
Host smart-72661349-4cd2-4c36-9fc3-7a47d7b2ba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38915128386815884505013537254094054916372516317921709312022214518354956718202 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.kmac_lc_escalation.38915128386815884505013537254094054916372516317921709312022214518354956718202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.84351054983867326207921997634775163964060532900922150184565880365933384732023
Short name T570
Test name
Test status
Simulation time 45517522529 ps
CPU time 714.12 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 02:06:44 PM PST 23
Peak memory 288220 kb
Host smart-5e4fb5d6-51cb-444b-891c-e9e4d78a6fed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84351054983867326207921997634775163964060532900922150184565880365933384732023 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.843510549838673262079219976347751639640605329009221501845658803659333
84732023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.58293218695820174289337552474870372778649304211696646489249751160831437852468
Short name T159
Test name
Test status
Simulation time 7733092664 ps
CPU time 113.61 seconds
Started Nov 22 01:54:45 PM PST 23
Finished Nov 22 01:56:39 PM PST 23
Peak memory 228104 kb
Host smart-6723cd39-d722-462b-852e-57f856dc5dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58293218695820174289337552474870372778649304211696646489249751160831437852468 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.kmac_sideload.58293218695820174289337552474870372778649304211696646489249751160831437852468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.62886865218343329692179267489704038577765977410945101477415290527625921008988
Short name T434
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.34 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:55:06 PM PST 23
Peak memory 215848 kb
Host smart-40fa8103-add2-4d2e-a8b6-156dc228fa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62886865218343329692179267489704038577765977410945101477415290527625921008988 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.kmac_smoke.62886865218343329692179267489704038577765977410945101477415290527625921008988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.107287658875597463351731788491001416828946552170893042742724098639521106814644
Short name T440
Test name
Test status
Simulation time 41434001626 ps
CPU time 628.68 seconds
Started Nov 22 01:54:28 PM PST 23
Finished Nov 22 02:04:59 PM PST 23
Peak memory 321732 kb
Host smart-eef960ed-2564-4135-9a18-22acabe425e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=107287658875597463351731788491001416828946552170893042742724098639521106814644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_s
tress_all.107287658875597463351731788491001416828946552170893042742724098639521106814644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.58652008375855267855183221924046019813605673415856299435783474515299346901429
Short name T433
Test name
Test status
Simulation time 298812853 ps
CPU time 4.38 seconds
Started Nov 22 01:54:35 PM PST 23
Finished Nov 22 01:54:40 PM PST 23
Peak memory 215864 kb
Host smart-cf9cee30-521e-4da0-ac27-e71d9fa13463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58652008375855267855183221924046019813605673415856299
435783474515299346901429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac.58652008375855267855183221924046019813
605673415856299435783474515299346901429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.92069929568596234328848169507093294626174344788825754787476702777668542186903
Short name T451
Test name
Test status
Simulation time 289902210 ps
CPU time 4.33 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 01:54:38 PM PST 23
Peak memory 215828 kb
Host smart-4348f1e9-2075-4499-a61a-8f264d8be105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92069929568596234328848169507093294626174344788825754
787476702777668542186903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac_xof.920699295685962343288481695070
93294626174344788825754787476702777668542186903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.30567364370264377936021197421061666582677795312503024543009962189697783496837
Short name T489
Test name
Test status
Simulation time 115269125226 ps
CPU time 1735.2 seconds
Started Nov 22 01:54:31 PM PST 23
Finished Nov 22 02:23:27 PM PST 23
Peak memory 390400 kb
Host smart-ce039212-6a62-4c25-9817-a6b88a2719f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30567364370264377936021197421061666582677795312503024543009962189697783496837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.kmac_test_vectors_sha3_224.30567364370264377936021197421061666582677795312503024543009962189697783496837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.89739114912092377873246654539454387934693242242390025220689531818476978115794
Short name T268
Test name
Test status
Simulation time 107886220004 ps
CPU time 1599.3 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 02:21:18 PM PST 23
Peak memory 370200 kb
Host smart-04f660b5-9616-42a5-a892-6aea13c41bc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89739114912092377873246654539454387934693242242390025220689531818476978115794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.kmac_test_vectors_sha3_256.89739114912092377873246654539454387934693242242390025220689531818476978115794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.75208197237737079816225951865223489362755951026621732175675680871274448190642
Short name T436
Test name
Test status
Simulation time 83070954242 ps
CPU time 1246.14 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 02:15:36 PM PST 23
Peak memory 332904 kb
Host smart-ac2cf312-f15f-4d26-8aea-852e686169de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=75208197237737079816225951865223489362755951026621732175675680871274448190642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.kmac_test_vectors_sha3_384.75208197237737079816225951865223489362755951026621732175675680871274448190642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1238484599428150847405301581492124256373914518132928118008923119611698000978
Short name T719
Test name
Test status
Simulation time 58503507926 ps
CPU time 893.67 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 02:09:43 PM PST 23
Peak memory 295884 kb
Host smart-5540abff-ba07-4183-9e0d-6cbf81310db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1238484599428150847405301581492124256373914518132928118008923119611698000978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
kmac_test_vectors_sha3_512.1238484599428150847405301581492124256373914518132928118008923119611698000978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.112174408896743309793169759672738708015586119528160103362278147670920523604733
Short name T308
Test name
Test status
Simulation time 307766781661 ps
CPU time 4499.58 seconds
Started Nov 22 01:54:35 PM PST 23
Finished Nov 22 03:09:37 PM PST 23
Peak memory 653284 kb
Host smart-481f71ea-e862-4e62-813f-0e2c194d07b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=112174408896743309793169759672738708015586119528160103362278147670920523604733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.kmac_test_vectors_shake_128.112174408896743309793169759672738708015586119528160103362278147670920523604733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.10869357182961251900514694648622677082895890323709347396315624526730427220760
Short name T155
Test name
Test status
Simulation time 258047411562 ps
CPU time 3649.56 seconds
Started Nov 22 01:54:31 PM PST 23
Finished Nov 22 02:55:22 PM PST 23
Peak memory 556320 kb
Host smart-c8a338d0-f11a-4f04-92a5-d93e42af3860
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=10869357182961251900514694648622677082895890323709347396315624526730427220760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.kmac_test_vectors_shake_256.10869357182961251900514694648622677082895890323709347396315624526730427220760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.54461591763143709794088555227732372907131967857275587094558158280530723590465
Short name T824
Test name
Test status
Simulation time 21118646 ps
CPU time 0.79 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:54:53 PM PST 23
Peak memory 205236 kb
Host smart-e79ae2a1-c7e5-4e45-abaa-595067cb4174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54461591763143709794088555227732372907131967857275587094558158280530723590465 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.kmac_alert_test.54461591763143709794088555227732372907131967857275587094558158280530723590465 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.45064230321710485389060330080994900548260425590465299835236631739044532721870
Short name T977
Test name
Test status
Simulation time 5659537824 ps
CPU time 75.63 seconds
Started Nov 22 01:54:29 PM PST 23
Finished Nov 22 01:55:46 PM PST 23
Peak memory 227364 kb
Host smart-74bbdcd2-c50f-4566-a3a6-675753fa2728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45064230321710485389060330080994900548260425590465299835236631739044532721870 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.kmac_app.45064230321710485389060330080994900548260425590465299835236631739044532721870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.18251100865985913151136588232577132918316227143303049914269212020132858763151
Short name T156
Test name
Test status
Simulation time 14812750312 ps
CPU time 248.93 seconds
Started Nov 22 01:54:35 PM PST 23
Finished Nov 22 01:58:45 PM PST 23
Peak memory 225584 kb
Host smart-ddc05c30-5eee-4846-ad4f-f1f25ca3090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18251100865985913151136588232577132918316227143303049914269212020132858763151 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.kmac_burst_write.18251100865985913151136588232577132918316227143303049914269212020132858763151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.91183939560734026249625066205491305160663903582196187565470867270645780580488
Short name T41
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.6 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:56:11 PM PST 23
Peak memory 226820 kb
Host smart-b607ba3a-d1af-4ba9-8e69-3e4ad59e7e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91183939560734026249625066205491305160663903582196187565470867270645780580488 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.kmac_entropy_refresh.91183939560734026249625066205491305160663903582196187565470867270645780580488 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.55315380923513899408691828126923015389145715107828995946167703373824827407425
Short name T656
Test name
Test status
Simulation time 8615085608 ps
CPU time 128.24 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:57:00 PM PST 23
Peak memory 248724 kb
Host smart-e5b97780-cdf6-4522-b788-addac37cfaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55315380923513899408691828126923015389145715107828995946167703373824827407425 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.kmac_error.55315380923513899408691828126923015389145715107828995946167703373824827407425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.54567442288996832248936055394807100596812135008147097031415284517201141253536
Short name T645
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.21 seconds
Started Nov 22 01:54:31 PM PST 23
Finished Nov 22 01:54:37 PM PST 23
Peak memory 207516 kb
Host smart-4a4054f4-0a5a-41c9-ba79-53edfc4a866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54567442288996832248936055394807100596812135008147097031415284517201141253536 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.kmac_key_error.54567442288996832248936055394807100596812135008147097031415284517201141253536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.27753963743006511035371314955539410040753190852506023110376499432944833421802
Short name T369
Test name
Test status
Simulation time 58171921 ps
CPU time 1.21 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 01:54:39 PM PST 23
Peak memory 215728 kb
Host smart-b348ffc1-c805-468d-95d8-4d8fc46b6f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27753963743006511035371314955539410040753190852506023110376499432944833421802 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.kmac_lc_escalation.27753963743006511035371314955539410040753190852506023110376499432944833421802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1722016799152020891456412201730358418180200890568488902241450652564376970323
Short name T947
Test name
Test status
Simulation time 45517522529 ps
CPU time 714.14 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 02:06:31 PM PST 23
Peak memory 288344 kb
Host smart-e4c9bf6b-021d-4e16-9608-645d027e6c44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722016799152020891456412201730358418180200890568488902241450652564376970323 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.1722016799152020891456412201730358418180200890568488902241450652564376
970323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.84072143212954061504479074898765733383497095361081008839626502666266112143866
Short name T743
Test name
Test status
Simulation time 7733092664 ps
CPU time 116.01 seconds
Started Nov 22 01:54:46 PM PST 23
Finished Nov 22 01:56:43 PM PST 23
Peak memory 228160 kb
Host smart-e537c461-dc48-4c87-ba12-9988d7b7f517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84072143212954061504479074898765733383497095361081008839626502666266112143866 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.kmac_sideload.84072143212954061504479074898765733383497095361081008839626502666266112143866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.77543666925516705654475203855166827099803557937440935903057465308187577287794
Short name T129
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.18 seconds
Started Nov 22 01:54:35 PM PST 23
Finished Nov 22 01:54:55 PM PST 23
Peak memory 215948 kb
Host smart-37e421e5-a8eb-4760-bbed-d467f0f11d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77543666925516705654475203855166827099803557937440935903057465308187577287794 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.kmac_smoke.77543666925516705654475203855166827099803557937440935903057465308187577287794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.46570495757510532757869470380795430872067561751849711119962709322565208711441
Short name T397
Test name
Test status
Simulation time 41434001626 ps
CPU time 608.03 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 02:04:46 PM PST 23
Peak memory 321752 kb
Host smart-d8d39b1c-5731-4456-bc48-c04aa3c74c71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=46570495757510532757869470380795430872067561751849711119962709322565208711441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_st
ress_all.46570495757510532757869470380795430872067561751849711119962709322565208711441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.36912582117641520984601562884144402889489586843286351123493934705065041035519
Short name T464
Test name
Test status
Simulation time 298812853 ps
CPU time 4.51 seconds
Started Nov 22 01:54:54 PM PST 23
Finished Nov 22 01:55:00 PM PST 23
Peak memory 215772 kb
Host smart-9e3baaab-4f6c-4e80-9e83-62c58a0528b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36912582117641520984601562884144402889489586843286351
123493934705065041035519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac.36912582117641520984601562884144402889
489586843286351123493934705065041035519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.102647680357161897980599239270612296569560739673910022751827735229869755677666
Short name T741
Test name
Test status
Simulation time 289902210 ps
CPU time 4.15 seconds
Started Nov 22 01:54:35 PM PST 23
Finished Nov 22 01:54:41 PM PST 23
Peak memory 215932 kb
Host smart-c4dbd878-f3ea-4990-93f8-40baffc395b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264768035716189798059923927061229656956073967391002
2751827735229869755677666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.10264768035716189798059923927
0612296569560739673910022751827735229869755677666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.28503441438345782100166306700673037637682343616899647238090180374697139181017
Short name T302
Test name
Test status
Simulation time 115269125226 ps
CPU time 1743.21 seconds
Started Nov 22 01:54:31 PM PST 23
Finished Nov 22 02:23:36 PM PST 23
Peak memory 390396 kb
Host smart-80345079-98f2-4b08-9987-01ab87fdfb61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=28503441438345782100166306700673037637682343616899647238090180374697139181017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.kmac_test_vectors_sha3_224.28503441438345782100166306700673037637682343616899647238090180374697139181017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.22846602816039915229241529094884429860825561970462493675746904567526616926256
Short name T494
Test name
Test status
Simulation time 107886220004 ps
CPU time 1579.61 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 02:20:57 PM PST 23
Peak memory 370140 kb
Host smart-90fbe699-344f-41e7-ad89-b98a43771328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=22846602816039915229241529094884429860825561970462493675746904567526616926256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.kmac_test_vectors_sha3_256.22846602816039915229241529094884429860825561970462493675746904567526616926256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.73618281298047358144268033467367268067135895041278571344607422190240219094686
Short name T871
Test name
Test status
Simulation time 83070954242 ps
CPU time 1201.59 seconds
Started Nov 22 01:54:44 PM PST 23
Finished Nov 22 02:14:47 PM PST 23
Peak memory 332840 kb
Host smart-d76d14d3-ae06-4cbf-a9e0-cb615158de2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=73618281298047358144268033467367268067135895041278571344607422190240219094686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.kmac_test_vectors_sha3_384.73618281298047358144268033467367268067135895041278571344607422190240219094686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.19702450231000719689113875135339111813078850749810030193930785557185638726163
Short name T686
Test name
Test status
Simulation time 58503507926 ps
CPU time 853.23 seconds
Started Nov 22 01:54:46 PM PST 23
Finished Nov 22 02:09:00 PM PST 23
Peak memory 295824 kb
Host smart-7eaf4093-0081-4603-833f-9d854120700b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=19702450231000719689113875135339111813078850749810030193930785557185638726163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.kmac_test_vectors_sha3_512.19702450231000719689113875135339111813078850749810030193930785557185638726163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.73061465187809980572981809293212717479672047641333098164366678672875233844497
Short name T913
Test name
Test status
Simulation time 307766781661 ps
CPU time 4464.71 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 03:09:04 PM PST 23
Peak memory 653116 kb
Host smart-3cdb1ac9-d36f-410a-a0d5-d6a8ac595785
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=73061465187809980572981809293212717479672047641333098164366678672875233844497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.kmac_test_vectors_shake_128.73061465187809980572981809293212717479672047641333098164366678672875233844497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.51029937748879117600250194161214661121223208185719628612711429871761400683918
Short name T912
Test name
Test status
Simulation time 258047411562 ps
CPU time 3853.24 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 02:58:51 PM PST 23
Peak memory 556136 kb
Host smart-51d5cb3f-51d5-41b4-b62e-9d0c34056047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=51029937748879117600250194161214661121223208185719628612711429871761400683918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.kmac_test_vectors_shake_256.51029937748879117600250194161214661121223208185719628612711429871761400683918 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.36888229843001695329384033716342193106415988668579512715878439281500406869915
Short name T614
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:54:52 PM PST 23
Peak memory 205184 kb
Host smart-41c0b937-68d7-4d56-8647-cf3f275ffaa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36888229843001695329384033716342193106415988668579512715878439281500406869915 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.kmac_alert_test.36888229843001695329384033716342193106415988668579512715878439281500406869915 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.75273033860324138601878239143472434801834365582889890626418004613389916894844
Short name T933
Test name
Test status
Simulation time 5659537824 ps
CPU time 69.87 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 01:55:48 PM PST 23
Peak memory 227364 kb
Host smart-c037e492-3c52-44e9-8887-80d5d6e3984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75273033860324138601878239143472434801834365582889890626418004613389916894844 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.kmac_app.75273033860324138601878239143472434801834365582889890626418004613389916894844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.13934254032150468640389642820906372695680848039538527696393620523185813730865
Short name T560
Test name
Test status
Simulation time 14812750312 ps
CPU time 247.56 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 01:58:44 PM PST 23
Peak memory 225404 kb
Host smart-1943fea3-29d8-4556-aeb1-bdeb770ef73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13934254032150468640389642820906372695680848039538527696393620523185813730865 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.kmac_burst_write.13934254032150468640389642820906372695680848039538527696393620523185813730865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.26952313941285181246687806622196401323210817124638967085505462357923718335233
Short name T702
Test name
Test status
Simulation time 6743332725 ps
CPU time 71.35 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:56:00 PM PST 23
Peak memory 227024 kb
Host smart-b683cd7b-b030-48c7-af95-e92a20d47f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26952313941285181246687806622196401323210817124638967085505462357923718335233 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.kmac_entropy_refresh.26952313941285181246687806622196401323210817124638967085505462357923718335233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.17567383138947985445629447774576192414345360060822027266738848970262383934935
Short name T380
Test name
Test status
Simulation time 8615085608 ps
CPU time 126.86 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:56:55 PM PST 23
Peak memory 248520 kb
Host smart-9d7b0791-c674-4ccf-b86a-37a1ac01e106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17567383138947985445629447774576192414345360060822027266738848970262383934935 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.kmac_error.17567383138947985445629447774576192414345360060822027266738848970262383934935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.48929086047150812748575985198453166022077446103771674894909823962726612682300
Short name T726
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.3 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 01:54:39 PM PST 23
Peak memory 207520 kb
Host smart-3c0c5d51-3942-4326-9e80-9770c08eae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48929086047150812748575985198453166022077446103771674894909823962726612682300 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.kmac_key_error.48929086047150812748575985198453166022077446103771674894909823962726612682300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.30354870044703799339068677557836888919147900708918361165610034307026363747608
Short name T954
Test name
Test status
Simulation time 58171921 ps
CPU time 1.22 seconds
Started Nov 22 01:54:34 PM PST 23
Finished Nov 22 01:54:36 PM PST 23
Peak memory 215744 kb
Host smart-5abe8917-62f8-4ba0-8b56-dbcfd788ab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30354870044703799339068677557836888919147900708918361165610034307026363747608 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.kmac_lc_escalation.30354870044703799339068677557836888919147900708918361165610034307026363747608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.80200020168839951537051642889235210791264420293562549668012301172640911406561
Short name T1012
Test name
Test status
Simulation time 45517522529 ps
CPU time 733.07 seconds
Started Nov 22 01:54:34 PM PST 23
Finished Nov 22 02:06:48 PM PST 23
Peak memory 288360 kb
Host smart-96a0e256-2bd4-422a-b697-9f43e8363096
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80200020168839951537051642889235210791264420293562549668012301172640911406561 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.802000201688399515370516428892352107912644202935625496680123011726409
11406561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.47478489769248574197718166798372234278595341608827441802302447353336961703776
Short name T678
Test name
Test status
Simulation time 7733092664 ps
CPU time 105.56 seconds
Started Nov 22 01:54:30 PM PST 23
Finished Nov 22 01:56:17 PM PST 23
Peak memory 228088 kb
Host smart-4847582e-4eb1-44a5-8dbc-f1378b252b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47478489769248574197718166798372234278595341608827441802302447353336961703776 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.kmac_sideload.47478489769248574197718166798372234278595341608827441802302447353336961703776 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.11116954888308005436925356690417881891169880600243054266062861947303904690621
Short name T526
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.53 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 01:55:14 PM PST 23
Peak memory 215916 kb
Host smart-0af26bb9-157a-48f8-b4a4-a64ff6b1bd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11116954888308005436925356690417881891169880600243054266062861947303904690621 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.kmac_smoke.11116954888308005436925356690417881891169880600243054266062861947303904690621 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.13557440859099386406522937508975370203260486056531473503591492381464066971966
Short name T371
Test name
Test status
Simulation time 41434001626 ps
CPU time 633.74 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 02:05:30 PM PST 23
Peak memory 321704 kb
Host smart-6bf43e6c-2140-4a11-87ae-6b827cf54706
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=13557440859099386406522937508975370203260486056531473503591492381464066971966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_st
ress_all.13557440859099386406522937508975370203260486056531473503591492381464066971966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.105734482241938246102789595813849440705478624754420265773783904090476734667764
Short name T948
Test name
Test status
Simulation time 298812853 ps
CPU time 4.45 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 01:54:57 PM PST 23
Peak memory 215828 kb
Host smart-9a71b92b-862a-4e23-9c55-313148227f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10573448224193824610278959581384944070547862475442026
5773783904090476734667764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac.1057344822419382461027895958138494407
05478624754420265773783904090476734667764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.16840809361698137959791804598704536274080356174176407741072124179086280515021
Short name T996
Test name
Test status
Simulation time 289902210 ps
CPU time 4.23 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 01:54:43 PM PST 23
Peak memory 215848 kb
Host smart-309b7986-4d43-4ef0-91e4-096c0134520f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16840809361698137959791804598704536274080356174176407
741072124179086280515021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.168408093616981379597918045987
04536274080356174176407741072124179086280515021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.89770596058310990164906718274835723376957647091090581389709217916738028329666
Short name T540
Test name
Test status
Simulation time 115269125226 ps
CPU time 1767.54 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 02:24:04 PM PST 23
Peak memory 390424 kb
Host smart-bca4dea1-2e7b-47d9-94b1-b7a06432fe35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89770596058310990164906718274835723376957647091090581389709217916738028329666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.kmac_test_vectors_sha3_224.89770596058310990164906718274835723376957647091090581389709217916738028329666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.10227007015440888735160835478036831183506727004770221026274644929770535315521
Short name T319
Test name
Test status
Simulation time 107886220004 ps
CPU time 1621.45 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 02:21:40 PM PST 23
Peak memory 370256 kb
Host smart-64cfbbb1-9b3f-4736-8acf-9c00cf2d4df5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=10227007015440888735160835478036831183506727004770221026274644929770535315521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.kmac_test_vectors_sha3_256.10227007015440888735160835478036831183506727004770221026274644929770535315521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.114963697028335786223135819631564632021609285258941618514957818330765561363635
Short name T926
Test name
Test status
Simulation time 83070954242 ps
CPU time 1260.39 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 02:15:52 PM PST 23
Peak memory 332888 kb
Host smart-1478991b-5212-40b2-b11a-8ab90f6168d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114963697028335786223135819631564632021609285258941618514957818330765561363635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.kmac_test_vectors_sha3_384.114963697028335786223135819631564632021609285258941618514957818330765561363635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.22977103831893487499712987205141463267551675214890199494250093812656844702927
Short name T774
Test name
Test status
Simulation time 58503507926 ps
CPU time 936.99 seconds
Started Nov 22 01:54:32 PM PST 23
Finished Nov 22 02:10:10 PM PST 23
Peak memory 295940 kb
Host smart-fb30e1ad-4f26-4411-873e-9998c2467e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=22977103831893487499712987205141463267551675214890199494250093812656844702927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.kmac_test_vectors_sha3_512.22977103831893487499712987205141463267551675214890199494250093812656844702927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.69033778301125161829643504402604057745799904223262953239824643937698428548549
Short name T818
Test name
Test status
Simulation time 307766781661 ps
CPU time 4497.68 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 03:09:32 PM PST 23
Peak memory 653240 kb
Host smart-dc6db0d7-7fbe-4781-8891-3996fe18c612
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=69033778301125161829643504402604057745799904223262953239824643937698428548549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.kmac_test_vectors_shake_128.69033778301125161829643504402604057745799904223262953239824643937698428548549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.6781942985931939076488078295035855833058836353849826776301657121262290540078
Short name T246
Test name
Test status
Simulation time 258047411562 ps
CPU time 3754.47 seconds
Started Nov 22 01:54:54 PM PST 23
Finished Nov 22 02:57:30 PM PST 23
Peak memory 556300 kb
Host smart-1e5160d2-49e6-47ab-8f08-bdf21c67cceb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=6781942985931939076488078295035855833058836353849826776301657121262290540078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.kmac_test_vectors_shake_256.6781942985931939076488078295035855833058836353849826776301657121262290540078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.56556591272868432665943501999163211540220006435168231946809867485881300201753
Short name T763
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 205128 kb
Host smart-e7cb7275-479f-4d74-8e59-f5dfe39e5328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56556591272868432665943501999163211540220006435168231946809867485881300201753 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.kmac_alert_test.56556591272868432665943501999163211540220006435168231946809867485881300201753 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.64532138181537135377494576724442071162511602224963829324971554199916408711934
Short name T343
Test name
Test status
Simulation time 5659537824 ps
CPU time 78.82 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:56:17 PM PST 23
Peak memory 227352 kb
Host smart-07eb6e0b-3474-4fb1-b98a-77a336d5d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64532138181537135377494576724442071162511602224963829324971554199916408711934 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.kmac_app.64532138181537135377494576724442071162511602224963829324971554199916408711934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.61286136214362486350218687497625872395753421155759590196776412292443648662704
Short name T477
Test name
Test status
Simulation time 14812750312 ps
CPU time 232.12 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:58:50 PM PST 23
Peak memory 225612 kb
Host smart-b4c73dc5-c25f-4efc-ab12-e3e4b1d85a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61286136214362486350218687497625872395753421155759590196776412292443648662704 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.kmac_burst_write.61286136214362486350218687497625872395753421155759590196776412292443648662704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.112376306315966428080252768163912284470643966495317075348401795523467723672828
Short name T801
Test name
Test status
Simulation time 6743332725 ps
CPU time 71.92 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:56:17 PM PST 23
Peak memory 227072 kb
Host smart-5457034b-179e-4495-bc74-b89cd11f4385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112376306315966428080252768163912284470643966495317075348401795523467723672828 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.kmac_entropy_refresh.112376306315966428080252768163912284470643966495317075348401795523467723672828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.50521170766763501894750591709702082562285096720933006542327938539390008033664
Short name T209
Test name
Test status
Simulation time 8615085608 ps
CPU time 127.13 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:57:10 PM PST 23
Peak memory 248628 kb
Host smart-324bb8e7-c2ce-4921-bcbc-6a6df5497f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50521170766763501894750591709702082562285096720933006542327938539390008033664 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.kmac_error.50521170766763501894750591709702082562285096720933006542327938539390008033664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.13840600590898802563622936318441032480277309901521777028807972691899381641851
Short name T749
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.4 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:09 PM PST 23
Peak memory 207324 kb
Host smart-b197ded0-ffde-4e59-a7e1-d1fe74f1f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13840600590898802563622936318441032480277309901521777028807972691899381641851 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.kmac_key_error.13840600590898802563622936318441032480277309901521777028807972691899381641851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.31806694807894008052408052252453929120544588285938733535723760215538669842136
Short name T751
Test name
Test status
Simulation time 58171921 ps
CPU time 1.28 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:00 PM PST 23
Peak memory 215760 kb
Host smart-eb5891d0-f614-40cb-a64b-65589268b5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31806694807894008052408052252453929120544588285938733535723760215538669842136 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.kmac_lc_escalation.31806694807894008052408052252453929120544588285938733535723760215538669842136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.97865208594653905438025218892433013893385314620257899046761365659622851449821
Short name T665
Test name
Test status
Simulation time 45517522529 ps
CPU time 712.07 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 02:06:41 PM PST 23
Peak memory 288284 kb
Host smart-b84d62aa-0206-4b2c-b136-cbf27cfc5ead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97865208594653905438025218892433013893385314620257899046761365659622851449821 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.978652085946539054380252188924330138933853146202578990467613656596228
51449821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.42272068189727787794323162861889819331731453264758422315794757242132394367628
Short name T523
Test name
Test status
Simulation time 7733092664 ps
CPU time 112.55 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 228072 kb
Host smart-d7a7e0a2-6568-445f-925d-9fe60b5dc56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42272068189727787794323162861889819331731453264758422315794757242132394367628 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.kmac_sideload.42272068189727787794323162861889819331731453264758422315794757242132394367628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.80188564724345432730225525903936638002242056659180199450013807705606169881098
Short name T488
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.56 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 01:55:12 PM PST 23
Peak memory 215960 kb
Host smart-bd9769dd-a688-4677-a52b-4c6f12f332c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80188564724345432730225525903936638002242056659180199450013807705606169881098 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.kmac_smoke.80188564724345432730225525903936638002242056659180199450013807705606169881098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.59479586617108059203649158841467233396075992136438705573113826553501850956363
Short name T73
Test name
Test status
Simulation time 41434001626 ps
CPU time 617.93 seconds
Started Nov 22 01:55:04 PM PST 23
Finished Nov 22 02:05:26 PM PST 23
Peak memory 321736 kb
Host smart-77468952-e01f-4687-b553-4f3690b33130
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=59479586617108059203649158841467233396075992136438705573113826553501850956363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_st
ress_all.59479586617108059203649158841467233396075992136438705573113826553501850956363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.100140193676798219686610213908144509994136086971735466774548637711906796137612
Short name T194
Test name
Test status
Simulation time 298812853 ps
CPU time 4.57 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 215752 kb
Host smart-bb71ec44-5fbb-4414-b5eb-fc7293fb1b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10014019367679821968661021390814450999413608697173546
6774548637711906796137612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac.1001401936767982196866102139081445099
94136086971735466774548637711906796137612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.11446292428503050886137290569404516356633463033400510732302691666630109424645
Short name T583
Test name
Test status
Simulation time 289902210 ps
CPU time 3.91 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:06 PM PST 23
Peak memory 215804 kb
Host smart-c3a48193-8d48-495c-a1cb-7de933341462
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11446292428503050886137290569404516356633463033400510
732302691666630109424645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac_xof.114462924285030508861372905694
04516356633463033400510732302691666630109424645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.51948746880681542896546405327716982323231005297185943337317871972004922814004
Short name T899
Test name
Test status
Simulation time 115269125226 ps
CPU time 1750.87 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 02:24:11 PM PST 23
Peak memory 390448 kb
Host smart-e667de2f-2a7e-4360-a8cb-b547cf88a334
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=51948746880681542896546405327716982323231005297185943337317871972004922814004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.kmac_test_vectors_sha3_224.51948746880681542896546405327716982323231005297185943337317871972004922814004 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.61940771898300202063783222368182625159841266487597275397483080795408864336081
Short name T483
Test name
Test status
Simulation time 107886220004 ps
CPU time 1574.62 seconds
Started Nov 22 01:54:46 PM PST 23
Finished Nov 22 02:21:02 PM PST 23
Peak memory 370160 kb
Host smart-f663e39a-2bee-48eb-8074-bec2a34e8aa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=61940771898300202063783222368182625159841266487597275397483080795408864336081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.kmac_test_vectors_sha3_256.61940771898300202063783222368182625159841266487597275397483080795408864336081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.88285041796222696480025574591942106430818500163919348226973998879510644677867
Short name T921
Test name
Test status
Simulation time 83070954242 ps
CPU time 1242.54 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 02:15:37 PM PST 23
Peak memory 332940 kb
Host smart-06def4e9-6b69-4cd2-a4dc-5ac616c60031
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=88285041796222696480025574591942106430818500163919348226973998879510644677867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.kmac_test_vectors_sha3_384.88285041796222696480025574591942106430818500163919348226973998879510644677867 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.73324080012784278568407361445055116064858678298041625493862857918368259588195
Short name T972
Test name
Test status
Simulation time 58503507926 ps
CPU time 861.03 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 02:09:25 PM PST 23
Peak memory 295844 kb
Host smart-1ca610e8-af4e-461e-abcd-fabae14edcf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=73324080012784278568407361445055116064858678298041625493862857918368259588195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.kmac_test_vectors_sha3_512.73324080012784278568407361445055116064858678298041625493862857918368259588195 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.37288874238278876109931543594363725008642648235020892747651486769683301271692
Short name T372
Test name
Test status
Simulation time 307766781661 ps
CPU time 4457.39 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 03:09:19 PM PST 23
Peak memory 653168 kb
Host smart-e00ecdfa-9654-4161-9671-5b25434561ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=37288874238278876109931543594363725008642648235020892747651486769683301271692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.kmac_test_vectors_shake_128.37288874238278876109931543594363725008642648235020892747651486769683301271692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.26129602584432988929033312593692534814722918396610162689904636634374512086896
Short name T210
Test name
Test status
Simulation time 258047411562 ps
CPU time 3784.95 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 02:58:08 PM PST 23
Peak memory 556292 kb
Host smart-210d7bc2-3dc9-4fba-86a6-699856896cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=26129602584432988929033312593692534814722918396610162689904636634374512086896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.kmac_test_vectors_shake_256.26129602584432988929033312593692534814722918396610162689904636634374512086896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.94549221364332168463987371219419006779434812669013742540496803625156742488842
Short name T1010
Test name
Test status
Simulation time 21118646 ps
CPU time 0.71 seconds
Started Nov 22 01:54:45 PM PST 23
Finished Nov 22 01:54:46 PM PST 23
Peak memory 205228 kb
Host smart-84dd5ac1-2692-4e88-b870-40d7d16eeee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94549221364332168463987371219419006779434812669013742540496803625156742488842 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.kmac_alert_test.94549221364332168463987371219419006779434812669013742540496803625156742488842 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.64203344066280153887354344310048534445603491806256303770424278499142800355848
Short name T72
Test name
Test status
Simulation time 5659537824 ps
CPU time 72.97 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:56:01 PM PST 23
Peak memory 227320 kb
Host smart-1254504a-9b97-40d5-aea0-6b9ddf755295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64203344066280153887354344310048534445603491806256303770424278499142800355848 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.kmac_app.64203344066280153887354344310048534445603491806256303770424278499142800355848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.43602464319982408946624624446394173825174021538749426038225628252942280191303
Short name T387
Test name
Test status
Simulation time 14812750312 ps
CPU time 239.05 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:58:59 PM PST 23
Peak memory 225528 kb
Host smart-9da83d5e-8969-4857-be03-b4ccf4d85cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43602464319982408946624624446394173825174021538749426038225628252942280191303 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.kmac_burst_write.43602464319982408946624624446394173825174021538749426038225628252942280191303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.51175499272102490182718462832278742142694959943389247487178761691319767602789
Short name T857
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.5 seconds
Started Nov 22 01:54:42 PM PST 23
Finished Nov 22 01:55:56 PM PST 23
Peak memory 227044 kb
Host smart-dbc192e8-c27c-4207-97d2-1f917a4a254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51175499272102490182718462832278742142694959943389247487178761691319767602789 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.kmac_entropy_refresh.51175499272102490182718462832278742142694959943389247487178761691319767602789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.11916398458042580874924307014889407794347940603675628287981049362110638973922
Short name T238
Test name
Test status
Simulation time 8615085608 ps
CPU time 128.2 seconds
Started Nov 22 01:54:38 PM PST 23
Finished Nov 22 01:56:47 PM PST 23
Peak memory 248732 kb
Host smart-2132ee24-7b0d-4f7d-be0d-f760c7bfe076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11916398458042580874924307014889407794347940603675628287981049362110638973922 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.kmac_error.11916398458042580874924307014889407794347940603675628287981049362110638973922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.8806917810545907393725778580007343248638011450260436926263764108378432561665
Short name T1078
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.25 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 01:54:42 PM PST 23
Peak memory 207484 kb
Host smart-949dbdc9-6aba-41ab-b90f-f42fc217a952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8806917810545907393725778580007343248638011450260436926263764108378432561665 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.kmac_key_error.8806917810545907393725778580007343248638011450260436926263764108378432561665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.78939193879810474911526453681292776793331559148503664132496358355914068540637
Short name T1025
Test name
Test status
Simulation time 58171921 ps
CPU time 1.18 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 01:54:55 PM PST 23
Peak memory 215572 kb
Host smart-f59ad17b-9104-4a13-833c-8105811f21b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78939193879810474911526453681292776793331559148503664132496358355914068540637 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.kmac_lc_escalation.78939193879810474911526453681292776793331559148503664132496358355914068540637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.62220415506925203100714405789294207275269425777785157346537787431332211940843
Short name T322
Test name
Test status
Simulation time 45517522529 ps
CPU time 728.01 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 02:07:01 PM PST 23
Peak memory 288348 kb
Host smart-285340bf-2df0-42ae-8ec8-1f4f970be7e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62220415506925203100714405789294207275269425777785157346537787431332211940843 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.622204155069252031007144057892942072752694257777851573465377874313322
11940843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.106389556196579117023976606648480925707150564839099065142312377824160255515054
Short name T1013
Test name
Test status
Simulation time 7733092664 ps
CPU time 118.83 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 228200 kb
Host smart-c1fbae0d-68af-4528-80f5-5c92c4ca47b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106389556196579117023976606648480925707150564839099065142312377824160255515054 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.kmac_sideload.106389556196579117023976606648480925707150564839099065142312377824160255515054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.109638540237457426718723694799163427175027820564205917283451170066702118408533
Short name T180
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.78 seconds
Started Nov 22 01:54:36 PM PST 23
Finished Nov 22 01:54:56 PM PST 23
Peak memory 216088 kb
Host smart-5296c2ff-0dab-4d5f-92eb-850058f241ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109638540237457426718723694799163427175027820564205917283451170066702118408533 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.kmac_smoke.109638540237457426718723694799163427175027820564205917283451170066702118408533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.5210147051513407691615877678508916222304764740661830505289704188719553120775
Short name T512
Test name
Test status
Simulation time 41434001626 ps
CPU time 620.83 seconds
Started Nov 22 01:54:38 PM PST 23
Finished Nov 22 02:05:00 PM PST 23
Peak memory 321796 kb
Host smart-39e9c2d3-800e-4724-9fa3-8c53eff77851
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=5210147051513407691615877678508916222304764740661830505289704188719553120775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_str
ess_all.5210147051513407691615877678508916222304764740661830505289704188719553120775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.42601457607830022517379046807331606680412980719397328731569308149712973358219
Short name T932
Test name
Test status
Simulation time 298812853 ps
CPU time 4.41 seconds
Started Nov 22 01:54:33 PM PST 23
Finished Nov 22 01:54:38 PM PST 23
Peak memory 215848 kb
Host smart-62f50de7-bf98-4d65-a761-ed4e3e70126a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601457607830022517379046807331606680412980719397328
731569308149712973358219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac.42601457607830022517379046807331606680
412980719397328731569308149712973358219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.17995798155507337520086916722416462815033168428464129989640220219222813112146
Short name T917
Test name
Test status
Simulation time 289902210 ps
CPU time 4.04 seconds
Started Nov 22 01:54:54 PM PST 23
Finished Nov 22 01:55:00 PM PST 23
Peak memory 215764 kb
Host smart-87f5a786-3a38-4f14-8fe1-55d3aca2b9fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995798155507337520086916722416462815033168428464129
989640220219222813112146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.179957981555073375200869167224
16462815033168428464129989640220219222813112146 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.103635541377850505357587473837708447703856267914174885717642606571049055853164
Short name T722
Test name
Test status
Simulation time 115269125226 ps
CPU time 1671.74 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 02:22:49 PM PST 23
Peak memory 390488 kb
Host smart-3a33da10-27a7-4c83-b742-e7b6c66144b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=103635541377850505357587473837708447703856267914174885717642606571049055853164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.kmac_test_vectors_sha3_224.103635541377850505357587473837708447703856267914174885717642606571049055853164 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.21951004467104615235671299475648943846083775670442104941098906775947875378703
Short name T565
Test name
Test status
Simulation time 107886220004 ps
CPU time 1638.09 seconds
Started Nov 22 01:54:40 PM PST 23
Finished Nov 22 02:21:59 PM PST 23
Peak memory 370180 kb
Host smart-6f783fee-8461-471d-8173-d57d3ed4e377
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=21951004467104615235671299475648943846083775670442104941098906775947875378703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.kmac_test_vectors_sha3_256.21951004467104615235671299475648943846083775670442104941098906775947875378703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.57420478102281707566558861489165798030318958629687480693458919649054352828685
Short name T663
Test name
Test status
Simulation time 83070954242 ps
CPU time 1233.91 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 02:15:26 PM PST 23
Peak memory 332792 kb
Host smart-2a44af3d-fc5f-4777-b88e-cab40771c8f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57420478102281707566558861489165798030318958629687480693458919649054352828685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.kmac_test_vectors_sha3_384.57420478102281707566558861489165798030318958629687480693458919649054352828685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.29161836200630325891771467405667955826547682403233297049555198174016590079350
Short name T679
Test name
Test status
Simulation time 58503507926 ps
CPU time 902.23 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 02:09:50 PM PST 23
Peak memory 295928 kb
Host smart-d8692d21-fafd-4a57-baed-ac1146df001c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=29161836200630325891771467405667955826547682403233297049555198174016590079350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.kmac_test_vectors_sha3_512.29161836200630325891771467405667955826547682403233297049555198174016590079350 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.87868787360700246884729471904305293904518261141137921641392026706056915611208
Short name T524
Test name
Test status
Simulation time 307766781661 ps
CPU time 4290.67 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 03:06:23 PM PST 23
Peak memory 653200 kb
Host smart-e1568b75-6c32-4f3e-a269-7424822121ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=87868787360700246884729471904305293904518261141137921641392026706056915611208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.kmac_test_vectors_shake_128.87868787360700246884729471904305293904518261141137921641392026706056915611208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.105066771003710966961787522797047692117807047685289008797695504819658566218148
Short name T659
Test name
Test status
Simulation time 258047411562 ps
CPU time 3596 seconds
Started Nov 22 01:54:35 PM PST 23
Finished Nov 22 02:54:33 PM PST 23
Peak memory 556320 kb
Host smart-3b521869-d426-4692-9d2b-a2c560b4405f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=105066771003710966961787522797047692117807047685289008797695504819658566218148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.kmac_test_vectors_shake_256.105066771003710966961787522797047692117807047685289008797695504819658566218148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.109501445036517656074500500409665365995313102172677765819908259183798425258762
Short name T843
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:54:34 PM PST 23
Finished Nov 22 01:54:36 PM PST 23
Peak memory 205252 kb
Host smart-b78dd88d-a4eb-4c0f-9fbd-14ede1d53ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109501445036517656074500500409665365995313102172677765819908259183798425258762 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.109501445036517656074500500409665365995313102172677765819908259183798425258762 +enable_masking=0
+sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3917344382861180456340501226531654474876511136923025755773620005409995430764
Short name T244
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.36 seconds
Started Nov 22 01:54:34 PM PST 23
Finished Nov 22 01:55:49 PM PST 23
Peak memory 227316 kb
Host smart-70b2bb0b-5cc5-41fa-b2bf-3aabb4862517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917344382861180456340501226531654474876511136923025755773620005409995430764 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.kmac_app.3917344382861180456340501226531654474876511136923025755773620005409995430764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.72000430728876309698536977806636574671759714495673678055176686215009975608574
Short name T81
Test name
Test status
Simulation time 14812750312 ps
CPU time 244.8 seconds
Started Nov 22 01:54:39 PM PST 23
Finished Nov 22 01:58:45 PM PST 23
Peak memory 225564 kb
Host smart-ea8ad745-0050-4ef1-87a4-1c4f6c6e0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72000430728876309698536977806636574671759714495673678055176686215009975608574 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.kmac_burst_write.72000430728876309698536977806636574671759714495673678055176686215009975608574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.90353533110418001176141525830094405624257287960611526018408286574739615483574
Short name T326
Test name
Test status
Simulation time 6743332725 ps
CPU time 75.11 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:56:06 PM PST 23
Peak memory 227000 kb
Host smart-77010445-9ce4-42dd-9e41-64c4abf5570c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90353533110418001176141525830094405624257287960611526018408286574739615483574 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.kmac_entropy_refresh.90353533110418001176141525830094405624257287960611526018408286574739615483574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.58616260929029697551544734927655155305296336008307101255907555578502075657783
Short name T395
Test name
Test status
Simulation time 8615085608 ps
CPU time 136.05 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 01:57:13 PM PST 23
Peak memory 248720 kb
Host smart-711cb6db-01ac-47ee-9f7d-2fd3036fbaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58616260929029697551544734927655155305296336008307101255907555578502075657783 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.kmac_error.58616260929029697551544734927655155305296336008307101255907555578502075657783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.107013221712118565441016320476547390803342579917539176848874081264283970700679
Short name T629
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.21 seconds
Started Nov 22 01:54:39 PM PST 23
Finished Nov 22 01:54:45 PM PST 23
Peak memory 207548 kb
Host smart-afb66de9-a28f-44e4-8c67-614d6675d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107013221712118565441016320476547390803342579917539176848874081264283970700679 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.kmac_key_error.107013221712118565441016320476547390803342579917539176848874081264283970700679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.74166552819540441866551395306966981091454395063570512868999722746286248433369
Short name T415
Test name
Test status
Simulation time 58171921 ps
CPU time 1.21 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:59 PM PST 23
Peak memory 215744 kb
Host smart-78f0d71d-3ec8-43b4-bbe5-e8660c9ce9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74166552819540441866551395306966981091454395063570512868999722746286248433369 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.kmac_lc_escalation.74166552819540441866551395306966981091454395063570512868999722746286248433369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.36547622731446590294530723110469312004782016032410708158136011958040579992234
Short name T348
Test name
Test status
Simulation time 45517522529 ps
CPU time 723.63 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 02:06:57 PM PST 23
Peak memory 288284 kb
Host smart-e0670234-5810-4e39-929a-87ef406ee389
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36547622731446590294530723110469312004782016032410708158136011958040579992234 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.365476227314465902945307231104693120047820160324107081581360119580405
79992234 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.51098033356178722331106522157927246253514504922165384388798678581280729405588
Short name T796
Test name
Test status
Simulation time 7733092664 ps
CPU time 111.1 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:56:38 PM PST 23
Peak memory 228156 kb
Host smart-0427aa71-2c1a-4218-affc-3b0855c666e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51098033356178722331106522157927246253514504922165384388798678581280729405588 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.kmac_sideload.51098033356178722331106522157927246253514504922165384388798678581280729405588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.39183319094063730215119775387595888594140451032042428344559211477579152991967
Short name T631
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.76 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 215952 kb
Host smart-3717dd6a-7bbd-4d7c-8be4-14d57b54cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39183319094063730215119775387595888594140451032042428344559211477579152991967 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.kmac_smoke.39183319094063730215119775387595888594140451032042428344559211477579152991967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.58984357430949329683238376715175354972666143504235063512122642144814611519309
Short name T616
Test name
Test status
Simulation time 41434001626 ps
CPU time 615.3 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 02:05:12 PM PST 23
Peak memory 321712 kb
Host smart-9353e964-6056-40bf-b20c-efb433c08650
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=58984357430949329683238376715175354972666143504235063512122642144814611519309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_st
ress_all.58984357430949329683238376715175354972666143504235063512122642144814611519309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.23811849756695302157919308171651549472936511238616042152698912840374492685338
Short name T247
Test name
Test status
Simulation time 298812853 ps
CPU time 4.35 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:54:55 PM PST 23
Peak memory 215852 kb
Host smart-4595a100-218c-4bb8-85aa-7743b98de664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23811849756695302157919308171651549472936511238616042
152698912840374492685338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac.23811849756695302157919308171651549472
936511238616042152698912840374492685338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.111345892304802024140723478416781759217969647233729592019119600194308988990075
Short name T379
Test name
Test status
Simulation time 289902210 ps
CPU time 4.2 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 01:54:57 PM PST 23
Peak memory 215688 kb
Host smart-24f4213a-3949-4e90-88a4-df5b2b961161
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134589230480202414072347841678175921796964723372959
2019119600194308988990075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.11134589230480202414072347841
6781759217969647233729592019119600194308988990075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.30345275015584152521196974699724637642482700901212061497623174631264250793732
Short name T365
Test name
Test status
Simulation time 115269125226 ps
CPU time 1810.84 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 02:24:48 PM PST 23
Peak memory 390396 kb
Host smart-9cfcac05-6f1a-4655-9740-9b8fb3ec95e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30345275015584152521196974699724637642482700901212061497623174631264250793732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.kmac_test_vectors_sha3_224.30345275015584152521196974699724637642482700901212061497623174631264250793732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.35821799935148029468981109512698281875246838388636966417948049171768861528032
Short name T328
Test name
Test status
Simulation time 107886220004 ps
CPU time 1632.8 seconds
Started Nov 22 01:54:34 PM PST 23
Finished Nov 22 02:21:48 PM PST 23
Peak memory 370132 kb
Host smart-baeb7ec0-171d-4f72-9626-f89d28e289cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=35821799935148029468981109512698281875246838388636966417948049171768861528032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.kmac_test_vectors_sha3_256.35821799935148029468981109512698281875246838388636966417948049171768861528032 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.24058591888239640880070929682485607135197695174424089832122270476641797618168
Short name T589
Test name
Test status
Simulation time 83070954242 ps
CPU time 1275.96 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 02:16:06 PM PST 23
Peak memory 332916 kb
Host smart-fb873871-8959-4799-a437-eea67f0e75e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=24058591888239640880070929682485607135197695174424089832122270476641797618168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.kmac_test_vectors_sha3_384.24058591888239640880070929682485607135197695174424089832122270476641797618168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.97661921422116676066340476874052459646905994428388739451123606548696581302315
Short name T949
Test name
Test status
Simulation time 58503507926 ps
CPU time 844.45 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 02:09:00 PM PST 23
Peak memory 295864 kb
Host smart-c0821a06-bd14-4e26-af45-52edd600ce1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=97661921422116676066340476874052459646905994428388739451123606548696581302315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.kmac_test_vectors_sha3_512.97661921422116676066340476874052459646905994428388739451123606548696581302315 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.98559422020489102240076523726989676743171386988750041446707992504941322716393
Short name T230
Test name
Test status
Simulation time 307766781661 ps
CPU time 4432.05 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 03:08:52 PM PST 23
Peak memory 653216 kb
Host smart-0e191b80-dd71-4896-be44-3ff138b82c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=98559422020489102240076523726989676743171386988750041446707992504941322716393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.kmac_test_vectors_shake_128.98559422020489102240076523726989676743171386988750041446707992504941322716393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.44460750114942258214124349244803094544578792920099481720614223198786074446679
Short name T1016
Test name
Test status
Simulation time 258047411562 ps
CPU time 3837.57 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 02:58:47 PM PST 23
Peak memory 556324 kb
Host smart-1edadbee-21b3-48a5-bec5-00a9a5fe5ad3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=44460750114942258214124349244803094544578792920099481720614223198786074446679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.kmac_test_vectors_shake_256.44460750114942258214124349244803094544578792920099481720614223198786074446679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.34263583801634447961597453057574482131955832018644037949075134637854341318833
Short name T479
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:54:48 PM PST 23
Peak memory 205216 kb
Host smart-4849e4e8-f7aa-4ad0-b27f-d983dceddcdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34263583801634447961597453057574482131955832018644037949075134637854341318833 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.kmac_alert_test.34263583801634447961597453057574482131955832018644037949075134637854341318833 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.72850047128763770618340286132939900428620974894315984226583087754110449646093
Short name T215
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.61 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:56:06 PM PST 23
Peak memory 227204 kb
Host smart-408d6ee6-c031-4230-bf56-4f2adff4bc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72850047128763770618340286132939900428620974894315984226583087754110449646093 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.kmac_app.72850047128763770618340286132939900428620974894315984226583087754110449646093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.93218720266432720654780330314271580189251913327152433240427046668632329896942
Short name T710
Test name
Test status
Simulation time 14812750312 ps
CPU time 241.89 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 01:58:57 PM PST 23
Peak memory 225580 kb
Host smart-4d63ba6d-1115-42d1-be56-038d13d803f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93218720266432720654780330314271580189251913327152433240427046668632329896942 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.kmac_burst_write.93218720266432720654780330314271580189251913327152433240427046668632329896942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.29153966073958272912324742993399048826881736971029661355423044656894504802467
Short name T333
Test name
Test status
Simulation time 6743332725 ps
CPU time 78.18 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 01:56:07 PM PST 23
Peak memory 227024 kb
Host smart-71c25177-203f-4457-8b39-dc4ab7fb3a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29153966073958272912324742993399048826881736971029661355423044656894504802467 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.kmac_entropy_refresh.29153966073958272912324742993399048826881736971029661355423044656894504802467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.7705414242139869224674281412831026665004894710708293725333175078463505652309
Short name T51
Test name
Test status
Simulation time 8615085608 ps
CPU time 127.63 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 248536 kb
Host smart-4313fde3-e6ff-44f1-925f-8b6daebb6dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7705414242139869224674281412831026665004894710708293725333175078463505652309 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.kmac_error.7705414242139869224674281412831026665004894710708293725333175078463505652309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.105546521790546698675101107825509790004012484399995456557735003159427955936959
Short name T613
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.21 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:04 PM PST 23
Peak memory 207480 kb
Host smart-585f9d7e-c891-4f2d-aab8-8c70e00f5c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105546521790546698675101107825509790004012484399995456557735003159427955936959 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.kmac_key_error.105546521790546698675101107825509790004012484399995456557735003159427955936959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.51504377824724650101502301871552460538958974837421151665996071349788349520117
Short name T25
Test name
Test status
Simulation time 58171921 ps
CPU time 1.23 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 215664 kb
Host smart-f4117101-de95-4481-bd8d-b0e523e279e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51504377824724650101502301871552460538958974837421151665996071349788349520117 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.kmac_lc_escalation.51504377824724650101502301871552460538958974837421151665996071349788349520117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.7531263602790919952101109730154823898571793861578273300433914673862164552674
Short name T910
Test name
Test status
Simulation time 45517522529 ps
CPU time 725.96 seconds
Started Nov 22 01:54:39 PM PST 23
Finished Nov 22 02:06:46 PM PST 23
Peak memory 288324 kb
Host smart-7fa80aeb-312f-46b2-88fa-745139ca8819
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7531263602790919952101109730154823898571793861578273300433914673862164552674 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.7531263602790919952101109730154823898571793861578273300433914673862164
552674 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.25123089253834961110596144565130590197855156945234744152326841250330339649920
Short name T903
Test name
Test status
Simulation time 7733092664 ps
CPU time 113.99 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:56:51 PM PST 23
Peak memory 228096 kb
Host smart-73760e91-1d17-4c23-af6d-6a174fd3aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25123089253834961110596144565130590197855156945234744152326841250330339649920 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.kmac_sideload.25123089253834961110596144565130590197855156945234744152326841250330339649920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.72419372315678135718589380554491984829961575994516571262195904031752088851703
Short name T241
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.61 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:55:06 PM PST 23
Peak memory 215920 kb
Host smart-1b3f2265-4606-49eb-a1b7-8b3ca9a92d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72419372315678135718589380554491984829961575994516571262195904031752088851703 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.kmac_smoke.72419372315678135718589380554491984829961575994516571262195904031752088851703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.43422568362443762619064545793107346636844380937799721825188607349801676469135
Short name T822
Test name
Test status
Simulation time 41434001626 ps
CPU time 606.09 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 02:04:59 PM PST 23
Peak memory 321708 kb
Host smart-e87bed38-63a8-4eb6-8643-e31ef5f58281
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=43422568362443762619064545793107346636844380937799721825188607349801676469135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_st
ress_all.43422568362443762619064545793107346636844380937799721825188607349801676469135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.60674003121601675986158522435106689078875165987645754188545720916740120271097
Short name T82
Test name
Test status
Simulation time 298812853 ps
CPU time 4.35 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:04 PM PST 23
Peak memory 215784 kb
Host smart-1f78cd98-620c-483b-9d88-2b4043cf46cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60674003121601675986158522435106689078875165987645754
188545720916740120271097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac.60674003121601675986158522435106689078
875165987645754188545720916740120271097 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.61013303885470155051813233160112854323981939872092570176108471466540749889232
Short name T509
Test name
Test status
Simulation time 289902210 ps
CPU time 4.15 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:54:52 PM PST 23
Peak memory 215764 kb
Host smart-72583d05-5dcd-4659-935e-180ab569c651
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61013303885470155051813233160112854323981939872092570
176108471466540749889232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.610133038854701550518132331601
12854323981939872092570176108471466540749889232 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.83477142946074986553016032306306085159374457155662035698422886785867798324593
Short name T496
Test name
Test status
Simulation time 115269125226 ps
CPU time 1647.85 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 02:22:22 PM PST 23
Peak memory 390332 kb
Host smart-edf0f97b-6422-4e39-9198-34d347e8de14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=83477142946074986553016032306306085159374457155662035698422886785867798324593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.kmac_test_vectors_sha3_224.83477142946074986553016032306306085159374457155662035698422886785867798324593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.46666894766011545335296510800579534621160832213719831760515913170221801627548
Short name T711
Test name
Test status
Simulation time 107886220004 ps
CPU time 1603.81 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 02:21:48 PM PST 23
Peak memory 370148 kb
Host smart-dd1f40b2-4314-4348-9a5c-3e5745dcf988
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=46666894766011545335296510800579534621160832213719831760515913170221801627548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.kmac_test_vectors_sha3_256.46666894766011545335296510800579534621160832213719831760515913170221801627548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.76746476710328809732579810371093260673905498443077750785479632369835038991669
Short name T876
Test name
Test status
Simulation time 83070954242 ps
CPU time 1234.29 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 02:15:39 PM PST 23
Peak memory 332840 kb
Host smart-1832c8fd-f3e3-4410-b822-bc64d5cb4e5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=76746476710328809732579810371093260673905498443077750785479632369835038991669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.kmac_test_vectors_sha3_384.76746476710328809732579810371093260673905498443077750785479632369835038991669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.39078298678097346646774376250230121338932806415487797612116729022810479007285
Short name T776
Test name
Test status
Simulation time 58503507926 ps
CPU time 894.31 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 02:09:45 PM PST 23
Peak memory 295916 kb
Host smart-2cd6091f-088b-4415-b6ac-6c2c7a5fc205
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=39078298678097346646774376250230121338932806415487797612116729022810479007285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.kmac_test_vectors_sha3_512.39078298678097346646774376250230121338932806415487797612116729022810479007285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.4343565558914037037655657118448554745227636911936138049734410938757854784728
Short name T863
Test name
Test status
Simulation time 307766781661 ps
CPU time 4546.92 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 03:10:50 PM PST 23
Peak memory 653164 kb
Host smart-4f6f8ead-bd64-46bb-a98e-da99d6efb6d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4343565558914037037655657118448554745227636911936138049734410938757854784728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.kmac_test_vectors_shake_128.4343565558914037037655657118448554745227636911936138049734410938757854784728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.32625493067136277355026655533395981233931387859394276853009928210709602345461
Short name T405
Test name
Test status
Simulation time 258047411562 ps
CPU time 3631.24 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 02:55:29 PM PST 23
Peak memory 556288 kb
Host smart-c94935f4-0484-4a91-9f2c-1e38732f1edd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=32625493067136277355026655533395981233931387859394276853009928210709602345461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.kmac_test_vectors_shake_256.32625493067136277355026655533395981233931387859394276853009928210709602345461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.78891995090327713856322951727704011506655025640867667768962146903805825805202
Short name T191
Test name
Test status
Simulation time 21118646 ps
CPU time 0.73 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:54:52 PM PST 23
Peak memory 205256 kb
Host smart-a862e7ab-f05b-442a-a7ba-7029808dd1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78891995090327713856322951727704011506655025640867667768962146903805825805202 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.kmac_alert_test.78891995090327713856322951727704011506655025640867667768962146903805825805202 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.104665926291621454101172717900395861528544462955115650368494983127390195077262
Short name T401
Test name
Test status
Simulation time 5659537824 ps
CPU time 74.33 seconds
Started Nov 22 01:54:46 PM PST 23
Finished Nov 22 01:56:01 PM PST 23
Peak memory 227340 kb
Host smart-932e9e1a-67d8-4ea0-9aa7-24a292d611fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104665926291621454101172717900395861528544462955115650368494983127390195077262 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.kmac_app.104665926291621454101172717900395861528544462955115650368494983127390195077262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.26040997214456184654343614571215116582504224680918693322112263117036269976954
Short name T698
Test name
Test status
Simulation time 14812750312 ps
CPU time 243.29 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:58:52 PM PST 23
Peak memory 225584 kb
Host smart-ea6d6b7f-0216-4192-a433-ee7723099859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26040997214456184654343614571215116582504224680918693322112263117036269976954 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.kmac_burst_write.26040997214456184654343614571215116582504224680918693322112263117036269976954 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.59558762188978125910059400493139546790888801025301208666527317514581847184826
Short name T901
Test name
Test status
Simulation time 6743332725 ps
CPU time 72.71 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:56:12 PM PST 23
Peak memory 226944 kb
Host smart-f141cce5-5c58-49d1-aeca-e3ffac9e4ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59558762188978125910059400493139546790888801025301208666527317514581847184826 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.kmac_entropy_refresh.59558762188978125910059400493139546790888801025301208666527317514581847184826 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.46728373412392042876568393309653581762913555597244749390986714157530051513042
Short name T980
Test name
Test status
Simulation time 8615085608 ps
CPU time 134.41 seconds
Started Nov 22 01:54:44 PM PST 23
Finished Nov 22 01:57:00 PM PST 23
Peak memory 248656 kb
Host smart-ca98a627-4cb7-4ec3-8344-8713ad391f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46728373412392042876568393309653581762913555597244749390986714157530051513042 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.kmac_error.46728373412392042876568393309653581762913555597244749390986714157530051513042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.56209751012503953249545883580435542118564275563950320309118107136475084470602
Short name T63
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.22 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:08 PM PST 23
Peak memory 207536 kb
Host smart-97775d93-2264-4694-8de9-04494df21fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56209751012503953249545883580435542118564275563950320309118107136475084470602 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.kmac_key_error.56209751012503953249545883580435542118564275563950320309118107136475084470602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.87978217111912388002634135271532135459434006152684531106669718288029846344781
Short name T623
Test name
Test status
Simulation time 58171921 ps
CPU time 1.26 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 01:54:55 PM PST 23
Peak memory 215760 kb
Host smart-3200f0e7-9ad3-4086-b531-68854690f3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87978217111912388002634135271532135459434006152684531106669718288029846344781 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.kmac_lc_escalation.87978217111912388002634135271532135459434006152684531106669718288029846344781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.65766100801436261185892589808058156940217813195827824155764868936251116607399
Short name T941
Test name
Test status
Simulation time 45517522529 ps
CPU time 698.77 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 02:06:29 PM PST 23
Peak memory 288344 kb
Host smart-5d36fcf1-6316-4943-9f05-63915ca911ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65766100801436261185892589808058156940217813195827824155764868936251116607399 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.657661008014362611858925898080581569402178131958278241557648689362511
16607399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.8836625782132917855009074885850781440280907533317453752843479762150106357326
Short name T1044
Test name
Test status
Simulation time 7733092664 ps
CPU time 113.17 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:56:45 PM PST 23
Peak memory 228124 kb
Host smart-1d81e6ad-7d38-4b3f-8738-68525f6eac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8836625782132917855009074885850781440280907533317453752843479762150106357326 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.kmac_sideload.8836625782132917855009074885850781440280907533317453752843479762150106357326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.93826163824089139056991064949248867336799781006415804303251281991298831663816
Short name T1019
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.98 seconds
Started Nov 22 01:54:37 PM PST 23
Finished Nov 22 01:54:57 PM PST 23
Peak memory 215988 kb
Host smart-2c0307ca-3b4e-4005-b2cf-cd20e216c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93826163824089139056991064949248867336799781006415804303251281991298831663816 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.kmac_smoke.93826163824089139056991064949248867336799781006415804303251281991298831663816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.62953159950522980130843098640434781790304152317102755047748646451717502295606
Short name T229
Test name
Test status
Simulation time 41434001626 ps
CPU time 608.56 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 02:05:06 PM PST 23
Peak memory 321704 kb
Host smart-73fe4021-9519-44e5-a1ef-fc64d4c07ad0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=62953159950522980130843098640434781790304152317102755047748646451717502295606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_st
ress_all.62953159950522980130843098640434781790304152317102755047748646451717502295606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.74874023788825247751223578105777484728938569407915170421812127244888560238398
Short name T1067
Test name
Test status
Simulation time 298812853 ps
CPU time 4.35 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:54:56 PM PST 23
Peak memory 215808 kb
Host smart-f93d60db-314e-47be-9cd6-3f6770dc76a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74874023788825247751223578105777484728938569407915170
421812127244888560238398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac.74874023788825247751223578105777484728
938569407915170421812127244888560238398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.35937887958695150665459200624573649416634575767029401293119877093659823366463
Short name T922
Test name
Test status
Simulation time 289902210 ps
CPU time 4.15 seconds
Started Nov 22 01:54:45 PM PST 23
Finished Nov 22 01:54:50 PM PST 23
Peak memory 215808 kb
Host smart-023e5bea-5044-4fec-9963-69631ffc4962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35937887958695150665459200624573649416634575767029401
293119877093659823366463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.359378879586951506654592006245
73649416634575767029401293119877093659823366463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.21058724844387463943529820188793890831518552084420890192799390493024975728713
Short name T334
Test name
Test status
Simulation time 115269125226 ps
CPU time 1749.12 seconds
Started Nov 22 01:54:39 PM PST 23
Finished Nov 22 02:23:50 PM PST 23
Peak memory 390432 kb
Host smart-1d63f089-9479-4cf7-8f59-4255873e8525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=21058724844387463943529820188793890831518552084420890192799390493024975728713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.kmac_test_vectors_sha3_224.21058724844387463943529820188793890831518552084420890192799390493024975728713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.71618449230502561076049219188590668965871113164265068724910710033889364540095
Short name T1028
Test name
Test status
Simulation time 107886220004 ps
CPU time 1580.25 seconds
Started Nov 22 01:54:54 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 370156 kb
Host smart-d43c3120-fc5f-4c17-9a93-c6c416a1e1c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=71618449230502561076049219188590668965871113164265068724910710033889364540095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.kmac_test_vectors_sha3_256.71618449230502561076049219188590668965871113164265068724910710033889364540095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1119270449410790093947461192274889000851323634806272176024692246775225691460
Short name T964
Test name
Test status
Simulation time 83070954242 ps
CPU time 1286.86 seconds
Started Nov 22 01:54:38 PM PST 23
Finished Nov 22 02:16:06 PM PST 23
Peak memory 333012 kb
Host smart-08d30fc5-dd83-4a03-b705-36671ac28dac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1119270449410790093947461192274889000851323634806272176024692246775225691460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
kmac_test_vectors_sha3_384.1119270449410790093947461192274889000851323634806272176024692246775225691460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.98809841356038095759679437475699473986041690270419615083374029287677772757765
Short name T432
Test name
Test status
Simulation time 58503507926 ps
CPU time 888 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 02:09:38 PM PST 23
Peak memory 296036 kb
Host smart-a913f55f-55f3-49f6-b656-0c8dce3c2b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=98809841356038095759679437475699473986041690270419615083374029287677772757765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.kmac_test_vectors_sha3_512.98809841356038095759679437475699473986041690270419615083374029287677772757765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.113985353842983709367530357371575852569540621779771183826901828430627295216703
Short name T829
Test name
Test status
Simulation time 307766781661 ps
CPU time 4500.35 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 03:09:57 PM PST 23
Peak memory 653248 kb
Host smart-067077d0-72d1-4c8a-a968-e8c57a2f4c10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=113985353842983709367530357371575852569540621779771183826901828430627295216703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.kmac_test_vectors_shake_128.113985353842983709367530357371575852569540621779771183826901828430627295216703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.93400829965343068189907181492281733401794099860949600076086159828429968613754
Short name T148
Test name
Test status
Simulation time 258047411562 ps
CPU time 3759.15 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 02:57:32 PM PST 23
Peak memory 556324 kb
Host smart-f10f2148-5513-48c3-9bd0-76fb3f474ce6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=93400829965343068189907181492281733401794099860949600076086159828429968613754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.kmac_test_vectors_shake_256.93400829965343068189907181492281733401794099860949600076086159828429968613754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.15829041067324488773432468677240785093696207627712449490257847605668877088486
Short name T53
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:58 PM PST 23
Peak memory 205252 kb
Host smart-e63b0568-77e7-41d4-818f-9ac1476b11ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829041067324488773432468677240785093696207627712449490257847605668877088486 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.kmac_alert_test.15829041067324488773432468677240785093696207627712449490257847605668877088486 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.34372523010524328443141837921978951694901706720996197903356109956538464764047
Short name T782
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.02 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:56:21 PM PST 23
Peak memory 227420 kb
Host smart-7f1cf526-d9b7-4d17-a9e3-c792b2372a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34372523010524328443141837921978951694901706720996197903356109956538464764047 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.kmac_app.34372523010524328443141837921978951694901706720996197903356109956538464764047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.9964496069150577145121838761630557484130669314322240267434598368002875842516
Short name T193
Test name
Test status
Simulation time 14812750312 ps
CPU time 244.2 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:59:07 PM PST 23
Peak memory 225532 kb
Host smart-b3af69f2-48cd-4916-b9c8-675111898380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9964496069150577145121838761630557484130669314322240267434598368002875842516 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.kmac_burst_write.9964496069150577145121838761630557484130669314322240267434598368002875842516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.66645666130108013645886025674866525547498378990643506510127543745903441524978
Short name T207
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.9 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 01:56:06 PM PST 23
Peak memory 227004 kb
Host smart-914a4136-a24c-4a95-9191-45767f7caa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66645666130108013645886025674866525547498378990643506510127543745903441524978 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.kmac_entropy_refresh.66645666130108013645886025674866525547498378990643506510127543745903441524978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.59020355966304544512261546081744039899571233291967562527049558035494142106743
Short name T992
Test name
Test status
Simulation time 8615085608 ps
CPU time 126.14 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 01:57:03 PM PST 23
Peak memory 248628 kb
Host smart-78d80de2-741f-4b5e-b90f-9fb12bdb71eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59020355966304544512261546081744039899571233291967562527049558035494142106743 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.kmac_error.59020355966304544512261546081744039899571233291967562527049558035494142106743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.89717121041725714093957760714424048100708086779880612287591326584571929110701
Short name T61
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.21 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 01:54:57 PM PST 23
Peak memory 207544 kb
Host smart-1d8ce8cd-a58f-4387-836c-3e5ad8310dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89717121041725714093957760714424048100708086779880612287591326584571929110701 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.kmac_key_error.89717121041725714093957760714424048100708086779880612287591326584571929110701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.49507256249177804232222585981322467442453728958949436875961744192499334905503
Short name T855
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:59 PM PST 23
Peak memory 215740 kb
Host smart-f8d47b8a-7329-4718-b9ff-29b314f20458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49507256249177804232222585981322467442453728958949436875961744192499334905503 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.kmac_lc_escalation.49507256249177804232222585981322467442453728958949436875961744192499334905503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.94785807819980448947127161569267126288171509832842770963922579023470928463799
Short name T979
Test name
Test status
Simulation time 45517522529 ps
CPU time 725.45 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 02:06:59 PM PST 23
Peak memory 288372 kb
Host smart-6648c989-a57a-41b3-9245-c2eb2b65c5b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94785807819980448947127161569267126288171509832842770963922579023470928463799 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.947858078199804489471271615692671262881715098328427709639225790234709
28463799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.102315834420959451763916691596321688876785857211116984070276207371653496249116
Short name T551
Test name
Test status
Simulation time 7733092664 ps
CPU time 106.49 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:56:47 PM PST 23
Peak memory 228088 kb
Host smart-99330745-5b3f-4f99-9a79-9f0b837e3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102315834420959451763916691596321688876785857211116984070276207371653496249116 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.kmac_sideload.102315834420959451763916691596321688876785857211116984070276207371653496249116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.65546699417384455151938029180689212101336448681824998756184597245628361374749
Short name T366
Test name
Test status
Simulation time 1554463522 ps
CPU time 19.49 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:23 PM PST 23
Peak memory 215956 kb
Host smart-11332684-8bf8-4dec-9d56-02589fb0a281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65546699417384455151938029180689212101336448681824998756184597245628361374749 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.kmac_smoke.65546699417384455151938029180689212101336448681824998756184597245628361374749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.97188991102246294218256458976874367042669767593408686053230073355682956906065
Short name T1043
Test name
Test status
Simulation time 41434001626 ps
CPU time 590.14 seconds
Started Nov 22 01:54:48 PM PST 23
Finished Nov 22 02:04:39 PM PST 23
Peak memory 321732 kb
Host smart-d9c9721e-aa3e-4eda-8104-ae2240a37c42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=97188991102246294218256458976874367042669767593408686053230073355682956906065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_st
ress_all.97188991102246294218256458976874367042669767593408686053230073355682956906065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.37606847723962887021772835180294348870719845298469410308852861165774353026472
Short name T125
Test name
Test status
Simulation time 298812853 ps
CPU time 4.46 seconds
Started Nov 22 01:55:04 PM PST 23
Finished Nov 22 01:55:12 PM PST 23
Peak memory 215844 kb
Host smart-f20ff50b-0dec-4ccc-8da1-a2d3d3d5fe8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606847723962887021772835180294348870719845298469410
308852861165774353026472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac.37606847723962887021772835180294348870
719845298469410308852861165774353026472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.28419275912510111798739309072786711804583826931763929073842698432499525814365
Short name T1034
Test name
Test status
Simulation time 289902210 ps
CPU time 4.31 seconds
Started Nov 22 01:55:02 PM PST 23
Finished Nov 22 01:55:10 PM PST 23
Peak memory 215812 kb
Host smart-eb22dd3a-5d58-4f29-a432-5531052126da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28419275912510111798739309072786711804583826931763929
073842698432499525814365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.284192759125101117987393090727
86711804583826931763929073842698432499525814365 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.95882524840944968412997668426349059278166748121937714483065501021915926665438
Short name T851
Test name
Test status
Simulation time 115269125226 ps
CPU time 1726.16 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 02:23:39 PM PST 23
Peak memory 390476 kb
Host smart-25cffc4e-e133-415d-a7b7-5cc3cbcc58e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=95882524840944968412997668426349059278166748121937714483065501021915926665438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.kmac_test_vectors_sha3_224.95882524840944968412997668426349059278166748121937714483065501021915926665438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.18661957362739309740802115863239004055394897447926649385611623263118316237254
Short name T877
Test name
Test status
Simulation time 107886220004 ps
CPU time 1538.22 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 02:20:41 PM PST 23
Peak memory 370048 kb
Host smart-4e5b094c-e181-4573-86b3-846c4b12ca3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=18661957362739309740802115863239004055394897447926649385611623263118316237254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.kmac_test_vectors_sha3_256.18661957362739309740802115863239004055394897447926649385611623263118316237254 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.10902489103922912992160446058337760092070628036052220680264959245579383024652
Short name T844
Test name
Test status
Simulation time 83070954242 ps
CPU time 1207.4 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 02:15:01 PM PST 23
Peak memory 332916 kb
Host smart-f1f03418-80a9-4533-853e-5e14264c97eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=10902489103922912992160446058337760092070628036052220680264959245579383024652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.kmac_test_vectors_sha3_384.10902489103922912992160446058337760092070628036052220680264959245579383024652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.84270325516919500058266511384742670588490591169149474049303114883042219433743
Short name T1075
Test name
Test status
Simulation time 58503507926 ps
CPU time 887.41 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 02:09:51 PM PST 23
Peak memory 295860 kb
Host smart-db7ffd37-aa1a-4be6-b5be-84702d9f7dd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=84270325516919500058266511384742670588490591169149474049303114883042219433743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.kmac_test_vectors_sha3_512.84270325516919500058266511384742670588490591169149474049303114883042219433743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.7185289460877920055855168296202688135837304518820638313544693120103088069012
Short name T290
Test name
Test status
Simulation time 307766781661 ps
CPU time 4342.84 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 03:07:27 PM PST 23
Peak memory 653016 kb
Host smart-fc458eac-56ea-4487-b4f7-313db2f1e697
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=7185289460877920055855168296202688135837304518820638313544693120103088069012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.kmac_test_vectors_shake_128.7185289460877920055855168296202688135837304518820638313544693120103088069012 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.111240193317513323260006088213588229468138727976173508857407260433407915115914
Short name T603
Test name
Test status
Simulation time 258047411562 ps
CPU time 3694.26 seconds
Started Nov 22 01:55:04 PM PST 23
Finished Nov 22 02:56:42 PM PST 23
Peak memory 556356 kb
Host smart-e1ce3468-4402-4b09-b825-913b2672d1e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=111240193317513323260006088213588229468138727976173508857407260433407915115914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.kmac_test_vectors_shake_256.111240193317513323260006088213588229468138727976173508857407260433407915115914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.76694013980436273023160094371832164172242507782352002080236471567138627303996
Short name T646
Test name
Test status
Simulation time 21118646 ps
CPU time 0.76 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:54:52 PM PST 23
Peak memory 205224 kb
Host smart-65d5a5bb-4f0a-4944-a521-b4b75aef46a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76694013980436273023160094371832164172242507782352002080236471567138627303996 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.kmac_alert_test.76694013980436273023160094371832164172242507782352002080236471567138627303996 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.18322699939048448959001101451519232198221461448221402102307852882218504143138
Short name T174
Test name
Test status
Simulation time 5659537824 ps
CPU time 78.48 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:56:08 PM PST 23
Peak memory 227364 kb
Host smart-c51fa490-bee2-4d28-9f4a-6cebc63f405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18322699939048448959001101451519232198221461448221402102307852882218504143138 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.kmac_app.18322699939048448959001101451519232198221461448221402102307852882218504143138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.30047692480755081103902826739437678784060386213341022484255484513455413116202
Short name T806
Test name
Test status
Simulation time 14812750312 ps
CPU time 238.64 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:58:47 PM PST 23
Peak memory 225528 kb
Host smart-d3c53777-d6a7-49d7-bb2d-87a96d6de3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30047692480755081103902826739437678784060386213341022484255484513455413116202 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.kmac_burst_write.30047692480755081103902826739437678784060386213341022484255484513455413116202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.102635434782543871412587645076184816251404195449009703280637434798262762324238
Short name T888
Test name
Test status
Simulation time 6743332725 ps
CPU time 73.07 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:56:03 PM PST 23
Peak memory 226860 kb
Host smart-19b4f2e8-a66d-4cec-b08b-bb9d189caf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102635434782543871412587645076184816251404195449009703280637434798262762324238 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.kmac_entropy_refresh.102635434782543871412587645076184816251404195449009703280637434798262762324238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.50589723443887786900098699067768291233513690849988635451322437305762091222088
Short name T819
Test name
Test status
Simulation time 8615085608 ps
CPU time 125.24 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 01:56:59 PM PST 23
Peak memory 248524 kb
Host smart-c258a334-bf68-4ef0-a2ae-b641c22b2cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50589723443887786900098699067768291233513690849988635451322437305762091222088 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.kmac_error.50589723443887786900098699067768291233513690849988635451322437305762091222088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.56843549914645655845529151651707139514459553944386998691290001783660994961106
Short name T777
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.31 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:54:53 PM PST 23
Peak memory 207572 kb
Host smart-46bd458c-554c-48a4-841c-50661e402a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56843549914645655845529151651707139514459553944386998691290001783660994961106 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.kmac_key_error.56843549914645655845529151651707139514459553944386998691290001783660994961106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.42596464198236597985300188179188542612312124373474576436420873427366023644469
Short name T171
Test name
Test status
Simulation time 58171921 ps
CPU time 1.21 seconds
Started Nov 22 01:54:44 PM PST 23
Finished Nov 22 01:54:47 PM PST 23
Peak memory 215744 kb
Host smart-e97f048a-9b77-4cd6-a689-342a556c45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42596464198236597985300188179188542612312124373474576436420873427366023644469 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.kmac_lc_escalation.42596464198236597985300188179188542612312124373474576436420873427366023644469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.95804372641774605758102918892537090626537731584421711728275941397914255481961
Short name T847
Test name
Test status
Simulation time 45517522529 ps
CPU time 687.26 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 02:06:18 PM PST 23
Peak memory 288372 kb
Host smart-e5fa0eb6-a466-476c-9dfb-69b8010d4d34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95804372641774605758102918892537090626537731584421711728275941397914255481961 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.958043726417746057581029188925370906265377315844217117282759413979142
55481961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.83078438401137877778512780089687796463356659900248453641162135836041459879924
Short name T529
Test name
Test status
Simulation time 7733092664 ps
CPU time 109.01 seconds
Started Nov 22 01:54:44 PM PST 23
Finished Nov 22 01:56:34 PM PST 23
Peak memory 228164 kb
Host smart-4a14ea6b-53e1-4e11-921f-e9b5cac2cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83078438401137877778512780089687796463356659900248453641162135836041459879924 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.kmac_sideload.83078438401137877778512780089687796463356659900248453641162135836041459879924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.44380922929774628501609502190380715156721825863127819608422008483157115888994
Short name T653
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.75 seconds
Started Nov 22 01:54:43 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 215944 kb
Host smart-0a108d83-e7d1-4198-8682-a58408dbc3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44380922929774628501609502190380715156721825863127819608422008483157115888994 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.kmac_smoke.44380922929774628501609502190380715156721825863127819608422008483157115888994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.28807575188630942739594685922737461256641825025690609683680233978049389165091
Short name T243
Test name
Test status
Simulation time 41434001626 ps
CPU time 593.77 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 02:04:49 PM PST 23
Peak memory 321608 kb
Host smart-8dc49dbf-ec2a-4c28-962f-0f2b356d9707
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=28807575188630942739594685922737461256641825025690609683680233978049389165091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_st
ress_all.28807575188630942739594685922737461256641825025690609683680233978049389165091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.66683254189546339627393848237804243065708448538107485507195139599026226001285
Short name T503
Test name
Test status
Simulation time 298812853 ps
CPU time 4.36 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 215772 kb
Host smart-aa8b81af-0373-4ee0-92fa-39daae6cec7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66683254189546339627393848237804243065708448538107485
507195139599026226001285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac.66683254189546339627393848237804243065
708448538107485507195139599026226001285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.7643461861734231666360142827551205182364775376934499334946771076763533657468
Short name T22
Test name
Test status
Simulation time 289902210 ps
CPU time 4.02 seconds
Started Nov 22 01:54:43 PM PST 23
Finished Nov 22 01:54:48 PM PST 23
Peak memory 215840 kb
Host smart-373dd501-e7fd-48fb-abe0-233ac85be65c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76434618617342316663601428275512051823647753769344993
34946771076763533657468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.7643461861734231666360142827551
205182364775376934499334946771076763533657468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.52614766234120230821636922336943808761524130632677402152709474782866619512108
Short name T166
Test name
Test status
Simulation time 115269125226 ps
CPU time 1754.92 seconds
Started Nov 22 01:54:54 PM PST 23
Finished Nov 22 02:24:11 PM PST 23
Peak memory 390456 kb
Host smart-53559d69-06d7-4b56-9030-863c9cd6c5aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=52614766234120230821636922336943808761524130632677402152709474782866619512108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_224.52614766234120230821636922336943808761524130632677402152709474782866619512108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.50300667261862249425856263385908549471059281391659029707856951401024024605355
Short name T578
Test name
Test status
Simulation time 107886220004 ps
CPU time 1579.47 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 02:21:19 PM PST 23
Peak memory 370124 kb
Host smart-6b24a681-eb5b-4c46-ac69-f37b45a9b03b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=50300667261862249425856263385908549471059281391659029707856951401024024605355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_256.50300667261862249425856263385908549471059281391659029707856951401024024605355 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.22436444855776698411500058240292391519613651911382318787971005884438026702753
Short name T374
Test name
Test status
Simulation time 83070954242 ps
CPU time 1209.88 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 02:15:09 PM PST 23
Peak memory 332696 kb
Host smart-0095c6f8-08ea-4239-998f-dee29c77ef34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=22436444855776698411500058240292391519613651911382318787971005884438026702753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_384.22436444855776698411500058240292391519613651911382318787971005884438026702753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.75392725623850614799346366061325657095867732039587116333548516368346952198531
Short name T649
Test name
Test status
Simulation time 58503507926 ps
CPU time 891.44 seconds
Started Nov 22 01:54:45 PM PST 23
Finished Nov 22 02:09:37 PM PST 23
Peak memory 295824 kb
Host smart-4c8ffcad-67f1-42eb-b8da-5fd179f22d49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=75392725623850614799346366061325657095867732039587116333548516368346952198531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.kmac_test_vectors_sha3_512.75392725623850614799346366061325657095867732039587116333548516368346952198531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.102631061302597867063456731086344007006451291339264875174166743126570034806620
Short name T956
Test name
Test status
Simulation time 307766781661 ps
CPU time 4361.6 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 03:07:35 PM PST 23
Peak memory 653128 kb
Host smart-28c24868-1545-4406-8a9c-9c172f1b400c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=102631061302597867063456731086344007006451291339264875174166743126570034806620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.kmac_test_vectors_shake_128.102631061302597867063456731086344007006451291339264875174166743126570034806620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.4936448362883735059662507256740550865399711817288370841777587504208775177924
Short name T962
Test name
Test status
Simulation time 258047411562 ps
CPU time 3527.55 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 02:53:47 PM PST 23
Peak memory 556268 kb
Host smart-98ecbb30-6829-4a1f-ac74-6d5ce31ac83e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4936448362883735059662507256740550865399711817288370841777587504208775177924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.kmac_test_vectors_shake_256.4936448362883735059662507256740550865399711817288370841777587504208775177924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.77113536303575510017547934223086676069594498110422668736668867125279254112529
Short name T695
Test name
Test status
Simulation time 21118646 ps
CPU time 0.75 seconds
Started Nov 22 01:52:52 PM PST 23
Finished Nov 22 01:52:54 PM PST 23
Peak memory 205100 kb
Host smart-8cb14cde-13ef-44aa-ad9e-35ea3c1cd3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77113536303575510017547934223086676069594498110422668736668867125279254112529 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.kmac_alert_test.77113536303575510017547934223086676069594498110422668736668867125279254112529 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.82280551262044369502318178397054263396361939520089452171869101534722505838331
Short name T681
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.04 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 01:54:10 PM PST 23
Peak memory 227376 kb
Host smart-f3cac7f4-98dd-4a04-a710-5c1da6546e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82280551262044369502318178397054263396361939520089452171869101534722505838331 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.kmac_app.82280551262044369502318178397054263396361939520089452171869101534722505838331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.4963323939567549067597390845416056998863146103892952822290613821794439766525
Short name T600
Test name
Test status
Simulation time 7615861459 ps
CPU time 84.08 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:54:12 PM PST 23
Peak memory 226016 kb
Host smart-74eca7a7-f1fb-4e64-b173-a674fb23b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4963323939567549067597390845416056998863146103892952822290613821794439766525 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.kmac_app_with_partial_data.4963323939567549067597390845416056998863146103892952822290613821794439766525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.65450523977389401475191254676848706434709599001924665682443881756801559516495
Short name T692
Test name
Test status
Simulation time 14812750312 ps
CPU time 236.34 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 01:57:18 PM PST 23
Peak memory 225348 kb
Host smart-9517af5a-a602-492e-86cf-cb33231c2045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65450523977389401475191254676848706434709599001924665682443881756801559516495 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.kmac_burst_write.65450523977389401475191254676848706434709599001924665682443881756801559516495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.61727128173463931589304591733396527337875549528786450887167499968947955877871
Short name T368
Test name
Test status
Simulation time 2342046507 ps
CPU time 34.3 seconds
Started Nov 22 01:52:56 PM PST 23
Finished Nov 22 01:53:31 PM PST 23
Peak memory 223928 kb
Host smart-7634d3bd-b9f7-4046-9a80-ed090841d82b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=61727128173463931589304591733396527337875549528786450887167499968947955877871 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.kmac_edn_timeout_error.61727128173463931589304591733396527337875549528786450887167499968947955877871 +enable_masking=0
+sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.27890329465544218956308655404305252469343359678762697886053337666751627248998
Short name T152
Test name
Test status
Simulation time 2211297553 ps
CPU time 29.91 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 223904 kb
Host smart-13fe4ad5-2663-43e0-ab25-85442197b480
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=27890329465544218956308655404305252469343359678762697886053337666751627248998 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.27890329465544218956308655404305252469343359678762697886053337666751627248998 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.110800927707927487019228545539908099272850425658744025371575601975196195405461
Short name T820
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.2 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:53:06 PM PST 23
Peak memory 216888 kb
Host smart-00662c08-e7fd-4e4e-bd67-61b2ca1cd64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110800927707927487019228545539908099272850425658744025371575601975196195405461 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.kmac_entropy_ready_error.110800927707927487019228545539908099272850425658744025371575601975196195405461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.42691153812265206522553262881247838293107286750992036951134568510476187592483
Short name T1006
Test name
Test status
Simulation time 6743332725 ps
CPU time 74.55 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 227124 kb
Host smart-237451a2-3aa5-467e-a2b3-354d806ded0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42691153812265206522553262881247838293107286750992036951134568510476187592483 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.kmac_entropy_refresh.42691153812265206522553262881247838293107286750992036951134568510476187592483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.21467061255634192368405565707357397732209121669828130172907966625104013768193
Short name T314
Test name
Test status
Simulation time 8615085608 ps
CPU time 124.96 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:54:52 PM PST 23
Peak memory 248112 kb
Host smart-28053b3e-6d7f-4547-ade6-e84695c434ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21467061255634192368405565707357397732209121669828130172907966625104013768193 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.kmac_error.21467061255634192368405565707357397732209121669828130172907966625104013768193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.97383887685617779800876939932945366577081744453830269197868252564158177074323
Short name T859
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.19 seconds
Started Nov 22 01:52:52 PM PST 23
Finished Nov 22 01:52:59 PM PST 23
Peak memory 207504 kb
Host smart-35a711ce-efff-493b-b1b3-9079ea98a0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97383887685617779800876939932945366577081744453830269197868252564158177074323 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.kmac_key_error.97383887685617779800876939932945366577081744453830269197868252564158177074323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.16972634853841069058516431655869205185090378216783756747945888608160817205692
Short name T584
Test name
Test status
Simulation time 58171921 ps
CPU time 1.26 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:52:47 PM PST 23
Peak memory 215752 kb
Host smart-680cb8f8-c267-4d8a-928f-3f3ccbccf97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16972634853841069058516431655869205185090378216783756747945888608160817205692 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.kmac_lc_escalation.16972634853841069058516431655869205185090378216783756747945888608160817205692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.80377276547860037401918115160104021616287779109922426295395221338604762423445
Short name T896
Test name
Test status
Simulation time 45517522529 ps
CPU time 705.39 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 02:04:40 PM PST 23
Peak memory 288296 kb
Host smart-ccec7aaf-189f-47bb-850f-b727336714f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80377276547860037401918115160104021616287779109922426295395221338604762423445 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.8037727654786003740191811516010402161628777910992242629539522133860476
2423445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.49629210992641723441963713911391380068977526811827137135189668086063434141670
Short name T295
Test name
Test status
Simulation time 5640716546 ps
CPU time 74.83 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 01:54:08 PM PST 23
Peak memory 227696 kb
Host smart-c59a70ac-6f3d-4d9a-a04d-b4fb12aa149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49629210992641723441963713911391380068977526811827137135189668086063434141670 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.kmac_mubi.49629210992641723441963713911391380068977526811827137135189668086063434141670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.60294650571544665174213611290181487627540431026164491191213182051049680966586
Short name T202
Test name
Test status
Simulation time 7733092664 ps
CPU time 115.65 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 01:55:14 PM PST 23
Peak memory 228148 kb
Host smart-bafa5efc-9da6-4d3f-9ce9-31ba9e5fa4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60294650571544665174213611290181487627540431026164491191213182051049680966586 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.kmac_sideload.60294650571544665174213611290181487627540431026164491191213182051049680966586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.95115168138175275077055696138504335205481752493586171938786812842396753646635
Short name T138
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.85 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 01:53:43 PM PST 23
Peak memory 215956 kb
Host smart-961103a3-d890-4dbf-a675-86b7ef5f070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95115168138175275077055696138504335205481752493586171938786812842396753646635 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.kmac_smoke.95115168138175275077055696138504335205481752493586171938786812842396753646635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.8863985070227833522095493470363204343586494331944704358332840396308527530958
Short name T497
Test name
Test status
Simulation time 41434001626 ps
CPU time 618.14 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 02:03:11 PM PST 23
Peak memory 321224 kb
Host smart-8dd7d8d9-a57b-424b-b173-dc9690859477
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=8863985070227833522095493470363204343586494331944704358332840396308527530958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stre
ss_all.8863985070227833522095493470363204343586494331944704358332840396308527530958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.55960311686847582882376510606627346028319635636780160619530492248213496920927
Short name T842
Test name
Test status
Simulation time 298812853 ps
CPU time 4.26 seconds
Started Nov 22 01:52:46 PM PST 23
Finished Nov 22 01:52:54 PM PST 23
Peak memory 215672 kb
Host smart-3ac80295-6888-461f-b9cc-a0ffe45f3227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55960311686847582882376510606627346028319635636780160
619530492248213496920927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac.559603116868475828823765106066273460283
19635636780160619530492248213496920927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.29899134664523083679082714422481299145329543098779116047880713515660513607987
Short name T775
Test name
Test status
Simulation time 289902210 ps
CPU time 4.07 seconds
Started Nov 22 01:52:54 PM PST 23
Finished Nov 22 01:53:00 PM PST 23
Peak memory 215848 kb
Host smart-a574e1c7-ff9d-4ac8-8698-e60e83daace4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899134664523083679082714422481299145329543098779116
047880713515660513607987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2989913466452308367908271442248
1299145329543098779116047880713515660513607987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.41393024915740163414282640375818859544393121469183087930504968216960176841324
Short name T1047
Test name
Test status
Simulation time 115269125226 ps
CPU time 1691.78 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 02:21:00 PM PST 23
Peak memory 390508 kb
Host smart-842f1f87-fb58-4338-bb29-7e779fcfa4d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=41393024915740163414282640375818859544393121469183087930504968216960176841324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
kmac_test_vectors_sha3_224.41393024915740163414282640375818859544393121469183087930504968216960176841324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.56859996019736955781521266747593848254940579905757030794484015571299435919005
Short name T944
Test name
Test status
Simulation time 107886220004 ps
CPU time 1609.2 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 02:19:42 PM PST 23
Peak memory 370096 kb
Host smart-92530c9b-720d-4eb9-8fa6-cc559d2636da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=56859996019736955781521266747593848254940579905757030794484015571299435919005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
kmac_test_vectors_sha3_256.56859996019736955781521266747593848254940579905757030794484015571299435919005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.26671727692709813232812718493680988877972906393636334783623789458335092504060
Short name T352
Test name
Test status
Simulation time 83070954242 ps
CPU time 1233.97 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 02:13:23 PM PST 23
Peak memory 332828 kb
Host smart-99524408-33c1-494e-aaf9-c6f6174a0b59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=26671727692709813232812718493680988877972906393636334783623789458335092504060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
kmac_test_vectors_sha3_384.26671727692709813232812718493680988877972906393636334783623789458335092504060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.3265240963143323397598463603041476839999842427344242659694680373024706608848
Short name T752
Test name
Test status
Simulation time 58503507926 ps
CPU time 902.59 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 02:07:51 PM PST 23
Peak memory 295864 kb
Host smart-22e4c0f1-1978-4110-a8c3-1a1c7099c998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3265240963143323397598463603041476839999842427344242659694680373024706608848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.k
mac_test_vectors_sha3_512.3265240963143323397598463603041476839999842427344242659694680373024706608848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.48649210390328301991318470957942587452100090739280814438991133347028816270152
Short name T158
Test name
Test status
Simulation time 307766781661 ps
CPU time 4354.96 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 03:05:27 PM PST 23
Peak memory 653236 kb
Host smart-e5a78fe1-c9e7-4e40-ae42-900c0bbe30f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=48649210390328301991318470957942587452100090739280814438991133347028816270152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.kmac_test_vectors_shake_128.48649210390328301991318470957942587452100090739280814438991133347028816270152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.104708708240864475683066004689561635898447144286239156038353052851914396224718
Short name T321
Test name
Test status
Simulation time 258047411562 ps
CPU time 3768.48 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 02:55:41 PM PST 23
Peak memory 556176 kb
Host smart-d65ccc14-be41-4fab-a8bd-348799d35277
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=104708708240864475683066004689561635898447144286239156038353052851914396224718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.kmac_test_vectors_shake_256.104708708240864475683066004689561635898447144286239156038353052851914396224718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.11135864443874493546355675419035748029897264125412658698724548430949897879911
Short name T170
Test name
Test status
Simulation time 21118646 ps
CPU time 0.72 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:52:53 PM PST 23
Peak memory 205248 kb
Host smart-73e239de-602e-423a-8f1e-3bd8de5f73bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135864443874493546355675419035748029897264125412658698724548430949897879911 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.kmac_alert_test.11135864443874493546355675419035748029897264125412658698724548430949897879911 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.45558554643561990345427049808199688634832155485481086366379345894838192076268
Short name T223
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.08 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:54:06 PM PST 23
Peak memory 227252 kb
Host smart-2f939d9e-1e79-4c97-b678-35f190c2871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45558554643561990345427049808199688634832155485481086366379345894838192076268 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.kmac_app.45558554643561990345427049808199688634832155485481086366379345894838192076268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.76790870565419488267413607573306779007802190737875047301719753843492363998388
Short name T288
Test name
Test status
Simulation time 7615861459 ps
CPU time 82.98 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:54:15 PM PST 23
Peak memory 225980 kb
Host smart-ea5408f3-be19-4d06-b718-404522a5d530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76790870565419488267413607573306779007802190737875047301719753843492363998388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_app_with_partial_data.76790870565419488267413607573306779007802190737875047301719753843492363998388 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.25784005120844930273749099689035911135770395996053713299929006396729851426099
Short name T641
Test name
Test status
Simulation time 14812750312 ps
CPU time 247.93 seconds
Started Nov 22 01:52:51 PM PST 23
Finished Nov 22 01:57:01 PM PST 23
Peak memory 225616 kb
Host smart-a83dfc0b-7541-45ce-a7b3-18d3640709dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25784005120844930273749099689035911135770395996053713299929006396729851426099 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.kmac_burst_write.25784005120844930273749099689035911135770395996053713299929006396729851426099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.109883267056356586854206240803149623341177902044883501391210435595679710649424
Short name T1040
Test name
Test status
Simulation time 2342046507 ps
CPU time 32.93 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:53:25 PM PST 23
Peak memory 223848 kb
Host smart-13b544b2-2eac-4112-8c5c-5ca5db01ad14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=109883267056356586854206240803149623341177902044883501391210435595679710649424 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.109883267056356586854206240803149623341177902044883501391210435595679710649424 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.71580376247842628582553697385978943907065749540247938123680050340922802234690
Short name T187
Test name
Test status
Simulation time 2211297553 ps
CPU time 29.76 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:53:21 PM PST 23
Peak memory 223908 kb
Host smart-e4b35553-cf1f-48c4-bded-aa117200a931
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=71580376247842628582553697385978943907065749540247938123680050340922802234690 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.71580376247842628582553697385978943907065749540247938123680050340922802234690 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.36775986274242039235300932922174682733702184283568543380799043371936983648050
Short name T119
Test name
Test status
Simulation time 2782989408 ps
CPU time 17.97 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:53:04 PM PST 23
Peak memory 216940 kb
Host smart-6ee199db-c829-4468-a8bd-1b8b03725e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36775986274242039235300932922174682733702184283568543380799043371936983648050 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.kmac_entropy_ready_error.36775986274242039235300932922174682733702184283568543380799043371936983648050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.54770676150346746191036150396087542215722128253940589019244495511003499395881
Short name T636
Test name
Test status
Simulation time 6743332725 ps
CPU time 75.3 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:54:03 PM PST 23
Peak memory 226984 kb
Host smart-bb437edc-fa2d-4222-9767-4a18340ad46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54770676150346746191036150396087542215722128253940589019244495511003499395881 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.kmac_entropy_refresh.54770676150346746191036150396087542215722128253940589019244495511003499395881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.33680718832853333413819913881931708951440100426858716995926447262246517901813
Short name T373
Test name
Test status
Simulation time 8615085608 ps
CPU time 133.2 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 248508 kb
Host smart-5e8b1be8-9eb6-4eb7-a9fa-26b8cd0dea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33680718832853333413819913881931708951440100426858716995926447262246517901813 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.kmac_error.33680718832853333413819913881931708951440100426858716995926447262246517901813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.112520307239496228172949016458716547839273852147809261094911844303956034616085
Short name T38
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.34 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:52:52 PM PST 23
Peak memory 207532 kb
Host smart-da0cdb31-dd55-4331-b1a6-1410c3a48aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112520307239496228172949016458716547839273852147809261094911844303956034616085 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.kmac_key_error.112520307239496228172949016458716547839273852147809261094911844303956034616085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.85654936317117197540084040155958460141616839265879442611800334532912465569578
Short name T1017
Test name
Test status
Simulation time 58171921 ps
CPU time 1.27 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:52:52 PM PST 23
Peak memory 215716 kb
Host smart-33a3a6c6-b271-4913-a5a9-325682fb39c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85654936317117197540084040155958460141616839265879442611800334532912465569578 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.kmac_lc_escalation.85654936317117197540084040155958460141616839265879442611800334532912465569578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.26293973754213820888074861215973174404760732564294395777534064672833981244576
Short name T470
Test name
Test status
Simulation time 45517522529 ps
CPU time 714.92 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 02:04:41 PM PST 23
Peak memory 288268 kb
Host smart-c5030ced-5b3d-4431-be40-3c35f43a0813
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26293973754213820888074861215973174404760732564294395777534064672833981244576 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2629397375421382088807486121597317440476073256429439577753406467283398
1244576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.10756809041784812984999293659181329480210999555348163967157259624222282398286
Short name T880
Test name
Test status
Simulation time 5640716546 ps
CPU time 71.71 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 01:54:00 PM PST 23
Peak memory 227636 kb
Host smart-36db4cbe-fad5-4f7a-b38f-5ec50137a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10756809041784812984999293659181329480210999555348163967157259624222282398286 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.kmac_mubi.10756809041784812984999293659181329480210999555348163967157259624222282398286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.11178449383375385719631519792804711241491366401928207994965630364949678177228
Short name T828
Test name
Test status
Simulation time 7733092664 ps
CPU time 105.01 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 01:54:38 PM PST 23
Peak memory 228052 kb
Host smart-5c5bdf9d-afee-423d-bae4-3055cf7b414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11178449383375385719631519792804711241491366401928207994965630364949678177228 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.kmac_sideload.11178449383375385719631519792804711241491366401928207994965630364949678177228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.103709118995450948851832212839026902590148267720376865136270201796496396090877
Short name T161
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.55 seconds
Started Nov 22 01:52:38 PM PST 23
Finished Nov 22 01:53:03 PM PST 23
Peak memory 215908 kb
Host smart-d5accccb-b81c-4cff-bbdc-201ca47d8984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103709118995450948851832212839026902590148267720376865136270201796496396090877 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.kmac_smoke.103709118995450948851832212839026902590148267720376865136270201796496396090877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.92382788691254831071397445495432616568796116876816385847325929481390902078690
Short name T813
Test name
Test status
Simulation time 41434001626 ps
CPU time 607.69 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 02:03:00 PM PST 23
Peak memory 321696 kb
Host smart-ee2437ef-15be-4393-b5f1-9deff6b29ff8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=92382788691254831071397445495432616568796116876816385847325929481390902078690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_str
ess_all.92382788691254831071397445495432616568796116876816385847325929481390902078690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.44183088222307638028891020946864682362807875790283939499553270736320271012392
Short name T575
Test name
Test status
Simulation time 298812853 ps
CPU time 4.44 seconds
Started Nov 22 01:52:43 PM PST 23
Finished Nov 22 01:52:52 PM PST 23
Peak memory 215712 kb
Host smart-9384bfe7-f997-4fc8-8cff-e7ecb9308925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44183088222307638028891020946864682362807875790283939
499553270736320271012392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac.441830882223076380288910209468646823628
07875790283939499553270736320271012392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.109341326283687817505355473134165443273870641041002685834489107107486554449908
Short name T729
Test name
Test status
Simulation time 289902210 ps
CPU time 4.26 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:52:56 PM PST 23
Peak memory 215908 kb
Host smart-ed68c2cc-7e93-4ba4-a824-94bc3b543f01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10934132628368781750535547313416544327387064104100268
5834489107107486554449908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.109341326283687817505355473134
165443273870641041002685834489107107486554449908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.11094051701459215153413341043243043548233976624862743420333129433210539758956
Short name T786
Test name
Test status
Simulation time 115269125226 ps
CPU time 1727.6 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 02:21:39 PM PST 23
Peak memory 390428 kb
Host smart-9d0483da-d4e1-4058-ab43-c0c399be9858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11094051701459215153413341043243043548233976624862743420333129433210539758956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
kmac_test_vectors_sha3_224.11094051701459215153413341043243043548233976624862743420333129433210539758956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.14359667137195218761965402463480027915411781290079971586699179671000944154881
Short name T198
Test name
Test status
Simulation time 107886220004 ps
CPU time 1663.24 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 02:20:36 PM PST 23
Peak memory 370104 kb
Host smart-aa4778a6-02c9-4a4b-9439-bbe957217da1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=14359667137195218761965402463480027915411781290079971586699179671000944154881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
kmac_test_vectors_sha3_256.14359667137195218761965402463480027915411781290079971586699179671000944154881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.14074343767331355856849734125102103447926695224094630429550293642956105697333
Short name T465
Test name
Test status
Simulation time 83070954242 ps
CPU time 1250 seconds
Started Nov 22 01:52:44 PM PST 23
Finished Nov 22 02:13:38 PM PST 23
Peak memory 332920 kb
Host smart-cacf3257-75ab-4bb2-9924-e26f20d37a77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=14074343767331355856849734125102103447926695224094630429550293642956105697333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
kmac_test_vectors_sha3_384.14074343767331355856849734125102103447926695224094630429550293642956105697333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.113813954662403286035652220137339261013455527567423756253112569812299026312151
Short name T699
Test name
Test status
Simulation time 58503507926 ps
CPU time 896.76 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 02:07:49 PM PST 23
Peak memory 295876 kb
Host smart-836aee43-67a3-44d8-8b82-e3d17766a7d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=113813954662403286035652220137339261013455527567423756253112569812299026312151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.kmac_test_vectors_sha3_512.113813954662403286035652220137339261013455527567423756253112569812299026312151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.46881242187870586200228664155121820578508069147940701371764082895852870877264
Short name T639
Test name
Test status
Simulation time 307766781661 ps
CPU time 4390.49 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 03:06:03 PM PST 23
Peak memory 653160 kb
Host smart-87b7d7e4-275c-4ff4-8bc1-970bc8be6a1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=46881242187870586200228664155121820578508069147940701371764082895852870877264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.kmac_test_vectors_shake_128.46881242187870586200228664155121820578508069147940701371764082895852870877264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.88603398573490155759334641594139934246930113497097188794792870514107412197366
Short name T861
Test name
Test status
Simulation time 258047411562 ps
CPU time 3640.07 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 02:53:27 PM PST 23
Peak memory 556248 kb
Host smart-644bb460-6481-4abf-86b6-403c000c6569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=88603398573490155759334641594139934246930113497097188794792870514107412197366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.kmac_test_vectors_shake_256.88603398573490155759334641594139934246930113497097188794792870514107412197366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.84951754067746134403105664934626990982974785295763487833604152844941155070689
Short name T222
Test name
Test status
Simulation time 21118646 ps
CPU time 0.76 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:52:50 PM PST 23
Peak memory 205268 kb
Host smart-2a5671e2-97c2-4912-86f9-d76268eb8934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84951754067746134403105664934626990982974785295763487833604152844941155070689 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.kmac_alert_test.84951754067746134403105664934626990982974785295763487833604152844941155070689 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.22597977512169551925917723619627027348919875345047159593623846690129204286468
Short name T455
Test name
Test status
Simulation time 5659537824 ps
CPU time 77.7 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:54:09 PM PST 23
Peak memory 227328 kb
Host smart-cc7ca93a-28f5-48ce-ac2e-ae9e281936af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22597977512169551925917723619627027348919875345047159593623846690129204286468 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.kmac_app.22597977512169551925917723619627027348919875345047159593623846690129204286468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.102074179514194318138075503139155549131768865358441313782530485912739982140475
Short name T1079
Test name
Test status
Simulation time 7615861459 ps
CPU time 84.06 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:54:16 PM PST 23
Peak memory 225988 kb
Host smart-7e648e1b-f15b-42fd-a641-49a031794204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102074179514194318138075503139155549131768865358441313782530485912739982140475 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_app_with_partial_data.102074179514194318138075503139155549131768865358441313782530485912739982140475 +enable_masking=0
+sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.47228797925641868277577691699569180191712932763831148968543488689181670566858
Short name T1030
Test name
Test status
Simulation time 14812750312 ps
CPU time 244.56 seconds
Started Nov 22 01:52:39 PM PST 23
Finished Nov 22 01:56:49 PM PST 23
Peak memory 225540 kb
Host smart-99186a3e-d9c8-448f-9b65-e8528f0c95a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47228797925641868277577691699569180191712932763831148968543488689181670566858 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.kmac_burst_write.47228797925641868277577691699569180191712932763831148968543488689181670566858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.64836961929369306921672153998143249769520937785142243467611239542727596483566
Short name T971
Test name
Test status
Simulation time 2342046507 ps
CPU time 35.19 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:53:28 PM PST 23
Peak memory 223816 kb
Host smart-6d7d1036-0f91-48b9-a824-77fb23bc7f08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=64836961929369306921672153998143249769520937785142243467611239542727596483566 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.kmac_edn_timeout_error.64836961929369306921672153998143249769520937785142243467611239542727596483566 +enable_masking=0
+sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.5581590703045833531845133211605082108323473394902552114180594595034822748443
Short name T1066
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.17 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:53:22 PM PST 23
Peak memory 223880 kb
Host smart-74e045c4-c48c-4409-b395-36a8012ad519
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=5581590703045833531845133211605082108323473394902552114180594595034822748443 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.kmac_entropy_mode_error.5581590703045833531845133211605082108323473394902552114180594595034822748443 +enable_masking=0
+sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.50408959777788876377457707096157054312457659366749309105601982021509017760213
Short name T382
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.3 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 01:53:11 PM PST 23
Peak memory 216952 kb
Host smart-cf9b6a0f-a3a3-44a7-93d8-6d917967c0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50408959777788876377457707096157054312457659366749309105601982021509017760213 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.kmac_entropy_ready_error.50408959777788876377457707096157054312457659366749309105601982021509017760213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.75051234942851179391340362871642459458888982567884856251309513296254920942823
Short name T1011
Test name
Test status
Simulation time 6743332725 ps
CPU time 75.77 seconds
Started Nov 22 01:52:58 PM PST 23
Finished Nov 22 01:54:15 PM PST 23
Peak memory 226860 kb
Host smart-67b56d6a-71dc-489d-ac42-3df52790a382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75051234942851179391340362871642459458888982567884856251309513296254920942823 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.kmac_entropy_refresh.75051234942851179391340362871642459458888982567884856251309513296254920942823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.108280571261438688190728828001596029199791701992617298515965707773599207992259
Short name T707
Test name
Test status
Simulation time 8615085608 ps
CPU time 128.56 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 01:55:00 PM PST 23
Peak memory 248652 kb
Host smart-0ae35630-f304-4e54-bdee-2b6c5cd738a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108280571261438688190728828001596029199791701992617298515965707773599207992259 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.kmac_error.108280571261438688190728828001596029199791701992617298515965707773599207992259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.3339423749169686199325267283235537319451264275375179733283819376706816527676
Short name T836
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.3 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 01:52:58 PM PST 23
Peak memory 207536 kb
Host smart-d77c95a2-14b5-4f62-a425-fd4362495366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339423749169686199325267283235537319451264275375179733283819376706816527676 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.kmac_key_error.3339423749169686199325267283235537319451264275375179733283819376706816527676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.23427078434854513813266306665103197279696842499369115187482496403240679936931
Short name T691
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:52:54 PM PST 23
Finished Nov 22 01:52:57 PM PST 23
Peak memory 215776 kb
Host smart-01e5ca90-f443-4b5e-8d35-f56ecea55acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23427078434854513813266306665103197279696842499369115187482496403240679936931 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.kmac_lc_escalation.23427078434854513813266306665103197279696842499369115187482496403240679936931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.86566185226746970242669305206312256358278395690185774654317507220308399503427
Short name T937
Test name
Test status
Simulation time 45517522529 ps
CPU time 721.59 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 02:04:55 PM PST 23
Peak memory 288384 kb
Host smart-4926f779-22f8-43e2-8cbd-7fc1c1baf253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86566185226746970242669305206312256358278395690185774654317507220308399503427 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.8656618522674697024266930520631225635827839569018577465431750722030839
9503427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.64819315283225147143031218592373770529714082805672689517771778142056856546471
Short name T883
Test name
Test status
Simulation time 5640716546 ps
CPU time 72.61 seconds
Started Nov 22 01:52:39 PM PST 23
Finished Nov 22 01:53:57 PM PST 23
Peak memory 227544 kb
Host smart-d677981a-3de8-4322-9be0-67b2fe6c40b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64819315283225147143031218592373770529714082805672689517771778142056856546471 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.kmac_mubi.64819315283225147143031218592373770529714082805672689517771778142056856546471 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.95787983724224481472500133830282783066836382798671081415124249492569217999430
Short name T874
Test name
Test status
Simulation time 7733092664 ps
CPU time 112.96 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:54:42 PM PST 23
Peak memory 228232 kb
Host smart-83d64d36-aa6b-4610-a961-45192e063921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95787983724224481472500133830282783066836382798671081415124249492569217999430 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.kmac_sideload.95787983724224481472500133830282783066836382798671081415124249492569217999430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.70587703944710803161632754214646626430403044078865573995379117571513656644507
Short name T753
Test name
Test status
Simulation time 1554463522 ps
CPU time 17.82 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 01:53:09 PM PST 23
Peak memory 215892 kb
Host smart-6dd3806a-ed42-4652-9e15-8dc7375e4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70587703944710803161632754214646626430403044078865573995379117571513656644507 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.kmac_smoke.70587703944710803161632754214646626430403044078865573995379117571513656644507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.10043379412340925898856434928090004875076422562912310810697387541201350484874
Short name T78
Test name
Test status
Simulation time 41434001626 ps
CPU time 627.72 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 321736 kb
Host smart-f1472986-738e-4aeb-8fae-3fcd94afe9b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=10043379412340925898856434928090004875076422562912310810697387541201350484874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_str
ess_all.10043379412340925898856434928090004875076422562912310810697387541201350484874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.28277321097453849617133597329503234405926254974155602859184345149709592411126
Short name T761
Test name
Test status
Simulation time 298812853 ps
CPU time 4.39 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:52:51 PM PST 23
Peak memory 215876 kb
Host smart-7ba7cc0f-0524-4e5a-9025-5e73a2d3bfce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277321097453849617133597329503234405926254974155602
859184345149709592411126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac.282773210974538496171335973295032344059
26254974155602859184345149709592411126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.63125456949586905812225403399422102603404111392653837341854765725990886121333
Short name T421
Test name
Test status
Simulation time 289902210 ps
CPU time 4.23 seconds
Started Nov 22 01:52:57 PM PST 23
Finished Nov 22 01:53:02 PM PST 23
Peak memory 215876 kb
Host smart-0b76886a-e314-4981-9069-8ba77ac88358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63125456949586905812225403399422102603404111392653837
341854765725990886121333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.6312545694958690581222540339942
2102603404111392653837341854765725990886121333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.55076712781232070884468117252482425247304237775423368467416156692405029928308
Short name T615
Test name
Test status
Simulation time 115269125226 ps
CPU time 1689.86 seconds
Started Nov 22 01:52:51 PM PST 23
Finished Nov 22 02:21:03 PM PST 23
Peak memory 390280 kb
Host smart-1f15b746-0165-4015-8436-0da768760256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55076712781232070884468117252482425247304237775423368467416156692405029928308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
kmac_test_vectors_sha3_224.55076712781232070884468117252482425247304237775423368467416156692405029928308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.34263893654364514329846721674637090787401310674694243167410484385504127938424
Short name T685
Test name
Test status
Simulation time 107886220004 ps
CPU time 1631.86 seconds
Started Nov 22 01:52:46 PM PST 23
Finished Nov 22 02:20:02 PM PST 23
Peak memory 370096 kb
Host smart-879a8695-a96e-4a15-9e55-f2607964568c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=34263893654364514329846721674637090787401310674694243167410484385504127938424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
kmac_test_vectors_sha3_256.34263893654364514329846721674637090787401310674694243167410484385504127938424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.1190249945278346945834769168302570902050476382181128661307766361877790501788
Short name T272
Test name
Test status
Simulation time 83070954242 ps
CPU time 1249.85 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 02:13:42 PM PST 23
Peak memory 332848 kb
Host smart-5442763a-06ee-42ef-9045-44e949e8bac5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1190249945278346945834769168302570902050476382181128661307766361877790501788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.k
mac_test_vectors_sha3_384.1190249945278346945834769168302570902050476382181128661307766361877790501788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.114424610107359312244301447536227884365145855570025884658064103532339656632597
Short name T760
Test name
Test status
Simulation time 58503507926 ps
CPU time 856.57 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 02:07:09 PM PST 23
Peak memory 296000 kb
Host smart-2390e35d-57aa-4c65-afd4-31a59cf235a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114424610107359312244301447536227884365145855570025884658064103532339656632597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.kmac_test_vectors_sha3_512.114424610107359312244301447536227884365145855570025884658064103532339656632597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.10223637253728333981670639320081408290499058371996533235569606708644254522799
Short name T670
Test name
Test status
Simulation time 307766781661 ps
CPU time 4480.19 seconds
Started Nov 22 01:52:49 PM PST 23
Finished Nov 22 03:07:33 PM PST 23
Peak memory 653112 kb
Host smart-6deff8f3-65f5-4008-b9b4-a58952953888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=10223637253728333981670639320081408290499058371996533235569606708644254522799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.kmac_test_vectors_shake_128.10223637253728333981670639320081408290499058371996533235569606708644254522799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.3358886882144582231029675037352095810651296196300599722650089171329054699610
Short name T1056
Test name
Test status
Simulation time 258047411562 ps
CPU time 3639.08 seconds
Started Nov 22 01:52:47 PM PST 23
Finished Nov 22 02:53:30 PM PST 23
Peak memory 556108 kb
Host smart-f1f82149-2eab-4327-b61d-a2ce18bf840e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3358886882144582231029675037352095810651296196300599722650089171329054699610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.kmac_test_vectors_shake_256.3358886882144582231029675037352095810651296196300599722650089171329054699610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.113704926955273112431677079777082134990144949967303947609075211398239482383315
Short name T825
Test name
Test status
Simulation time 21118646 ps
CPU time 0.74 seconds
Started Nov 22 01:53:01 PM PST 23
Finished Nov 22 01:53:03 PM PST 23
Peak memory 205212 kb
Host smart-6ae0f294-008b-47b3-ba89-a4fa3f65b412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113704926955273112431677079777082134990144949967303947609075211398239482383315 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.113704926955273112431677079777082134990144949967303947609075211398239482383315 +enable_masking=0
+sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.4301417451496363216025876310509696534957471896759515082714073330401943767167
Short name T527
Test name
Test status
Simulation time 5659537824 ps
CPU time 73.46 seconds
Started Nov 22 01:53:03 PM PST 23
Finished Nov 22 01:54:18 PM PST 23
Peak memory 227376 kb
Host smart-df99dfee-758b-4978-ad43-2db9f7380681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4301417451496363216025876310509696534957471896759515082714073330401943767167 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.kmac_app.4301417451496363216025876310509696534957471896759515082714073330401943767167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.55842252416518356228299340001407873805808626168355970074944193087986102877190
Short name T606
Test name
Test status
Simulation time 7615861459 ps
CPU time 81.56 seconds
Started Nov 22 01:52:59 PM PST 23
Finished Nov 22 01:54:21 PM PST 23
Peak memory 226012 kb
Host smart-151c6051-b761-4800-ae25-bb2db3968a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55842252416518356228299340001407873805808626168355970074944193087986102877190 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_app_with_partial_data.55842252416518356228299340001407873805808626168355970074944193087986102877190 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.24828642540209530342250611221931851573482097323065861163347407658158263736825
Short name T427
Test name
Test status
Simulation time 14812750312 ps
CPU time 250.18 seconds
Started Nov 22 01:52:41 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 225568 kb
Host smart-6167ef95-34aa-4dc6-a8f3-54c42cc54629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24828642540209530342250611221931851573482097323065861163347407658158263736825 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.kmac_burst_write.24828642540209530342250611221931851573482097323065861163347407658158263736825 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.33981632843462910741141321367510494093211230898948356655238561784047156527020
Short name T472
Test name
Test status
Simulation time 2342046507 ps
CPU time 33.01 seconds
Started Nov 22 01:53:01 PM PST 23
Finished Nov 22 01:53:35 PM PST 23
Peak memory 223748 kb
Host smart-52a59226-ad95-4a36-b8b7-e5c70943876f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33981632843462910741141321367510494093211230898948356655238561784047156527020 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.kmac_edn_timeout_error.33981632843462910741141321367510494093211230898948356655238561784047156527020 +enable_masking=0
+sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.114487023990464976569675621491190653034519311321424980654999012466040763521135
Short name T779
Test name
Test status
Simulation time 2211297553 ps
CPU time 31.49 seconds
Started Nov 22 01:52:57 PM PST 23
Finished Nov 22 01:53:30 PM PST 23
Peak memory 223976 kb
Host smart-639ebe0f-8345-4fef-8087-910c40e87736
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=114487023990464976569675621491190653034519311321424980654999012466040763521135 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.114487023990464976569675621491190653034519311321424980654999012466040763521135 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.71364034544641683462601397650091702703288282941209034269081760067707564040296
Short name T758
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.61 seconds
Started Nov 22 01:53:31 PM PST 23
Finished Nov 22 01:53:50 PM PST 23
Peak memory 216940 kb
Host smart-6316b389-1481-4005-a97b-88a4771cbb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71364034544641683462601397650091702703288282941209034269081760067707564040296 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.kmac_entropy_ready_error.71364034544641683462601397650091702703288282941209034269081760067707564040296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.1409549435127983769210221666881459446577369522917737569782869605239109007551
Short name T351
Test name
Test status
Simulation time 6743332725 ps
CPU time 77.93 seconds
Started Nov 22 01:53:03 PM PST 23
Finished Nov 22 01:54:22 PM PST 23
Peak memory 227028 kb
Host smart-f71a39ad-68f8-4129-bce0-c69248745362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409549435127983769210221666881459446577369522917737569782869605239109007551 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.kmac_entropy_refresh.1409549435127983769210221666881459446577369522917737569782869605239109007551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.12604744664096716702149171862585953643514750875518791653801065585117547098011
Short name T485
Test name
Test status
Simulation time 8615085608 ps
CPU time 125.08 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 01:54:54 PM PST 23
Peak memory 248564 kb
Host smart-dd9ff854-9abd-47cc-b430-ae6e1af24551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12604744664096716702149171862585953643514750875518791653801065585117547098011 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.kmac_error.12604744664096716702149171862585953643514750875518791653801065585117547098011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.67368960864775348747191049368025251839194971072989423058247466448270696960813
Short name T36
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.33 seconds
Started Nov 22 01:52:52 PM PST 23
Finished Nov 22 01:52:59 PM PST 23
Peak memory 207556 kb
Host smart-a9303728-a484-45c2-9071-2d90c8ee76f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67368960864775348747191049368025251839194971072989423058247466448270696960813 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.kmac_key_error.67368960864775348747191049368025251839194971072989423058247466448270696960813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.71247487288249104651625319591725317583871745962680020366364570866562846502693
Short name T345
Test name
Test status
Simulation time 58171921 ps
CPU time 1.21 seconds
Started Nov 22 01:52:59 PM PST 23
Finished Nov 22 01:53:01 PM PST 23
Peak memory 215764 kb
Host smart-f8e6c061-d405-488b-8263-bfefc166d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71247487288249104651625319591725317583871745962680020366364570866562846502693 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.kmac_lc_escalation.71247487288249104651625319591725317583871745962680020366364570866562846502693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.20844649628898940343655843353725634330849362923474986061141185735242181001509
Short name T755
Test name
Test status
Simulation time 45517522529 ps
CPU time 712.63 seconds
Started Nov 22 01:52:45 PM PST 23
Finished Nov 22 02:04:42 PM PST 23
Peak memory 288372 kb
Host smart-c2c6d98d-5cec-4234-a790-07bb69b86036
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20844649628898940343655843353725634330849362923474986061141185735242181001509 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2084464962889894034365584335372563433084936292347498606114118573524218
1001509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.5933404013237157240720004685347597237572207356648174420913347608861519751021
Short name T266
Test name
Test status
Simulation time 5640716546 ps
CPU time 72.14 seconds
Started Nov 22 01:52:59 PM PST 23
Finished Nov 22 01:54:12 PM PST 23
Peak memory 227680 kb
Host smart-d852d180-d448-4ecc-a05b-f3c8908c8f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5933404013237157240720004685347597237572207356648174420913347608861519751021 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.kmac_mubi.5933404013237157240720004685347597237572207356648174420913347608861519751021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.24137814532306686106831780062735777512859443536640582949854166917768113488505
Short name T1049
Test name
Test status
Simulation time 7733092664 ps
CPU time 111.56 seconds
Started Nov 22 01:52:50 PM PST 23
Finished Nov 22 01:54:45 PM PST 23
Peak memory 228180 kb
Host smart-872331bc-5e95-4ff8-8b04-5b592d0a332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24137814532306686106831780062735777512859443536640582949854166917768113488505 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.kmac_sideload.24137814532306686106831780062735777512859443536640582949854166917768113488505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.114186850450344145140649895117390767906679770848643341134188462077894691142108
Short name T475
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.12 seconds
Started Nov 22 01:52:42 PM PST 23
Finished Nov 22 01:53:05 PM PST 23
Peak memory 215872 kb
Host smart-b272cf4f-2897-474e-ac1e-df87267486c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114186850450344145140649895117390767906679770848643341134188462077894691142108 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.kmac_smoke.114186850450344145140649895117390767906679770848643341134188462077894691142108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.56511389103712915302336296756355956977482895432524885489396081960840644845235
Short name T1014
Test name
Test status
Simulation time 41434001626 ps
CPU time 603.73 seconds
Started Nov 22 01:53:20 PM PST 23
Finished Nov 22 02:03:28 PM PST 23
Peak memory 321676 kb
Host smart-73e7beca-7813-4153-9d09-bd9465d803e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=56511389103712915302336296756355956977482895432524885489396081960840644845235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_str
ess_all.56511389103712915302336296756355956977482895432524885489396081960840644845235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.75232567196289804007016786146157804867972177775808625891704820885515772030436
Short name T740
Test name
Test status
Simulation time 298812853 ps
CPU time 4.26 seconds
Started Nov 22 01:53:23 PM PST 23
Finished Nov 22 01:53:29 PM PST 23
Peak memory 215184 kb
Host smart-98ad44c4-0713-4eb0-80a4-876e7e6edb28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75232567196289804007016786146157804867972177775808625
891704820885515772030436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac.752325671962898040070167861461578048679
72177775808625891704820885515772030436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.51055795695969122146954231920836653116178660779950365961259096879699601368574
Short name T75
Test name
Test status
Simulation time 289902210 ps
CPU time 4.05 seconds
Started Nov 22 01:53:02 PM PST 23
Finished Nov 22 01:53:07 PM PST 23
Peak memory 215692 kb
Host smart-d416164d-3757-431e-bba4-320dcb6b422c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51055795695969122146954231920836653116178660779950365
961259096879699601368574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.5105579569596912214695423192083
6653116178660779950365961259096879699601368574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.84751820536890563468775795943935223314397342185880070270533281311523846352987
Short name T599
Test name
Test status
Simulation time 115269125226 ps
CPU time 1813.87 seconds
Started Nov 22 01:52:35 PM PST 23
Finished Nov 22 02:22:56 PM PST 23
Peak memory 390332 kb
Host smart-4dad6ba3-7778-497f-853d-2988e4aa5b25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=84751820536890563468775795943935223314397342185880070270533281311523846352987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
kmac_test_vectors_sha3_224.84751820536890563468775795943935223314397342185880070270533281311523846352987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.65000348912307446804622071789092275125495911747132922873290314399585558136372
Short name T67
Test name
Test status
Simulation time 107886220004 ps
CPU time 1650.68 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 02:20:27 PM PST 23
Peak memory 369992 kb
Host smart-1e191ed3-dd2e-4079-8b70-188bd1f82f59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=65000348912307446804622071789092275125495911747132922873290314399585558136372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
kmac_test_vectors_sha3_256.65000348912307446804622071789092275125495911747132922873290314399585558136372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.59421850566077826301043475056024173487452148626232150687824808980646729918271
Short name T712
Test name
Test status
Simulation time 83070954242 ps
CPU time 1257.11 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 02:13:53 PM PST 23
Peak memory 332336 kb
Host smart-bb6d6efd-c9cd-4bcc-ab78-1dee3b4eae3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59421850566077826301043475056024173487452148626232150687824808980646729918271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
kmac_test_vectors_sha3_384.59421850566077826301043475056024173487452148626232150687824808980646729918271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.5438148391831252960710825374983014508847083965805741979187478747659162388495
Short name T969
Test name
Test status
Simulation time 58503507926 ps
CPU time 843.59 seconds
Started Nov 22 01:53:02 PM PST 23
Finished Nov 22 02:07:07 PM PST 23
Peak memory 295912 kb
Host smart-99f214fa-5556-4ed8-ad5c-f6c1bc3c5581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=5438148391831252960710825374983014508847083965805741979187478747659162388495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.k
mac_test_vectors_sha3_512.5438148391831252960710825374983014508847083965805741979187478747659162388495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.88285356425743146337687839334023492246179735325104688282340384638332428058841
Short name T967
Test name
Test status
Simulation time 307766781661 ps
CPU time 4533.42 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 03:08:30 PM PST 23
Peak memory 653224 kb
Host smart-246d2ad2-a8cf-455e-a1a3-876b0d9889e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=88285356425743146337687839334023492246179735325104688282340384638332428058841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.kmac_test_vectors_shake_128.88285356425743146337687839334023492246179735325104688282340384638332428058841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.32098526527401790854961920859982815626427268386088848596349738780302615788721
Short name T480
Test name
Test status
Simulation time 258047411562 ps
CPU time 3850.25 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 02:57:29 PM PST 23
Peak memory 556364 kb
Host smart-8c87de5e-9a07-4389-baa5-bdec791d0096
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=32098526527401790854961920859982815626427268386088848596349738780302615788721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.kmac_test_vectors_shake_256.32098526527401790854961920859982815626427268386088848596349738780302615788721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.46357983998728237606514987935339636399977426996438545881728711425645234624621
Short name T617
Test name
Test status
Simulation time 21118646 ps
CPU time 0.77 seconds
Started Nov 22 01:53:23 PM PST 23
Finished Nov 22 01:53:26 PM PST 23
Peak memory 204568 kb
Host smart-f16b7c91-3f69-4891-a9f3-78a068ef3ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46357983998728237606514987935339636399977426996438545881728711425645234624621 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.kmac_alert_test.46357983998728237606514987935339636399977426996438545881728711425645234624621 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.34492181388135949892430783002961485517881270468450095396807050431373096879287
Short name T146
Test name
Test status
Simulation time 5659537824 ps
CPU time 75.99 seconds
Started Nov 22 01:53:17 PM PST 23
Finished Nov 22 01:54:39 PM PST 23
Peak memory 227392 kb
Host smart-4958e611-4699-4b14-bbe7-b1ff334b413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34492181388135949892430783002961485517881270468450095396807050431373096879287 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.kmac_app.34492181388135949892430783002961485517881270468450095396807050431373096879287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.52777696507426665227593581683677106474065129313946322008956657063888799236677
Short name T808
Test name
Test status
Simulation time 7615861459 ps
CPU time 80.54 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 01:54:15 PM PST 23
Peak memory 225988 kb
Host smart-69f6ec6b-4c96-4f19-a010-f6d9c6e2cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52777696507426665227593581683677106474065129313946322008956657063888799236677 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_app_with_partial_data.52777696507426665227593581683677106474065129313946322008956657063888799236677 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.108454969743821226918974884569100103913903642180045119915968752186133296249354
Short name T574
Test name
Test status
Simulation time 14812750312 ps
CPU time 250.07 seconds
Started Nov 22 01:53:19 PM PST 23
Finished Nov 22 01:57:34 PM PST 23
Peak memory 225576 kb
Host smart-9183a71a-cb71-4119-ba25-eacb2d2120cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108454969743821226918974884569100103913903642180045119915968752186133296249354 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.kmac_burst_write.108454969743821226918974884569100103913903642180045119915968752186133296249354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.38516841132284024433212753495779483264187398611268394739905157959793218496661
Short name T251
Test name
Test status
Simulation time 2342046507 ps
CPU time 35.29 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 01:53:32 PM PST 23
Peak memory 223888 kb
Host smart-1acad8b9-ad22-4587-8838-039a6ada16df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=38516841132284024433212753495779483264187398611268394739905157959793218496661 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.kmac_edn_timeout_error.38516841132284024433212753495779483264187398611268394739905157959793218496661 +enable_masking=0
+sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.3592824601715762054169261311553175092755119279094407637946886445314365442218
Short name T809
Test name
Test status
Simulation time 2211297553 ps
CPU time 30.58 seconds
Started Nov 22 01:53:42 PM PST 23
Finished Nov 22 01:54:13 PM PST 23
Peak memory 223896 kb
Host smart-c5cf716e-8e06-40e0-98ae-5ddd48c6e714
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3592824601715762054169261311553175092755119279094407637946886445314365442218 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.kmac_entropy_mode_error.3592824601715762054169261311553175092755119279094407637946886445314365442218 +enable_masking=0
+sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.103547344180861297440854439796987760934476466307446933190022881854091703686317
Short name T1065
Test name
Test status
Simulation time 2782989408 ps
CPU time 18.32 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 01:53:13 PM PST 23
Peak memory 216880 kb
Host smart-8e50ed73-dba1-4ab5-85e5-95711a867c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103547344180861297440854439796987760934476466307446933190022881854091703686317 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.kmac_entropy_ready_error.103547344180861297440854439796987760934476466307446933190022881854091703686317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.88755415865678066373621817030672470645078487397393839523643110560904182065716
Short name T412
Test name
Test status
Simulation time 6743332725 ps
CPU time 76.3 seconds
Started Nov 22 01:53:14 PM PST 23
Finished Nov 22 01:54:34 PM PST 23
Peak memory 227000 kb
Host smart-b5263e59-7f2c-4eeb-82d2-0972ec8d965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88755415865678066373621817030672470645078487397393839523643110560904182065716 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.kmac_entropy_refresh.88755415865678066373621817030672470645078487397393839523643110560904182065716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.82396111756185819634207002994177931333496390792930854587267106372114163246885
Short name T953
Test name
Test status
Simulation time 8615085608 ps
CPU time 136.83 seconds
Started Nov 22 01:52:59 PM PST 23
Finished Nov 22 01:55:17 PM PST 23
Peak memory 248608 kb
Host smart-15c85f9e-5e6a-4551-93d7-1f4018b2d8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82396111756185819634207002994177931333496390792930854587267106372114163246885 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.kmac_error.82396111756185819634207002994177931333496390792930854587267106372114163246885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.11021646100834636295335595539750676491586130935975782664952002420812928936614
Short name T873
Test name
Test status
Simulation time 1579963318 ps
CPU time 5.23 seconds
Started Nov 22 01:52:56 PM PST 23
Finished Nov 22 01:53:03 PM PST 23
Peak memory 207556 kb
Host smart-c86da792-746e-4895-9e96-7cc07793b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11021646100834636295335595539750676491586130935975782664952002420812928936614 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.kmac_key_error.11021646100834636295335595539750676491586130935975782664952002420812928936614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.42358632066330474992985061884248283588096415172541837274854572311461961449158
Short name T730
Test name
Test status
Simulation time 58171921 ps
CPU time 1.24 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 01:52:56 PM PST 23
Peak memory 215796 kb
Host smart-3e243d9b-5f90-46ff-8008-9273c047d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42358632066330474992985061884248283588096415172541837274854572311461961449158 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.kmac_lc_escalation.42358632066330474992985061884248283588096415172541837274854572311461961449158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.9784477634359296333272562428571848831940640880572648412252186682315645323857
Short name T867
Test name
Test status
Simulation time 45517522529 ps
CPU time 729.82 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 02:05:04 PM PST 23
Peak memory 288328 kb
Host smart-7f060287-f2d5-4529-aaa2-d6bf841e0faa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9784477634359296333272562428571848831940640880572648412252186682315645323857 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.97844776343592963332725624285718488319406408805726484122521866823156453
23857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.38742007824466086770218125687662878108309847738118383277428291817315526709404
Short name T858
Test name
Test status
Simulation time 5640716546 ps
CPU time 78.79 seconds
Started Nov 22 01:53:03 PM PST 23
Finished Nov 22 01:54:22 PM PST 23
Peak memory 227696 kb
Host smart-a09fad0c-c457-48a6-b9e5-5aa69b0f89ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38742007824466086770218125687662878108309847738118383277428291817315526709404 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.kmac_mubi.38742007824466086770218125687662878108309847738118383277428291817315526709404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.19108481375411731263096696247029543142334560667382471261630544718508043697837
Short name T367
Test name
Test status
Simulation time 7733092664 ps
CPU time 110.54 seconds
Started Nov 22 01:53:21 PM PST 23
Finished Nov 22 01:55:14 PM PST 23
Peak memory 228120 kb
Host smart-fe288079-bd10-4ff7-9fc5-5ebb2ea5b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19108481375411731263096696247029543142334560667382471261630544718508043697837 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.kmac_sideload.19108481375411731263096696247029543142334560667382471261630544718508043697837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.133331012698654451675237569392702202490412310731726418976765621185811228365
Short name T169
Test name
Test status
Simulation time 1554463522 ps
CPU time 18.61 seconds
Started Nov 22 01:53:15 PM PST 23
Finished Nov 22 01:53:40 PM PST 23
Peak memory 215956 kb
Host smart-b2549068-6398-4e99-8bf2-ecab96812362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133331012698654451675237569392702202490412310731726418976765621185811228365 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.kmac_smoke.133331012698654451675237569392702202490412310731726418976765621185811228365 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.92167312587780015512443416182870862059084777300298234999596904887637523061670
Short name T598
Test name
Test status
Simulation time 41434001626 ps
CPU time 617.99 seconds
Started Nov 22 01:53:02 PM PST 23
Finished Nov 22 02:03:21 PM PST 23
Peak memory 321660 kb
Host smart-89dc6b1c-0416-4e90-bdc1-a30469fe024a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=92167312587780015512443416182870862059084777300298234999596904887637523061670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_str
ess_all.92167312587780015512443416182870862059084777300298234999596904887637523061670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.91239521081989216343051126239383445943968102024866543243808967283171130405863
Short name T988
Test name
Test status
Simulation time 298812853 ps
CPU time 4.14 seconds
Started Nov 22 01:53:29 PM PST 23
Finished Nov 22 01:53:35 PM PST 23
Peak memory 215820 kb
Host smart-69e46b9b-711c-4744-a807-559fbd917218
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91239521081989216343051126239383445943968102024866543
243808967283171130405863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac.912395210819892163430511262393834459439
68102024866543243808967283171130405863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.73229308196008389474669608943647405268817600332093394037386789823830824760754
Short name T800
Test name
Test status
Simulation time 289902210 ps
CPU time 4.09 seconds
Started Nov 22 01:52:55 PM PST 23
Finished Nov 22 01:53:00 PM PST 23
Peak memory 215292 kb
Host smart-3fd61564-f1dd-4ac8-b246-36b61ac3e8e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73229308196008389474669608943647405268817600332093394
037386789823830824760754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.7322930819600838947466960894364
7405268817600332093394037386789823830824760754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.95118940506028685707523770716907092006828566149976613863804074533097556862956
Short name T898
Test name
Test status
Simulation time 115269125226 ps
CPU time 1740.28 seconds
Started Nov 22 01:52:59 PM PST 23
Finished Nov 22 02:22:00 PM PST 23
Peak memory 390548 kb
Host smart-4e47aaa6-e021-41be-8679-a68074e6a690
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=95118940506028685707523770716907092006828566149976613863804074533097556862956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
kmac_test_vectors_sha3_224.95118940506028685707523770716907092006828566149976613863804074533097556862956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.47734705967661617992982080324095665350074032996297213241500132081251619585081
Short name T1020
Test name
Test status
Simulation time 107886220004 ps
CPU time 1583.07 seconds
Started Nov 22 01:53:21 PM PST 23
Finished Nov 22 02:19:47 PM PST 23
Peak memory 369940 kb
Host smart-31537e71-be9b-443c-a36a-9b056964584c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=47734705967661617992982080324095665350074032996297213241500132081251619585081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
kmac_test_vectors_sha3_256.47734705967661617992982080324095665350074032996297213241500132081251619585081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.111593041269907561202910557134258377015218112813858521525945596994136117585902
Short name T220
Test name
Test status
Simulation time 83070954242 ps
CPU time 1211.72 seconds
Started Nov 22 01:52:56 PM PST 23
Finished Nov 22 02:13:09 PM PST 23
Peak memory 332944 kb
Host smart-5d6529e9-c1da-452d-b44c-c4490704dd84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=111593041269907561202910557134258377015218112813858521525945596994136117585902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.kmac_test_vectors_sha3_384.111593041269907561202910557134258377015218112813858521525945596994136117585902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.3834930846567951514276851961827576725812570993265651953822311964163352793382
Short name T928
Test name
Test status
Simulation time 58503507926 ps
CPU time 893.94 seconds
Started Nov 22 01:52:48 PM PST 23
Finished Nov 22 02:07:46 PM PST 23
Peak memory 295788 kb
Host smart-8d5848ac-0618-4478-a519-ca75231839fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3834930846567951514276851961827576725812570993265651953822311964163352793382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.k
mac_test_vectors_sha3_512.3834930846567951514276851961827576725812570993265651953822311964163352793382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.66356788494399666621168602994853989951172250136922844195695103991526009361954
Short name T256
Test name
Test status
Simulation time 307766781661 ps
CPU time 4522.31 seconds
Started Nov 22 01:53:16 PM PST 23
Finished Nov 22 03:08:45 PM PST 23
Peak memory 653240 kb
Host smart-a70d534c-e91a-4046-8db6-fbb7dbfa53ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=66356788494399666621168602994853989951172250136922844195695103991526009361954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.kmac_test_vectors_shake_128.66356788494399666621168602994853989951172250136922844195695103991526009361954 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.107048563979319787332232285028872816536782361554155247549020095588304542017216
Short name T160
Test name
Test status
Simulation time 258047411562 ps
CPU time 3525.47 seconds
Started Nov 22 01:52:53 PM PST 23
Finished Nov 22 02:51:40 PM PST 23
Peak memory 556156 kb
Host smart-ba584b87-15c0-4a85-b591-c6154ae2674e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=107048563979319787332232285028872816536782361554155247549020095588304542017216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.kmac_test_vectors_shake_256.107048563979319787332232285028872816536782361554155247549020095588304542017216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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