Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100810014	1			T53	8		T54	5		T55	1
all_values[1]	100810014	1			T53	8		T54	5		T55	1
all_values[2]	100810014	1			T53	8		T54	5		T55	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599303

1

T53

13

T54

4

T55

3

auto[1]

301830739

1

T53

11

T54

11

T61

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300884661

1

T53

12

T54

9

T55

3

auto[1]

1545381

1

T53

12

T54

6

T61

21

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	168791	1			T53	4		T55	1		T91	2
all_values[0]	auto[0]	auto[1]	2372	1			T53	2		T61	3		T91	2
all_values[0]	auto[1]	auto[0]	100126096	1			T54	3		T61	1		T91	3
all_values[0]	auto[1]	auto[1]	512755	1			T53	2		T54	2		T61	4
all_values[1]	auto[0]	auto[0]	212712	1			T53	1		T54	1		T55	1
all_values[1]	auto[0]	auto[1]	1829	1			T61	4		T91	2		T94	3
all_values[1]	auto[1]	auto[0]	100082175	1			T53	3		T54	2		T61	1
all_values[1]	auto[1]	auto[1]	513298	1			T53	4		T54	2		T61	3
all_values[2]	auto[0]	auto[0]	211866	1			T53	2		T54	1		T55	1
all_values[2]	auto[0]	auto[1]	1733	1			T53	4		T54	2		T61	2
all_values[2]	auto[1]	auto[0]	100083021	1			T53	2		T54	2		T61	1
all_values[2]	auto[1]	auto[1]	513394	1			T61	5		T94	3		T151	2