Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
357514 |
1 |
|
|
T4 |
294 |
|
T5 |
780 |
|
T7 |
312 |
auto[1] |
343545 |
1 |
|
|
T14 |
292 |
|
T16 |
490 |
|
T17 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176481 |
1 |
|
|
T4 |
81 |
|
T5 |
206 |
|
T7 |
77 |
lower_val |
172550 |
1 |
|
|
T4 |
68 |
|
T5 |
164 |
|
T7 |
78 |
zero_val |
2044 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T7 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350373 |
1 |
|
|
T4 |
162 |
|
T5 |
370 |
|
T7 |
174 |
lower_val |
350678 |
1 |
|
|
T4 |
132 |
|
T5 |
410 |
|
T7 |
138 |
zero_val |
8 |
1 |
|
|
T19 |
2 |
|
T143 |
2 |
|
T144 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44828 |
1 |
|
|
T4 |
44 |
|
T5 |
107 |
|
T7 |
39 |
higher_val |
higher_val |
auto[1] |
43465 |
1 |
|
|
T14 |
29 |
|
T16 |
80 |
|
T17 |
3 |
higher_val |
lower_val |
auto[0] |
44924 |
1 |
|
|
T4 |
37 |
|
T5 |
99 |
|
T7 |
38 |
higher_val |
lower_val |
auto[1] |
43263 |
1 |
|
|
T14 |
46 |
|
T16 |
72 |
|
T17 |
1 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T19 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
44234 |
1 |
|
|
T4 |
42 |
|
T5 |
74 |
|
T7 |
43 |
lower_val |
higher_val |
auto[1] |
42369 |
1 |
|
|
T14 |
42 |
|
T16 |
48 |
|
T17 |
1 |
lower_val |
lower_val |
auto[0] |
44098 |
1 |
|
|
T4 |
26 |
|
T5 |
90 |
|
T7 |
35 |
lower_val |
lower_val |
auto[1] |
41848 |
1 |
|
|
T14 |
39 |
|
T16 |
68 |
|
T19 |
47 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T144 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
752 |
1 |
|
|
T7 |
1 |
|
T14 |
2 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
270 |
1 |
|
|
T14 |
2 |
|
T22 |
3 |
|
T145 |
2 |
zero_val |
lower_val |
auto[0] |
744 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T7 |
2 |
zero_val |
lower_val |
auto[1] |
278 |
1 |
|
|
T14 |
2 |
|
T22 |
1 |
|
T145 |
2 |