Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10350	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9034	1			T5	17		T7	31		T14	7
len_5001_7500	14675	1			T5	17		T7	75		T14	9
len_2501_5000	9277	1			T5	17		T7	13		T14	2
len_1025_2500	5406	1			T5	10		T7	9		T14	1
len_769_1024	6535	1			T4	32		T5	2		T7	1
len_513_768	6847	1			T4	40		T5	2		T7	2
len_257_512	21304	1			T4	42		T5	2		T7	2
len_0_256	260217	1			T4	33		T5	290		T7	23
len_keccak_block_sizes[72]	721	1			T5	2		T16	2		T19	2
len_keccak_block_sizes[104]	621	1			T5	2		T22	1		T44	3
len_keccak_block_sizes[136]	521	1			T5	2		T44	3		T45	3
len_keccak_block_sizes[144]	426	1			T5	2		T44	3		T45	3
len_keccak_block_sizes[168]	326	1			T44	3		T45	3		T145	3
len_1	772	1			T5	2		T16	2		T19	2
len_0	1256	1			T5	2		T7	4		T14	4