Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100810014	1			T53	8		T54	5		T55	1
all_pins[1]	100810014	1			T53	8		T54	5		T55	1
all_pins[2]	100810014	1			T53	8		T54	5		T55	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	241213858	1			T53	18		T54	12		T55	3
values[0x1]	61216184	1			T53	6		T54	3		T61	10
transitions[0x0=>0x1]	60782046	1			T53	4		T54	3		T61	2
transitions[0x1=>0x0]	60782070	1			T53	4		T54	3		T61	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100297259	1			T53	6		T54	3		T55	1
all_pins[0]	values[0x1]	512755	1			T53	2		T54	2		T61	4
all_pins[0]	transitions[0x0=>0x1]	219931	1			T54	2		T61	2		T94	3
all_pins[0]	transitions[0x1=>0x0]	60097150	1			T53	1		T91	1		T140	2
all_pins[1]	values[0x0]	40420040	1			T53	5		T54	5		T55	1
all_pins[1]	values[0x1]	60389974	1			T53	3		T61	2		T91	2
all_pins[1]	transitions[0x0=>0x1]	60250517	1			T53	3		T91	2		T151	2
all_pins[1]	transitions[0x1=>0x0]	173998	1			T53	1		T54	1		T61	2
all_pins[2]	values[0x0]	100496559	1			T53	7		T54	4		T55	1
all_pins[2]	values[0x1]	313455	1			T53	1		T54	1		T61	4
all_pins[2]	transitions[0x0=>0x1]	311598	1			T53	1		T54	1		T91	2
all_pins[2]	transitions[0x1=>0x0]	510922	1			T53	2		T54	2		T61	1