Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	659	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5822	1			T4	24		T7	19		T14	14
len_601_800	12851	1			T4	56		T7	49		T14	31
len_401_600	8444	1			T4	26		T7	42		T14	28
len_201_400	16588	1			T4	17		T7	20		T14	8
len_65_200	74752	1			T4	7		T7	8		T14	27
len_min_for_xof_require_squeeze	1022	1			T14	1		T22	1		T44	10
len_keccak_block_sizes[72]	759	1			T15	2		T22	1		T44	5
len_keccak_block_sizes[104]	775	1			T15	1		T44	5		T45	5
len_keccak_block_sizes[136]	766	1			T7	1		T14	1		T15	1
len_keccak_block_sizes[144]	298	1			T22	2		T44	5		T45	5
len_keccak_block_sizes[168]	276	1			T15	1		T44	5		T45	5
len_datapath_width	14394	1			T4	1		T7	2		T13	3
len_2_63	215689	1			T4	10		T5	390		T7	11
len_1	60	1			T162	3		T27	1		T163	1