Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10986164 |
1 |
|
|
T4 |
25019 |
|
T5 |
2730 |
|
T7 |
25064 |
auto[1] |
26142135 |
1 |
|
|
T4 |
36158 |
|
T5 |
19500 |
|
T7 |
36800 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
37007284 |
1 |
|
|
T4 |
61077 |
|
T5 |
22230 |
|
T7 |
61753 |
triple_byte_access |
40282 |
1 |
|
|
T4 |
25 |
|
T7 |
33 |
|
T14 |
28 |
halfword_access |
40538 |
1 |
|
|
T4 |
43 |
|
T7 |
34 |
|
T14 |
34 |
byte_access |
40195 |
1 |
|
|
T4 |
32 |
|
T7 |
44 |
|
T14 |
30 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10865149 |
1 |
|
|
T4 |
24919 |
|
T5 |
2730 |
|
T7 |
24953 |
auto[0] |
triple_byte_access |
40282 |
1 |
|
|
T4 |
25 |
|
T7 |
33 |
|
T14 |
28 |
auto[0] |
halfword_access |
40538 |
1 |
|
|
T4 |
43 |
|
T7 |
34 |
|
T14 |
34 |
auto[0] |
byte_access |
40195 |
1 |
|
|
T4 |
32 |
|
T7 |
44 |
|
T14 |
30 |
auto[1] |
word_access |
26142135 |
1 |
|
|
T4 |
36158 |
|
T5 |
19500 |
|
T7 |
36800 |