Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T53 7 T54 4 T61 7
all_values[1] 278 1 T53 7 T54 4 T61 7
all_values[2] 278 1 T53 7 T54 4 T61 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 467 1 T53 11 T54 3 T61 11
auto[1] 367 1 T53 10 T54 9 T61 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 317 1 T53 5 T54 8 T61 3
auto[1] 517 1 T53 16 T54 4 T61 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 483 1 T53 12 T54 9 T61 11
auto[1] 351 1 T53 9 T54 3 T61 10


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 64 1 T53 2 T91 1 T94 1
all_values[0] auto[0] auto[0] auto[1] 28 1 T53 2 T61 3 T152 1
all_values[0] auto[0] auto[1] auto[0] 37 1 T54 2 T91 2 T151 1
all_values[0] auto[0] auto[1] auto[1] 22 1 T54 1 T61 1 T94 1
all_values[0] auto[1] auto[0] auto[1] 70 1 T61 2 T91 3 T151 1
all_values[0] auto[1] auto[1] auto[1] 57 1 T53 3 T54 1 T61 1
all_values[1] auto[0] auto[0] auto[0] 51 1 T54 1 T61 2 T151 1
all_values[1] auto[0] auto[0] auto[1] 33 1 T94 2 T140 1 T151 1
all_values[1] auto[0] auto[1] auto[0] 43 1 T53 1 T54 2 T61 1
all_values[1] auto[0] auto[1] auto[1] 34 1 T53 2 T61 2 T91 1
all_values[1] auto[1] auto[0] auto[1] 69 1 T53 1 T61 2 T91 2
all_values[1] auto[1] auto[1] auto[1] 48 1 T53 3 T54 1 T91 2
all_values[2] auto[0] auto[0] auto[0] 70 1 T53 2 T54 2 T91 3
all_values[2] auto[0] auto[0] auto[1] 27 1 T53 3 T140 1 T152 1
all_values[2] auto[0] auto[1] auto[0] 52 1 T54 1 T94 1 T151 1
all_values[2] auto[0] auto[1] auto[1] 22 1 T61 2 T91 1 T94 1
all_values[2] auto[1] auto[0] auto[1] 55 1 T53 1 T61 2 T91 2
all_values[2] auto[1] auto[1] auto[1] 52 1 T53 1 T54 1 T61 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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